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authorHans Wennborg <hans@hanshq.net>2017-08-30 22:11:37 +0000
committerHans Wennborg <hans@hanshq.net>2017-08-30 22:11:37 +0000
commit92b6b153a4a2ef547d1cb12c497a18afd6e33fa1 (patch)
tree757c83ded5661034a930c824803317c2414e950e /test/CodeGen/PowerPC/inlineasm-i64-reg.ll
parentaa892fdd036014742dca7a42e49f14c49feb657c (diff)
Revert r312154 "Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding""
It caused PR34387: Assertion failed: (RegNo < NumRegs && "Attempting to access record for invalid register number!") > Issues identified by buildbots addressed since original review: > - Fixed ARMLoadStoreOptimizer bug exposed by this change in r311907. > - The pass no longer forwards COPYs to physical register uses, since > doing so can break code that implicitly relies on the physical > register number of the use. > - The pass no longer forwards COPYs to undef uses, since doing so > can break the machine verifier by creating LiveRanges that don't > end on a use (since the undef operand is not considered a use). > > [MachineCopyPropagation] Extend pass to do COPY source forwarding > > This change extends MachineCopyPropagation to do COPY source forwarding. > > This change also extends the MachineCopyPropagation pass to be able to > be run during register allocation, after physical registers have been > assigned, but before the virtual registers have been re-written, which > allows it to remove virtual register COPY LiveIntervals that become dead > through the forwarding of all of their uses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312178 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC/inlineasm-i64-reg.ll')
-rw-r--r--test/CodeGen/PowerPC/inlineasm-i64-reg.ll2
1 files changed, 1 insertions, 1 deletions
diff --git a/test/CodeGen/PowerPC/inlineasm-i64-reg.ll b/test/CodeGen/PowerPC/inlineasm-i64-reg.ll
index d06edd66b24..aa944a8d464 100644
--- a/test/CodeGen/PowerPC/inlineasm-i64-reg.ll
+++ b/test/CodeGen/PowerPC/inlineasm-i64-reg.ll
@@ -75,7 +75,7 @@ entry:
; CHECK-DAG: mr [[REG:[0-9]+]], 3
; CHECK-DAG: li 0, 1076
-; CHECK-DAG: stw 3,
+; CHECK: stw [[REG]],
; CHECK: #APP
; CHECK: sc