diff options
| author | Hal Finkel <hfinkel@anl.gov> | 2015-01-06 06:01:57 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2015-01-06 06:01:57 +0000 |
| commit | 10ae86584773a23574ecc26f750366f959e9d058 (patch) | |
| tree | 86fcb21ce6e712364ea5ab9873e4e9d404458acd /test/CodeGen/PowerPC/fp-to-int-to-fp.ll | |
| parent | 17395fa733494da19b3931c2957b870da78aa0b7 (diff) | |
[PowerPC] Improve int_to_fp(fp_to_int(x)) combining
The old target DAG combine that allowed for performing int_to_fp(fp_to_int(x))
without a load/store pair is updated here with support for unsigned integers,
and to support single-precision values without a third rounding step, on newer
cores with the appropriate instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225248 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC/fp-to-int-to-fp.ll')
| -rw-r--r-- | test/CodeGen/PowerPC/fp-to-int-to-fp.ll | 70 |
1 files changed, 70 insertions, 0 deletions
diff --git a/test/CodeGen/PowerPC/fp-to-int-to-fp.ll b/test/CodeGen/PowerPC/fp-to-int-to-fp.ll new file mode 100644 index 00000000000..f56b9b38ead --- /dev/null +++ b/test/CodeGen/PowerPC/fp-to-int-to-fp.ll @@ -0,0 +1,70 @@ +; RUN: llc -mcpu=a2 < %s | FileCheck %s -check-prefix=FPCVT +; RUN: llc -mcpu=ppc64 < %s | FileCheck %s -check-prefix=PPC64 +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +; Function Attrs: nounwind readnone +define float @fool(float %X) #0 { +entry: + %conv = fptosi float %X to i64 + %conv1 = sitofp i64 %conv to float + ret float %conv1 + +; FPCVT-LABEL: @fool +; FPCVT: fctidz [[REG1:[0-9]+]], 1 +; FPCVT: fcfids 1, [[REG1]] +; FPCVT: blr + +; PPC64-LABEL: @fool +; PPC64: fctidz [[REG1:[0-9]+]], 1 +; PPC64: fcfid [[REG2:[0-9]+]], [[REG1]] +; PPC64: frsp 1, [[REG2]] +; PPC64: blr +} + +; Function Attrs: nounwind readnone +define double @foodl(double %X) #0 { +entry: + %conv = fptosi double %X to i64 + %conv1 = sitofp i64 %conv to double + ret double %conv1 + +; FPCVT-LABEL: @foodl +; FPCVT: fctidz [[REG1:[0-9]+]], 1 +; FPCVT: fcfid 1, [[REG1]] +; FPCVT: blr + +; PPC64-LABEL: @foodl +; PPC64: fctidz [[REG1:[0-9]+]], 1 +; PPC64: fcfid 1, [[REG1]] +; PPC64: blr +} + +; Function Attrs: nounwind readnone +define float @fooul(float %X) #0 { +entry: + %conv = fptoui float %X to i64 + %conv1 = uitofp i64 %conv to float + ret float %conv1 + +; FPCVT-LABEL: @fooul +; FPCVT: fctiduz [[REG1:[0-9]+]], 1 +; FPCVT: fcfidus 1, [[REG1]] +; FPCVT: blr +} + +; Function Attrs: nounwind readnone +define double @fooudl(double %X) #0 { +entry: + %conv = fptoui double %X to i64 + %conv1 = uitofp i64 %conv to double + ret double %conv1 + +; FPCVT-LABEL: @fooudl +; FPCVT: fctiduz [[REG1:[0-9]+]], 1 +; FPCVT: fcfidu 1, [[REG1]] +; FPCVT: blr +} + +attributes #0 = { nounwind readnone } + |