diff options
author | Bill Schmidt <wschmidt@linux.vnet.ibm.com> | 2014-06-24 20:05:18 +0000 |
---|---|---|
committer | Bill Schmidt <wschmidt@linux.vnet.ibm.com> | 2014-06-24 20:05:18 +0000 |
commit | 808d878a968257a4a010ce2cd563f552dcf91147 (patch) | |
tree | f4f1d68f6f88ec3fe640d3c332f05b2b2b1f236a /test/CodeGen/PowerPC/fast-isel-conversion.ll | |
parent | 031ad1b930104d89494c7d76e20bfabc6901fabf (diff) |
[PPC64] Fix PR20071 (fctiduz generated for targets lacking that instruction)
PR20071 identifies a problem in PowerPC's fast-isel implementation for
floating-point conversion to integer. The fctiduz instruction was added in
Power ISA 2.06 (i.e., Power7 and later). However, this instruction is being
generated regardless of which 64-bit PowerPC target is selected.
The intent is for fast-isel to punt to DAG selection when this instruction is
not available. This patch implements that change. For testing purposes, the
existing fast-isel-conversion.ll test adds a RUN line for -mcpu=970 and tests
for the expected code generation. Additionally, the existing test
fast-isel-conversion-p5.ll was found to be incorrectly expecting the
unavailable instruction to be generated. I've removed these test variants
since we have adequate coverage in fast-isel-conversion.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211627 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC/fast-isel-conversion.ll')
-rw-r--r-- | test/CodeGen/PowerPC/fast-isel-conversion.ll | 104 |
1 files changed, 104 insertions, 0 deletions
diff --git a/test/CodeGen/PowerPC/fast-isel-conversion.ll b/test/CodeGen/PowerPC/fast-isel-conversion.ll index a31c31210c3..5e00675c039 100644 --- a/test/CodeGen/PowerPC/fast-isel-conversion.ll +++ b/test/CodeGen/PowerPC/fast-isel-conversion.ll @@ -1,15 +1,24 @@ ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64 +; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=970 | FileCheck %s --check-prefix=PPC970 + +;; Tests for 970 don't use -fast-isel-abort because we intentionally punt +;; to SelectionDAG in some cases. ; Test sitofp define void @sitofp_single_i64(i64 %a, float %b) nounwind ssp { entry: ; ELF64: sitofp_single_i64 +; PPC970: sitofp_single_i64 %b.addr = alloca float, align 4 %conv = sitofp i64 %a to float ; ELF64: std ; ELF64: lfd ; ELF64: fcfids +; PPC970: std +; PPC970: lfd +; PPC970: fcfid +; PPC970: frsp store float %conv, float* %b.addr, align 4 ret void } @@ -17,11 +26,16 @@ entry: define void @sitofp_single_i32(i32 %a, float %b) nounwind ssp { entry: ; ELF64: sitofp_single_i32 +; PPC970: sitofp_single_i32 %b.addr = alloca float, align 4 %conv = sitofp i32 %a to float ; ELF64: std ; ELF64: lfiwax ; ELF64: fcfids +; PPC970: std +; PPC970: lfd +; PPC970: fcfid +; PPC970: frsp store float %conv, float* %b.addr, align 4 ret void } @@ -29,12 +43,18 @@ entry: define void @sitofp_single_i16(i16 %a, float %b) nounwind ssp { entry: ; ELF64: sitofp_single_i16 +; PPC970: sitofp_single_i16 %b.addr = alloca float, align 4 %conv = sitofp i16 %a to float ; ELF64: extsh ; ELF64: std ; ELF64: lfd ; ELF64: fcfids +; PPC970: extsh +; PPC970: std +; PPC970: lfd +; PPC970: fcfid +; PPC970: frsp store float %conv, float* %b.addr, align 4 ret void } @@ -42,12 +62,18 @@ entry: define void @sitofp_single_i8(i8 %a) nounwind ssp { entry: ; ELF64: sitofp_single_i8 +; PPC970: sitofp_single_i8 %b.addr = alloca float, align 4 %conv = sitofp i8 %a to float ; ELF64: extsb ; ELF64: std ; ELF64: lfd ; ELF64: fcfids +; PPC970: extsb +; PPC970: std +; PPC970: lfd +; PPC970: fcfid +; PPC970: frsp store float %conv, float* %b.addr, align 4 ret void } @@ -55,11 +81,15 @@ entry: define void @sitofp_double_i32(i32 %a, double %b) nounwind ssp { entry: ; ELF64: sitofp_double_i32 +; PPC970: sitofp_double_i32 %b.addr = alloca double, align 8 %conv = sitofp i32 %a to double ; ELF64: std ; ELF64: lfiwax ; ELF64: fcfid +; PPC970: std +; PPC970: lfd +; PPC970: fcfid store double %conv, double* %b.addr, align 8 ret void } @@ -67,11 +97,15 @@ entry: define void @sitofp_double_i64(i64 %a, double %b) nounwind ssp { entry: ; ELF64: sitofp_double_i64 +; PPC970: sitofp_double_i64 %b.addr = alloca double, align 8 %conv = sitofp i64 %a to double ; ELF64: std ; ELF64: lfd ; ELF64: fcfid +; PPC970: std +; PPC970: lfd +; PPC970: fcfid store double %conv, double* %b.addr, align 8 ret void } @@ -79,12 +113,17 @@ entry: define void @sitofp_double_i16(i16 %a, double %b) nounwind ssp { entry: ; ELF64: sitofp_double_i16 +; PPC970: sitofp_double_i16 %b.addr = alloca double, align 8 %conv = sitofp i16 %a to double ; ELF64: extsh ; ELF64: std ; ELF64: lfd ; ELF64: fcfid +; PPC970: extsh +; PPC970: std +; PPC970: lfd +; PPC970: fcfid store double %conv, double* %b.addr, align 8 ret void } @@ -92,12 +131,17 @@ entry: define void @sitofp_double_i8(i8 %a, double %b) nounwind ssp { entry: ; ELF64: sitofp_double_i8 +; PPC970: sitofp_double_i8 %b.addr = alloca double, align 8 %conv = sitofp i8 %a to double ; ELF64: extsb ; ELF64: std ; ELF64: lfd ; ELF64: fcfid +; PPC970: extsb +; PPC970: std +; PPC970: lfd +; PPC970: fcfid store double %conv, double* %b.addr, align 8 ret void } @@ -107,11 +151,13 @@ entry: define void @uitofp_single_i64(i64 %a, float %b) nounwind ssp { entry: ; ELF64: uitofp_single_i64 +; PPC970: uitofp_single_i64 %b.addr = alloca float, align 4 %conv = uitofp i64 %a to float ; ELF64: std ; ELF64: lfd ; ELF64: fcfidus +; PPC970-NOT: fcfidus store float %conv, float* %b.addr, align 4 ret void } @@ -119,11 +165,14 @@ entry: define void @uitofp_single_i32(i32 %a, float %b) nounwind ssp { entry: ; ELF64: uitofp_single_i32 +; PPC970: uitofp_single_i32 %b.addr = alloca float, align 4 %conv = uitofp i32 %a to float ; ELF64: std ; ELF64: lfiwzx ; ELF64: fcfidus +; PPC970-NOT: lfiwzx +; PPC970-NOT: fcfidus store float %conv, float* %b.addr, align 4 ret void } @@ -131,12 +180,18 @@ entry: define void @uitofp_single_i16(i16 %a, float %b) nounwind ssp { entry: ; ELF64: uitofp_single_i16 +; PPC970: uitofp_single_i16 %b.addr = alloca float, align 4 %conv = uitofp i16 %a to float ; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48 ; ELF64: std ; ELF64: lfd ; ELF64: fcfidus +; PPC970: rlwinm {{[0-9]+}}, {{[0-9]+}}, 0, 16, 31 +; PPC970: std +; PPC970: lfd +; PPC970: fcfid +; PPC970: frsp store float %conv, float* %b.addr, align 4 ret void } @@ -144,12 +199,18 @@ entry: define void @uitofp_single_i8(i8 %a) nounwind ssp { entry: ; ELF64: uitofp_single_i8 +; PPC970: uitofp_single_i8 %b.addr = alloca float, align 4 %conv = uitofp i8 %a to float ; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56 ; ELF64: std ; ELF64: lfd ; ELF64: fcfidus +; PPC970: rlwinm {{[0-9]+}}, {{[0-9]+}}, 0, 24, 31 +; PPC970: std +; PPC970: lfd +; PPC970: fcfid +; PPC970: frsp store float %conv, float* %b.addr, align 4 ret void } @@ -157,11 +218,13 @@ entry: define void @uitofp_double_i64(i64 %a, double %b) nounwind ssp { entry: ; ELF64: uitofp_double_i64 +; PPC970: uitofp_double_i64 %b.addr = alloca double, align 8 %conv = uitofp i64 %a to double ; ELF64: std ; ELF64: lfd ; ELF64: fcfidu +; PPC970-NOT: fcfidu store double %conv, double* %b.addr, align 8 ret void } @@ -169,11 +232,14 @@ entry: define void @uitofp_double_i32(i32 %a, double %b) nounwind ssp { entry: ; ELF64: uitofp_double_i32 +; PPC970: uitofp_double_i32 %b.addr = alloca double, align 8 %conv = uitofp i32 %a to double ; ELF64: std ; ELF64: lfiwzx ; ELF64: fcfidu +; PPC970-NOT: lfiwzx +; PPC970-NOT: fcfidu store double %conv, double* %b.addr, align 8 ret void } @@ -181,12 +247,17 @@ entry: define void @uitofp_double_i16(i16 %a, double %b) nounwind ssp { entry: ; ELF64: uitofp_double_i16 +; PPC970: uitofp_double_i16 %b.addr = alloca double, align 8 %conv = uitofp i16 %a to double ; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48 ; ELF64: std ; ELF64: lfd ; ELF64: fcfidu +; PPC970: rlwinm {{[0-9]+}}, {{[0-9]+}}, 0, 16, 31 +; PPC970: std +; PPC970: lfd +; PPC970: fcfid store double %conv, double* %b.addr, align 8 ret void } @@ -194,12 +265,17 @@ entry: define void @uitofp_double_i8(i8 %a, double %b) nounwind ssp { entry: ; ELF64: uitofp_double_i8 +; PPC970: uitofp_double_i8 %b.addr = alloca double, align 8 %conv = uitofp i8 %a to double ; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56 ; ELF64: std ; ELF64: lfd ; ELF64: fcfidu +; PPC970: rlwinm {{[0-9]+}}, {{[0-9]+}}, 0, 24, 31 +; PPC970: std +; PPC970: lfd +; PPC970: fcfid store double %conv, double* %b.addr, align 8 ret void } @@ -209,11 +285,15 @@ entry: define void @fptosi_float_i32(float %a) nounwind ssp { entry: ; ELF64: fptosi_float_i32 +; PPC970: fptosi_float_i32 %b.addr = alloca i32, align 4 %conv = fptosi float %a to i32 ; ELF64: fctiwz ; ELF64: stfd ; ELF64: lwa +; PPC970: fctiwz +; PPC970: stfd +; PPC970: lwa store i32 %conv, i32* %b.addr, align 4 ret void } @@ -221,11 +301,15 @@ entry: define void @fptosi_float_i64(float %a) nounwind ssp { entry: ; ELF64: fptosi_float_i64 +; PPC970: fptosi_float_i64 %b.addr = alloca i64, align 4 %conv = fptosi float %a to i64 ; ELF64: fctidz ; ELF64: stfd ; ELF64: ld +; PPC970: fctidz +; PPC970: stfd +; PPC970: ld store i64 %conv, i64* %b.addr, align 4 ret void } @@ -233,11 +317,15 @@ entry: define void @fptosi_double_i32(double %a) nounwind ssp { entry: ; ELF64: fptosi_double_i32 +; PPC970: fptosi_double_i32 %b.addr = alloca i32, align 8 %conv = fptosi double %a to i32 ; ELF64: fctiwz ; ELF64: stfd ; ELF64: lwa +; PPC970: fctiwz +; PPC970: stfd +; PPC970: lwa store i32 %conv, i32* %b.addr, align 8 ret void } @@ -245,11 +333,15 @@ entry: define void @fptosi_double_i64(double %a) nounwind ssp { entry: ; ELF64: fptosi_double_i64 +; PPC970: fptosi_double_i64 %b.addr = alloca i64, align 8 %conv = fptosi double %a to i64 ; ELF64: fctidz ; ELF64: stfd ; ELF64: ld +; PPC970: fctidz +; PPC970: stfd +; PPC970: ld store i64 %conv, i64* %b.addr, align 8 ret void } @@ -259,11 +351,15 @@ entry: define void @fptoui_float_i32(float %a) nounwind ssp { entry: ; ELF64: fptoui_float_i32 +; PPC970: fptoui_float_i32 %b.addr = alloca i32, align 4 %conv = fptoui float %a to i32 ; ELF64: fctiwuz ; ELF64: stfd ; ELF64: lwz +; PPC970: fctidz +; PPC970: stfd +; PPC970: lwz store i32 %conv, i32* %b.addr, align 4 ret void } @@ -271,11 +367,13 @@ entry: define void @fptoui_float_i64(float %a) nounwind ssp { entry: ; ELF64: fptoui_float_i64 +; PPC970: fptoui_float_i64 %b.addr = alloca i64, align 4 %conv = fptoui float %a to i64 ; ELF64: fctiduz ; ELF64: stfd ; ELF64: ld +; PPC970-NOT: fctiduz store i64 %conv, i64* %b.addr, align 4 ret void } @@ -283,11 +381,15 @@ entry: define void @fptoui_double_i32(double %a) nounwind ssp { entry: ; ELF64: fptoui_double_i32 +; PPC970: fptoui_double_i32 %b.addr = alloca i32, align 8 %conv = fptoui double %a to i32 ; ELF64: fctiwuz ; ELF64: stfd ; ELF64: lwz +; PPC970: fctidz +; PPC970: stfd +; PPC970: lwz store i32 %conv, i32* %b.addr, align 8 ret void } @@ -295,11 +397,13 @@ entry: define void @fptoui_double_i64(double %a) nounwind ssp { entry: ; ELF64: fptoui_double_i64 +; PPC970: fptoui_double_i64 %b.addr = alloca i64, align 8 %conv = fptoui double %a to i64 ; ELF64: fctiduz ; ELF64: stfd ; ELF64: ld +; PPC970-NOT: fctiduz store i64 %conv, i64* %b.addr, align 8 ret void } |