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| author | Tony Jiang <jtony@ca.ibm.com> | 2017-01-16 20:12:26 +0000 |
|---|---|---|
| committer | Tony Jiang <jtony@ca.ibm.com> | 2017-01-16 20:12:26 +0000 |
| commit | 758e067345e203fed4bd61819c7c8d4f2ad9930b (patch) | |
| tree | 7426826094845cb184c8eaa4b6414159c39974ad /test/CodeGen/PowerPC/expand-isel-8.mir | |
| parent | 627c8074e746928e6f318c3246047b221a187241 (diff) | |
[PowerPC] Expand ISEL instruction into if-then-else sequence.
Generally, the ISEL is expanded into if-then-else sequence, in some
cases (like when the destination register is the same with the true
or false value register), it may just be expanded into just the if
or else sequence.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292154 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC/expand-isel-8.mir')
| -rw-r--r-- | test/CodeGen/PowerPC/expand-isel-8.mir | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/test/CodeGen/PowerPC/expand-isel-8.mir b/test/CodeGen/PowerPC/expand-isel-8.mir new file mode 100644 index 00000000000..c8b857e6979 --- /dev/null +++ b/test/CodeGen/PowerPC/expand-isel-8.mir @@ -0,0 +1,65 @@ +# This file tests combining three consecutive ISELs scenario. +# RUN: llc -ppc-gen-isel=false -run-pass ppc-expand-isel -o - %s | FileCheck %s + +--- | + target datalayout = "E-m:e-i64:64-n32:64" + target triple = "powerpc64-unknown-linux-gnu" + define signext i32 @testExpandISEL(i32 signext %i, i32 signext %j) { + entry: + %cmp = icmp sgt i32 %i, 0 + %add = add nsw i32 %i, 1 + %cond = select i1 %cmp, i32 %add, i32 %j + ret i32 %cond + } + +... +--- +name: testExpandISEL +alignment: 2 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +liveins: + - { reg: '%x3' } + - { reg: '%x4' } + - { reg: '%x5' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + maxCallFrameSize: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false +body: | + bb.0.entry: + liveins: %x3, %x4, %x5 + + %r4 = ADDI %r3, 1 + %cr0 = CMPWI %r3, 0 + %r5 = ISEL %r3, %r4, %cr0gt + %r3 = ISEL %r4, %r5, %cr0gt + %r4 = ISEL %r3, %r5, %cr0gt + ; CHECK: BC %cr0gt, %[[TRUE:bb.[0-9]+]] + ; CHECK: %[[FALSE:bb.[0-9]+]] + ; CHECK: %r5 = ORI %r4, 0 + ; CHECK: %r3 = ORI %r5, 0 + ; CHECK: %r4 = ORI %r5, 0 + ; CHECK: B %[[SUCCESSOR:bb.[0-9]+]] + ; CHECK: [[TRUE]] + ; CHECK: %r5 = ADDI %r3, 0 + ; CHECK: %r3 = ADDI %r4, 0 + ; CHECK: %r4 = ADDI %r3, 0 + + %x5 = EXTSW_32_64 %r5 + %x3 = EXTSW_32_64 %r3 + +... |