diff options
| author | Matthias Braun <matze@braunis.de> | 2017-06-15 22:14:55 +0000 |
|---|---|---|
| committer | Matthias Braun <matze@braunis.de> | 2017-06-15 22:14:55 +0000 |
| commit | 02688b00ef03018033c601d8d83c6baf7a596c7f (patch) | |
| tree | a1761d3e246d9819885cd2d770e49c1a3d0fbcc4 /test/CodeGen/PowerPC/dyn-alloca-aligned.ll | |
| parent | c82adde7b97fc21bddcc396683487af5a6bb73cd (diff) | |
RegScavenging: Add scavengeRegisterBackwards()
Re-apply r276044/r279124. Trying to reproduce or disprove the ppc64
problems reported in the stage2 build last time, which I cannot
reproduce right now.
This is a variant of scavengeRegister() that works for
enterBasicBlockEnd()/backward(). The benefit of the backward mode is
that it is not affected by incomplete kill flags.
This patch also changes
PrologEpilogInserter::doScavengeFrameVirtualRegs() to use the register
scavenger in backwards mode.
Differential Revision: http://reviews.llvm.org/D21885
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305516 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC/dyn-alloca-aligned.ll')
| -rw-r--r-- | test/CodeGen/PowerPC/dyn-alloca-aligned.ll | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/test/CodeGen/PowerPC/dyn-alloca-aligned.ll b/test/CodeGen/PowerPC/dyn-alloca-aligned.ll index 0de2e220c2c..e0f28475d8f 100644 --- a/test/CodeGen/PowerPC/dyn-alloca-aligned.ll +++ b/test/CodeGen/PowerPC/dyn-alloca-aligned.ll @@ -25,8 +25,8 @@ entry: ; CHECK-DAG: li [[REG1:[0-9]+]], -128 ; CHECK-DAG: neg [[REG2:[0-9]+]], -; CHECK: and [[REG1]], [[REG2]], [[REG1]] -; CHECK: stdux {{[0-9]+}}, 1, [[REG1]] +; CHECK: and [[REG3:[0-9]+]], [[REG2]], [[REG1]] +; CHECK: stdux {{[0-9]+}}, 1, [[REG3]] ; CHECK: blr |