diff options
| author | Hal Finkel <hfinkel@anl.gov> | 2013-03-21 23:23:34 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2013-03-21 23:23:34 +0000 |
| commit | 3ea1b064a0b9c3d161b0f77a9e957970f98907ab (patch) | |
| tree | 16053716b244cfe03039d14a5dcc129b26d3111d /test/CodeGen/PowerPC/asym-regclass-copy.ll | |
| parent | bb4e619cd9ff34708e3baaf0aac70275a917e0ba (diff) | |
Fix a register-class comparison bug in PPCCTRLoops
Thanks to Jakob for isolating the underlying problem from the
test case in r177423. The original commit had introduced
asymmetric copy operations, but these turned out to be a work-around
to the real problem (the use of == instead of hasSubClassEq in PPCCTRLoops).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177679 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC/asym-regclass-copy.ll')
| -rw-r--r-- | test/CodeGen/PowerPC/asym-regclass-copy.ll | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/test/CodeGen/PowerPC/asym-regclass-copy.ll b/test/CodeGen/PowerPC/asym-regclass-copy.ll index c399802a1ee..d04a6c98ee1 100644 --- a/test/CodeGen/PowerPC/asym-regclass-copy.ll +++ b/test/CodeGen/PowerPC/asym-regclass-copy.ll @@ -2,7 +2,8 @@ target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" -; This test triggers the use of the asymmetric OR8_32 copy pattern. +; This tests that the GPRC/GPRC_NOR0 intersection subclass relationship with +; GPRC is handled correctly. When it was not, this test would assert. @gen_random.last = external unnamed_addr global i64, align 8 @.str = external unnamed_addr constant [4 x i8], align 1 |