diff options
| author | Owen Anderson <resistor@mac.com> | 2015-03-19 22:48:57 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2015-03-19 22:48:57 +0000 |
| commit | 8154ef7589acc76850d6e430adfc0d60e82d94cf (patch) | |
| tree | 9f5cc7e35299a0aac5c6df7fb7ef326164334633 /test/CodeGen/PowerPC/anon_aggr.ll | |
| parent | 53f788786fc103f516e4b9a7fcfc3a8f21e48918 (diff) | |
Fix a nasty bug in DAGCombine of STORE nodes.
This is very related to the bug fixed in r174431. The problem is that
SelectionDAG does not include alignment in the uniquing of loads and
stores. When an otherwise no-op DAGCombine would increase the alignment
of a load or store, the original node would be returned (with the
alignment increased), which would cause the node not to be processed by
any further DAGCombines.
I don't have a direct testcase for this that manifests on an in-tree
target, but I did see some noise in the tests for other targets and have
updated them for it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232780 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC/anon_aggr.ll')
| -rw-r--r-- | test/CodeGen/PowerPC/anon_aggr.ll | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/test/CodeGen/PowerPC/anon_aggr.ll b/test/CodeGen/PowerPC/anon_aggr.ll index 1a25f4bfbfe..e899cfa4ce0 100644 --- a/test/CodeGen/PowerPC/anon_aggr.ll +++ b/test/CodeGen/PowerPC/anon_aggr.ll @@ -165,7 +165,7 @@ unequal: ; DARWIN32: lwz r[[REG3:[0-9]+]], 108(r1) ; DARWIN32: mr r[[REG2:[0-9]+]], r[[REG4]] ; DARWIN32: cmplw cr{{[0-9]+}}, r[[REG4]], r[[REG3]] -; DARWIN32: stw r[[REG4]], -[[OFFSET1:[0-9]+]] +; DARWIN32: stw r[[REG2]], -[[OFFSET1:[0-9]+]] ; DARWIN32: stw r[[REG3]], -[[OFFSET2:[0-9]+]] ; DARWIN32: lwz r[[REG1]], -[[OFFSET1]] ; DARWIN32: lwz r[[REG1]], -[[OFFSET2]] |