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| author | Nirav Dave <niravd@google.com> | 2016-10-13 20:23:25 +0000 |
|---|---|---|
| committer | Nirav Dave <niravd@google.com> | 2016-10-13 20:23:25 +0000 |
| commit | 080559c6d39cfb0bbf1effe4d2d4a87368620596 (patch) | |
| tree | e3b8e93b0f4bdbb6bc5a173eaf8f3e3088b3a44d /test/CodeGen/PowerPC/anon_aggr.ll | |
| parent | 154f790710ef85dc956d994fcb27b3582e7a75de (diff) | |
Revert "In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled."
This reverts commit r284151 which appears to be triggering a LTO
failures on Hexagon
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284157 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC/anon_aggr.ll')
| -rw-r--r-- | test/CodeGen/PowerPC/anon_aggr.ll | 31 |
1 files changed, 16 insertions, 15 deletions
diff --git a/test/CodeGen/PowerPC/anon_aggr.ll b/test/CodeGen/PowerPC/anon_aggr.ll index 6e7c196c4b9..f4e788849ec 100644 --- a/test/CodeGen/PowerPC/anon_aggr.ll +++ b/test/CodeGen/PowerPC/anon_aggr.ll @@ -60,9 +60,10 @@ equal: unequal: ret i8* %array2_ptr } + ; CHECK-LABEL: func2: -; CHECK: cmpld {{([0-9]+,)?}}4, 6 -; CHECK: mr [[REG2:[0-9]+]], 6 +; CHECK: ld [[REG2:[0-9]+]], 72(1) +; CHECK: cmpld {{([0-9]+,)?}}4, [[REG2]] ; CHECK-DAG: std [[REG2]], -[[OFFSET1:[0-9]+]] ; CHECK-DAG: std 4, -[[OFFSET2:[0-9]+]] ; CHECK: ld 3, -[[OFFSET2]](1) @@ -84,8 +85,8 @@ unequal: ; DARWIN64: mr ; DARWIN64: mr r[[REG3:[0-9]+]], r[[REGA:[0-9]+]] ; DARWIN64: cmpld {{(cr[0-9]+,)?}}r[[REGA]], r[[REG2]] -; DARWIN64: std r[[REG2]], -[[OFFSET2:[0-9]+]] ; DARWIN64: std r[[REG3]], -[[OFFSET1:[0-9]+]] +; DARWIN64: std r[[REG2]], -[[OFFSET2:[0-9]+]] ; DARWIN64: ld r3, -[[OFFSET1]] ; DARWIN64: ld r3, -[[OFFSET2]] @@ -105,24 +106,24 @@ unequal: } ; CHECK-LABEL: func3: -; CHECK: cmpld {{([0-9]+,)?}}4, 6 -; CHECK: mr [[REG3:[0-9]+]], 6 -; CHECK: mr [[REG4:[0-9]+]], 4 -; CHECK: std [[REG4]], -[[OFFSET2:[0-9]+]](1) +; CHECK: ld [[REG3:[0-9]+]], 72(1) +; CHECK: ld [[REG4:[0-9]+]], 56(1) +; CHECK: cmpld {{([0-9]+,)?}}[[REG4]], [[REG3]] ; CHECK: std [[REG3]], -[[OFFSET1:[0-9]+]](1) +; CHECK: std [[REG4]], -[[OFFSET2:[0-9]+]](1) ; CHECK: ld 3, -[[OFFSET2]](1) ; CHECK: ld 3, -[[OFFSET1]](1) ; DARWIN32: _func3: -; DARWIN32-DAG: addi r[[REG1:[0-9]+]], r[[REGSP:[0-9]+]], 36 -; DARWIN32-DAG: addi r[[REG2:[0-9]+]], r[[REGSP]], 24 -; DARWIN32-DAG: lwz r[[REG3:[0-9]+]], 44(r[[REGSP]]) -; DARWIN32-DAG: lwz r[[REG4:[0-9]+]], 32(r[[REGSP]]) +; DARWIN32: addi r[[REG1:[0-9]+]], r[[REGSP:[0-9]+]], 36 +; DARWIN32: addi r[[REG2:[0-9]+]], r[[REGSP]], 24 +; DARWIN32: lwz r[[REG3:[0-9]+]], 44(r[[REGSP]]) +; DARWIN32: lwz r[[REG4:[0-9]+]], 32(r[[REGSP]]) ; DARWIN32: cmplw {{(cr[0-9]+,)?}}r[[REG4]], r[[REG3]] -; DARWIN32-DAG: stw r[[REG3]], -[[OFFSET1:[0-9]+]] -; DARWIN32-DAG: stw r[[REG4]], -[[OFFSET2:[0-9]+]] -; DARWIN32-DAG: lwz r3, -[[OFFSET1:[0-9]+]] -; DARWIN32-DAG: lwz r3, -[[OFFSET2:[0-9]+]] +; DARWIN32: stw r[[REG3]], -[[OFFSET1:[0-9]+]] +; DARWIN32: stw r[[REG4]], -[[OFFSET2:[0-9]+]] +; DARWIN32: lwz r3, -[[OFFSET2]] +; DARWIN32: lwz r3, -[[OFFSET1]] ; DARWIN64: _func3: ; DARWIN64: ld r[[REG3:[0-9]+]], 72(r1) |