diff options
| author | Simon Dardis <simon.dardis@mips.com> | 2017-12-14 16:42:04 +0000 |
|---|---|---|
| committer | Simon Dardis <simon.dardis@mips.com> | 2017-12-14 16:42:04 +0000 |
| commit | e8153722a356ac99dcd2d3da58ae24383d91193d (patch) | |
| tree | 8141d2d89859a9d33d0cbdd6e1181fccd63c1a31 /test/CodeGen/Mips | |
| parent | 92d81a8d4651622e66a000b79a0de6cb09748e00 (diff) | |
[mips] Update some tests before posting a patch, NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320715 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Mips')
| -rw-r--r-- | test/CodeGen/Mips/llvm-ir/and.ll | 2292 | ||||
| -rw-r--r-- | test/CodeGen/Mips/llvm-ir/ashr.ll | 1134 | ||||
| -rw-r--r-- | test/CodeGen/Mips/llvm-ir/lshr.ll | 1147 | ||||
| -rw-r--r-- | test/CodeGen/Mips/llvm-ir/or.ll | 1328 | ||||
| -rw-r--r-- | test/CodeGen/Mips/llvm-ir/shl.ll | 1185 | ||||
| -rw-r--r-- | test/CodeGen/Mips/llvm-ir/xor.ll | 735 |
6 files changed, 6350 insertions, 1471 deletions
diff --git a/test/CodeGen/Mips/llvm-ir/and.ll b/test/CodeGen/Mips/llvm-ir/and.ll index 9ea810dfcbf..c3a973f01cc 100644 --- a/test/CodeGen/Mips/llvm-ir/and.ll +++ b/test/CodeGen/Mips/llvm-ir/and.ll @@ -1,663 +1,2135 @@ -; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32 -; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32 -; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64 -; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64 -; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64 -; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \ -; RUN: -check-prefixes=ALL,MM,MM32 -; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ -; RUN: -check-prefixes=ALL,MM,MM32 +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips2 | FileCheck %s \ +; RUN: -check-prefix=MIPS +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32 | FileCheck %s \ +; RUN: -check-prefix=MIPS +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r2 | FileCheck %s \ +; RUN: -check-prefix=MIPS32R2 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 | FileCheck %s \ +; RUN: -check-prefix=MIPS32R2 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r5 | FileCheck %s \ +; RUN: -check-prefix=MIPS32R2 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 | FileCheck %s \ +; RUN: -check-prefix=MIPS32R6 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips3 | FileCheck %s \ +; RUN: -check-prefix=MIPS64 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips4 | FileCheck %s \ +; RUN: -check-prefix=MIPS64 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64 | FileCheck %s \ +; RUN: -check-prefix=MIPS64 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r2 | FileCheck %s \ +; RUN: -check-prefix=MIPS64R2 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r3 | FileCheck %s \ +; RUN: -check-prefix=MIPS64R2 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r5 | FileCheck %s \ +; RUN: -check-prefix=MIPS64R2 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r6 | FileCheck %s \ +; RUN: -check-prefix=MIPS64R6 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefix=MM32R3 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefix=MM32R6 define signext i1 @and_i1(i1 signext %a, i1 signext %b) { +; MIPS-LABEL: and_i1: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: and $2, $4, $5 +; +; MIPS32R2-LABEL: and_i1: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: and $2, $4, $5 +; +; MIPS32R6-LABEL: and_i1: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: and $2, $4, $5 +; +; MIPS64-LABEL: and_i1: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: and $1, $4, $5 +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: sll $2, $1, 0 +; +; MIPS64R2-LABEL: and_i1: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: and $1, $4, $5 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: sll $2, $1, 0 +; +; MIPS64R6-LABEL: and_i1: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: and $1, $4, $5 +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: sll $2, $1, 0 +; +; MM32R3-LABEL: and_i1: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: and16 $4, $5 +; MM32R3-NEXT: move $2, $4 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i1: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: and16 $4, $5 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i1: - - ; GP32: and $2, $4, $5 - - ; GP64: and $1, $4, $5 - - ; MM32: and16 $[[T0:[0-9]+]], $5 - ; MM32: move $2, $[[T0]] - %r = and i1 %a, %b ret i1 %r } define signext i8 @and_i8(i8 signext %a, i8 signext %b) { +; MIPS-LABEL: and_i8: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: and $2, $4, $5 +; +; MIPS32R2-LABEL: and_i8: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: and $2, $4, $5 +; +; MIPS32R6-LABEL: and_i8: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: and $2, $4, $5 +; +; MIPS64-LABEL: and_i8: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: and $1, $4, $5 +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: sll $2, $1, 0 +; +; MIPS64R2-LABEL: and_i8: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: and $1, $4, $5 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: sll $2, $1, 0 +; +; MIPS64R6-LABEL: and_i8: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: and $1, $4, $5 +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: sll $2, $1, 0 +; +; MM32R3-LABEL: and_i8: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: and16 $4, $5 +; MM32R3-NEXT: move $2, $4 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i8: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: and16 $4, $5 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i8: - - ; GP32: and $2, $4, $5 - - ; GP64: and $1, $4, $5 - - ; MM32: and16 $[[T0:[0-9]+]], $5 - ; MM32: move $2, $[[T0]] - %r = and i8 %a, %b ret i8 %r } define signext i16 @and_i16(i16 signext %a, i16 signext %b) { +; MIPS-LABEL: and_i16: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: and $2, $4, $5 +; +; MIPS32R2-LABEL: and_i16: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: and $2, $4, $5 +; +; MIPS32R6-LABEL: and_i16: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: and $2, $4, $5 +; +; MIPS64-LABEL: and_i16: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: and $1, $4, $5 +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: sll $2, $1, 0 +; +; MIPS64R2-LABEL: and_i16: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: and $1, $4, $5 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: sll $2, $1, 0 +; +; MIPS64R6-LABEL: and_i16: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: and $1, $4, $5 +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: sll $2, $1, 0 +; +; MM32R3-LABEL: and_i16: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: and16 $4, $5 +; MM32R3-NEXT: move $2, $4 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i16: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: and16 $4, $5 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i16: - - ; GP32: and $2, $4, $5 - - ; GP64: and $1, $4, $5 - - ; MM32: and16 $[[T0:[0-9]+]], $5 - ; MM32 move $2, $[[T0]] - %r = and i16 %a, %b ret i16 %r } define signext i32 @and_i32(i32 signext %a, i32 signext %b) { +; MIPS-LABEL: and_i32: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: and $2, $4, $5 +; +; MIPS32R2-LABEL: and_i32: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: and $2, $4, $5 +; +; MIPS32R6-LABEL: and_i32: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: and $2, $4, $5 +; +; MIPS64-LABEL: and_i32: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: and $1, $4, $5 +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: sll $2, $1, 0 +; +; MIPS64R2-LABEL: and_i32: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: and $1, $4, $5 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: sll $2, $1, 0 +; +; MIPS64R6-LABEL: and_i32: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: and $1, $4, $5 +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: sll $2, $1, 0 +; +; MM32R3-LABEL: and_i32: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: and16 $4, $5 +; MM32R3-NEXT: move $2, $4 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i32: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: and16 $4, $5 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i32: - - ; GP32: and $2, $4, $5 - - ; GP64: and $[[T0:[0-9]+]], $4, $5 - ; GP64: sll $2, $[[T0]], 0 - - ; MM32: and16 $[[T0:[0-9]+]], $5 - ; MM32: move $2, $[[T0]] - %r = and i32 %a, %b ret i32 %r } define signext i64 @and_i64(i64 signext %a, i64 signext %b) { +; MIPS-LABEL: and_i64: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: and $2, $4, $6 +; MIPS-NEXT: jr $ra +; MIPS-NEXT: and $3, $5, $7 +; +; MIPS32R2-LABEL: and_i64: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: and $2, $4, $6 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: and $3, $5, $7 +; +; MIPS32R6-LABEL: and_i64: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: and $2, $4, $6 +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: and $3, $5, $7 +; +; MIPS64-LABEL: and_i64: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: and $2, $4, $5 +; +; MIPS64R2-LABEL: and_i64: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: and $2, $4, $5 +; +; MIPS64R6-LABEL: and_i64: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: and $2, $4, $5 +; +; MM32R3-LABEL: and_i64: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: and16 $4, $6 +; MM32R3-NEXT: and16 $5, $7 +; MM32R3-NEXT: move $2, $4 +; MM32R3-NEXT: move $3, $5 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i64: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: and16 $4, $6 +; MM32R6-NEXT: and16 $5, $7 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: move $3, $5 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i64: - - ; GP32: and $2, $4, $6 - ; GP32: and $3, $5, $7 - - ; GP64: and $2, $4, $5 - - ; MM32: and16 $[[T0:[0-9]+]], $6 - ; MM32: and16 $[[T1:[0-9]+]], $7 - ; MM32: move $2, $[[T0]] - ; MM32: move $3, $[[T1]] - %r = and i64 %a, %b ret i64 %r } define signext i128 @and_i128(i128 signext %a, i128 signext %b) { +; MIPS-LABEL: and_i128: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: lw $1, 20($sp) +; MIPS-NEXT: lw $2, 16($sp) +; MIPS-NEXT: and $2, $4, $2 +; MIPS-NEXT: and $3, $5, $1 +; MIPS-NEXT: lw $1, 24($sp) +; MIPS-NEXT: and $4, $6, $1 +; MIPS-NEXT: lw $1, 28($sp) +; MIPS-NEXT: jr $ra +; MIPS-NEXT: and $5, $7, $1 +; +; MIPS32R2-LABEL: and_i128: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: lw $1, 20($sp) +; MIPS32R2-NEXT: lw $2, 16($sp) +; MIPS32R2-NEXT: and $2, $4, $2 +; MIPS32R2-NEXT: and $3, $5, $1 +; MIPS32R2-NEXT: lw $1, 24($sp) +; MIPS32R2-NEXT: and $4, $6, $1 +; MIPS32R2-NEXT: lw $1, 28($sp) +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: and $5, $7, $1 +; +; MIPS32R6-LABEL: and_i128: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: lw $1, 20($sp) +; MIPS32R6-NEXT: lw $2, 16($sp) +; MIPS32R6-NEXT: and $2, $4, $2 +; MIPS32R6-NEXT: and $3, $5, $1 +; MIPS32R6-NEXT: lw $1, 24($sp) +; MIPS32R6-NEXT: and $4, $6, $1 +; MIPS32R6-NEXT: lw $1, 28($sp) +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: and $5, $7, $1 +; +; MIPS64-LABEL: and_i128: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: and $2, $4, $6 +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: and $3, $5, $7 +; +; MIPS64R2-LABEL: and_i128: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: and $2, $4, $6 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: and $3, $5, $7 +; +; MIPS64R6-LABEL: and_i128: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: and $2, $4, $6 +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: and $3, $5, $7 +; +; MM32R3-LABEL: and_i128: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: lw $3, 20($sp) +; MM32R3-NEXT: lw $2, 16($sp) +; MM32R3-NEXT: and16 $2, $4 +; MM32R3-NEXT: and16 $3, $5 +; MM32R3-NEXT: lw $4, 24($sp) +; MM32R3-NEXT: and16 $4, $6 +; MM32R3-NEXT: lw $5, 28($sp) +; MM32R3-NEXT: and16 $5, $7 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i128: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: lw $3, 20($sp) +; MM32R6-NEXT: lw $2, 16($sp) +; MM32R6-NEXT: and16 $2, $4 +; MM32R6-NEXT: and16 $3, $5 +; MM32R6-NEXT: lw $4, 24($sp) +; MM32R6-NEXT: and16 $4, $6 +; MM32R6-NEXT: lw $5, 28($sp) +; MM32R6-NEXT: and16 $5, $7 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i128: - - ; GP32: lw $[[T0:[0-9]+]], 20($sp) - ; GP32: lw $[[T1:[0-9]+]], 16($sp) - ; GP32: and $2, $4, $[[T1]] - ; GP32: and $3, $5, $[[T0]] - ; GP32: lw $[[T2:[0-9]+]], 24($sp) - ; GP32: and $4, $6, $[[T2]] - ; GP32: lw $[[T3:[0-9]+]], 28($sp) - ; GP32: and $5, $7, $[[T3]] - - ; GP64: and $2, $4, $6 - ; GP64: and $3, $5, $7 - - ; MM32: lw $[[T0:[0-9]+]], 20($sp) - ; MM32: lw $[[T1:[0-9]+]], 16($sp) - ; MM32: and16 $[[T1]], $4 - ; MM32: and16 $[[T0]], $5 - ; MM32: lw $[[T2:[0-9]+]], 24($sp) - ; MM32: and16 $[[T2]], $6 - ; MM32: lw $[[T3:[0-9]+]], 28($sp) - ; MM32: and16 $[[T3]], $7 - %r = and i128 %a, %b ret i128 %r } define signext i1 @and_i1_4(i1 signext %b) { +; MIPS-LABEL: and_i1_4: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: addiu $2, $zero, 0 +; +; MIPS32R2-LABEL: and_i1_4: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: addiu $2, $zero, 0 +; +; MIPS32R6-LABEL: and_i1_4: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: addiu $2, $zero, 0 +; +; MIPS64-LABEL: and_i1_4: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: addiu $2, $zero, 0 +; +; MIPS64R2-LABEL: and_i1_4: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: addiu $2, $zero, 0 +; +; MIPS64R6-LABEL: and_i1_4: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: addiu $2, $zero, 0 +; +; MM32R3-LABEL: and_i1_4: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: li16 $2, 0 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i1_4: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: li16 $2, 0 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i1_4: - - ; GP32: addiu $2, $zero, 0 - - ; GP64: addiu $2, $zero, 0 - - ; MM: li16 $2, 0 - %r = and i1 4, %b ret i1 %r } define signext i8 @and_i8_4(i8 signext %b) { +; MIPS-LABEL: and_i8_4: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: andi $2, $4, 4 +; +; MIPS32R2-LABEL: and_i8_4: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: andi $2, $4, 4 +; +; MIPS32R6-LABEL: and_i8_4: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: andi $2, $4, 4 +; +; MIPS64-LABEL: and_i8_4: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: andi $2, $4, 4 +; +; MIPS64R2-LABEL: and_i8_4: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: andi $2, $4, 4 +; +; MIPS64R6-LABEL: and_i8_4: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: andi $2, $4, 4 +; +; MM32R3-LABEL: and_i8_4: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: andi16 $2, $4, 4 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i8_4: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: andi16 $2, $4, 4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i8_4: - - ; GP32: andi $2, $4, 4 - - ; GP64: andi $2, $4, 4 - - ; MM: andi16 $2, $4, 4 - %r = and i8 4, %b ret i8 %r } define signext i16 @and_i16_4(i16 signext %b) { +; MIPS-LABEL: and_i16_4: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: andi $2, $4, 4 +; +; MIPS32R2-LABEL: and_i16_4: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: andi $2, $4, 4 +; +; MIPS32R6-LABEL: and_i16_4: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: andi $2, $4, 4 +; +; MIPS64-LABEL: and_i16_4: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: andi $2, $4, 4 +; +; MIPS64R2-LABEL: and_i16_4: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: andi $2, $4, 4 +; +; MIPS64R6-LABEL: and_i16_4: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: andi $2, $4, 4 +; +; MM32R3-LABEL: and_i16_4: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: andi16 $2, $4, 4 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i16_4: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: andi16 $2, $4, 4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i16_4: - - ; GP32: andi $2, $4, 4 - - ; GP64: andi $2, $4, 4 - - ; MM: andi16 $2, $4, 4 - %r = and i16 4, %b ret i16 %r } define signext i32 @and_i32_4(i32 signext %b) { +; MIPS-LABEL: and_i32_4: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: andi $2, $4, 4 +; +; MIPS32R2-LABEL: and_i32_4: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: andi $2, $4, 4 +; +; MIPS32R6-LABEL: and_i32_4: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: andi $2, $4, 4 +; +; MIPS64-LABEL: and_i32_4: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: andi $2, $4, 4 +; +; MIPS64R2-LABEL: and_i32_4: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: andi $2, $4, 4 +; +; MIPS64R6-LABEL: and_i32_4: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: andi $2, $4, 4 +; +; MM32R3-LABEL: and_i32_4: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: andi16 $2, $4, 4 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i32_4: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: andi16 $2, $4, 4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i32_4: - - ; GP32: andi $2, $4, 4 - - ; GP64: andi $2, $4, 4 - - ; MM: andi16 $2, $4, 4 - %r = and i32 4, %b ret i32 %r } define signext i64 @and_i64_4(i64 signext %b) { +; MIPS-LABEL: and_i64_4: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: andi $3, $5, 4 +; MIPS-NEXT: jr $ra +; MIPS-NEXT: addiu $2, $zero, 0 +; +; MIPS32R2-LABEL: and_i64_4: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: andi $3, $5, 4 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: addiu $2, $zero, 0 +; +; MIPS32R6-LABEL: and_i64_4: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: andi $3, $5, 4 +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: addiu $2, $zero, 0 +; +; MIPS64-LABEL: and_i64_4: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: andi $2, $4, 4 +; +; MIPS64R2-LABEL: and_i64_4: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: andi $2, $4, 4 +; +; MIPS64R6-LABEL: and_i64_4: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: andi $2, $4, 4 +; +; MM32R3-LABEL: and_i64_4: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: andi16 $3, $5, 4 +; MM32R3-NEXT: li16 $2, 0 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i64_4: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: andi16 $3, $5, 4 +; MM32R6-NEXT: li16 $2, 0 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i64_4: - - ; GP32: andi $3, $5, 4 - ; GP32: addiu $2, $zero, 0 - - ; GP64: andi $2, $4, 4 - - ; MM32: andi16 $3, $5, 4 - ; MM32: li16 $2, 0 - %r = and i64 4, %b ret i64 %r } define signext i128 @and_i128_4(i128 signext %b) { +; MIPS-LABEL: and_i128_4: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: andi $5, $7, 4 +; MIPS-NEXT: addiu $2, $zero, 0 +; MIPS-NEXT: addiu $3, $zero, 0 +; MIPS-NEXT: jr $ra +; MIPS-NEXT: addiu $4, $zero, 0 +; +; MIPS32R2-LABEL: and_i128_4: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: andi $5, $7, 4 +; MIPS32R2-NEXT: addiu $2, $zero, 0 +; MIPS32R2-NEXT: addiu $3, $zero, 0 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: addiu $4, $zero, 0 +; +; MIPS32R6-LABEL: and_i128_4: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: andi $5, $7, 4 +; MIPS32R6-NEXT: addiu $2, $zero, 0 +; MIPS32R6-NEXT: addiu $3, $zero, 0 +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: addiu $4, $zero, 0 +; +; MIPS64-LABEL: and_i128_4: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: andi $3, $5, 4 +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: daddiu $2, $zero, 0 +; +; MIPS64R2-LABEL: and_i128_4: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: andi $3, $5, 4 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: daddiu $2, $zero, 0 +; +; MIPS64R6-LABEL: and_i128_4: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: andi $3, $5, 4 +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: daddiu $2, $zero, 0 +; +; MM32R3-LABEL: and_i128_4: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: andi16 $5, $7, 4 +; MM32R3-NEXT: li16 $2, 0 +; MM32R3-NEXT: li16 $3, 0 +; MM32R3-NEXT: li16 $4, 0 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i128_4: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: andi16 $5, $7, 4 +; MM32R6-NEXT: li16 $2, 0 +; MM32R6-NEXT: li16 $3, 0 +; MM32R6-NEXT: li16 $4, 0 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i128_4: - - ; GP32: andi $5, $7, 4 - ; GP32: addiu $2, $zero, 0 - ; GP32: addiu $3, $zero, 0 - ; GP32: addiu $4, $zero, 0 - - ; GP64: andi $3, $5, 4 - ; GP64: daddiu $2, $zero, 0 - - ; MM32: andi16 $5, $7, 4 - ; MM32: li16 $2, 0 - ; MM32: li16 $3, 0 - ; MM32: li16 $4, 0 - %r = and i128 4, %b ret i128 %r } define signext i1 @and_i1_31(i1 signext %b) { +; MIPS-LABEL: and_i1_31: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: move $2, $4 +; +; MIPS32R2-LABEL: and_i1_31: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: move $2, $4 +; +; MIPS32R6-LABEL: and_i1_31: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: move $2, $4 +; +; MIPS64-LABEL: and_i1_31: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: move $2, $4 +; +; MIPS64R2-LABEL: and_i1_31: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: move $2, $4 +; +; MIPS64R6-LABEL: and_i1_31: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: move $2, $4 +; +; MM32R3-LABEL: and_i1_31: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: move $2, $4 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i1_31: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i1_31: - - ; ALL: move $2, $4 - %r = and i1 31, %b ret i1 %r } define signext i8 @and_i8_31(i8 signext %b) { +; MIPS-LABEL: and_i8_31: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: andi $2, $4, 31 +; +; MIPS32R2-LABEL: and_i8_31: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: andi $2, $4, 31 +; +; MIPS32R6-LABEL: and_i8_31: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: andi $2, $4, 31 +; +; MIPS64-LABEL: and_i8_31: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: andi $2, $4, 31 +; +; MIPS64R2-LABEL: and_i8_31: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: andi $2, $4, 31 +; +; MIPS64R6-LABEL: and_i8_31: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: andi $2, $4, 31 +; +; MM32R3-LABEL: and_i8_31: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: andi16 $2, $4, 31 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i8_31: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: andi16 $2, $4, 31 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i8_31: - - ; GP32: andi $2, $4, 31 - - ; GP64: andi $2, $4, 31 - - ; MM: andi16 $2, $4, 31 - %r = and i8 31, %b ret i8 %r } define signext i16 @and_i16_31(i16 signext %b) { +; MIPS-LABEL: and_i16_31: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: andi $2, $4, 31 +; +; MIPS32R2-LABEL: and_i16_31: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: andi $2, $4, 31 +; +; MIPS32R6-LABEL: and_i16_31: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: andi $2, $4, 31 +; +; MIPS64-LABEL: and_i16_31: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: andi $2, $4, 31 +; +; MIPS64R2-LABEL: and_i16_31: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: andi $2, $4, 31 +; +; MIPS64R6-LABEL: and_i16_31: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: andi $2, $4, 31 +; +; MM32R3-LABEL: and_i16_31: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: andi16 $2, $4, 31 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i16_31: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: andi16 $2, $4, 31 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i16_31: - - ; GP32: andi $2, $4, 31 - - ; GP64: andi $2, $4, 31 - - ; MM: andi16 $2, $4, 31 - %r = and i16 31, %b ret i16 %r } define signext i32 @and_i32_31(i32 signext %b) { +; MIPS-LABEL: and_i32_31: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: andi $2, $4, 31 +; +; MIPS32R2-LABEL: and_i32_31: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: andi $2, $4, 31 +; +; MIPS32R6-LABEL: and_i32_31: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: andi $2, $4, 31 +; +; MIPS64-LABEL: and_i32_31: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: andi $2, $4, 31 +; +; MIPS64R2-LABEL: and_i32_31: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: andi $2, $4, 31 +; +; MIPS64R6-LABEL: and_i32_31: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: andi $2, $4, 31 +; +; MM32R3-LABEL: and_i32_31: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: andi16 $2, $4, 31 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i32_31: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: andi16 $2, $4, 31 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i32_31: - - ; GP32: andi $2, $4, 31 - - ; GP64: andi $2, $4, 31 - - ; MM: andi16 $2, $4, 31 - %r = and i32 31, %b ret i32 %r } define signext i64 @and_i64_31(i64 signext %b) { +; MIPS-LABEL: and_i64_31: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: andi $3, $5, 31 +; MIPS-NEXT: jr $ra +; MIPS-NEXT: addiu $2, $zero, 0 +; +; MIPS32R2-LABEL: and_i64_31: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: andi $3, $5, 31 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: addiu $2, $zero, 0 +; +; MIPS32R6-LABEL: and_i64_31: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: andi $3, $5, 31 +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: addiu $2, $zero, 0 +; +; MIPS64-LABEL: and_i64_31: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: andi $2, $4, 31 +; +; MIPS64R2-LABEL: and_i64_31: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: andi $2, $4, 31 +; +; MIPS64R6-LABEL: and_i64_31: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: andi $2, $4, 31 +; +; MM32R3-LABEL: and_i64_31: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: andi16 $3, $5, 31 +; MM32R3-NEXT: li16 $2, 0 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i64_31: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: andi16 $3, $5, 31 +; MM32R6-NEXT: li16 $2, 0 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i64_31: - - ; GP32: andi $3, $5, 31 - ; GP32: addiu $2, $zero, 0 - - ; GP64: andi $2, $4, 31 - - ; MM32: andi16 $3, $5, 31 - ; MM32: li16 $2, 0 - %r = and i64 31, %b ret i64 %r } define signext i128 @and_i128_31(i128 signext %b) { +; MIPS-LABEL: and_i128_31: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: andi $5, $7, 31 +; MIPS-NEXT: addiu $2, $zero, 0 +; MIPS-NEXT: addiu $3, $zero, 0 +; MIPS-NEXT: jr $ra +; MIPS-NEXT: addiu $4, $zero, 0 +; +; MIPS32R2-LABEL: and_i128_31: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: andi $5, $7, 31 +; MIPS32R2-NEXT: addiu $2, $zero, 0 +; MIPS32R2-NEXT: addiu $3, $zero, 0 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: addiu $4, $zero, 0 +; +; MIPS32R6-LABEL: and_i128_31: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: andi $5, $7, 31 +; MIPS32R6-NEXT: addiu $2, $zero, 0 +; MIPS32R6-NEXT: addiu $3, $zero, 0 +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: addiu $4, $zero, 0 +; +; MIPS64-LABEL: and_i128_31: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: andi $3, $5, 31 +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: daddiu $2, $zero, 0 +; +; MIPS64R2-LABEL: and_i128_31: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: andi $3, $5, 31 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: daddiu $2, $zero, 0 +; +; MIPS64R6-LABEL: and_i128_31: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: andi $3, $5, 31 +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: daddiu $2, $zero, 0 +; +; MM32R3-LABEL: and_i128_31: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: andi16 $5, $7, 31 +; MM32R3-NEXT: li16 $2, 0 +; MM32R3-NEXT: li16 $3, 0 +; MM32R3-NEXT: li16 $4, 0 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i128_31: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: andi16 $5, $7, 31 +; MM32R6-NEXT: li16 $2, 0 +; MM32R6-NEXT: li16 $3, 0 +; MM32R6-NEXT: li16 $4, 0 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i128_31: - - ; GP32: andi $5, $7, 31 - ; GP32: addiu $2, $zero, 0 - ; GP32: addiu $3, $zero, 0 - ; GP32: addiu $4, $zero, 0 - - ; GP64: andi $3, $5, 31 - ; GP64: daddiu $2, $zero, 0 - - ; MM32: andi16 $5, $7, 31 - ; MM32: li16 $2, 0 - ; MM32: li16 $3, 0 - ; MM32: li16 $4, 0 - %r = and i128 31, %b ret i128 %r } define signext i1 @and_i1_255(i1 signext %b) { +; MIPS-LABEL: and_i1_255: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: move $2, $4 +; +; MIPS32R2-LABEL: and_i1_255: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: move $2, $4 +; +; MIPS32R6-LABEL: and_i1_255: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: move $2, $4 +; +; MIPS64-LABEL: and_i1_255: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: move $2, $4 +; +; MIPS64R2-LABEL: and_i1_255: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: move $2, $4 +; +; MIPS64R6-LABEL: and_i1_255: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: move $2, $4 +; +; MM32R3-LABEL: and_i1_255: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: move $2, $4 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i1_255: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i1_255: - - ; ALL: move $2, $4 - %r = and i1 255, %b ret i1 %r } define signext i8 @and_i8_255(i8 signext %b) { +; MIPS-LABEL: and_i8_255: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: move $2, $4 +; +; MIPS32R2-LABEL: and_i8_255: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: move $2, $4 +; +; MIPS32R6-LABEL: and_i8_255: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: move $2, $4 +; +; MIPS64-LABEL: and_i8_255: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: move $2, $4 +; +; MIPS64R2-LABEL: and_i8_255: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: move $2, $4 +; +; MIPS64R6-LABEL: and_i8_255: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: move $2, $4 +; +; MM32R3-LABEL: and_i8_255: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: move $2, $4 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i8_255: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i8_255: - - ; ALL: move $2, $4 - %r = and i8 255, %b ret i8 %r } define signext i16 @and_i16_255(i16 signext %b) { +; MIPS-LABEL: and_i16_255: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: andi $2, $4, 255 +; +; MIPS32R2-LABEL: and_i16_255: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: andi $2, $4, 255 +; +; MIPS32R6-LABEL: and_i16_255: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: andi $2, $4, 255 +; +; MIPS64-LABEL: and_i16_255: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: andi $2, $4, 255 +; +; MIPS64R2-LABEL: and_i16_255: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: andi $2, $4, 255 +; +; MIPS64R6-LABEL: and_i16_255: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: andi $2, $4, 255 +; +; MM32R3-LABEL: and_i16_255: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: andi16 $2, $4, 255 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i16_255: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: andi16 $2, $4, 255 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i16_255: - - ; GP32: andi $2, $4, 255 - - ; GP64: andi $2, $4, 255 - - ; MM: andi16 $2, $4, 255 - %r = and i16 255, %b ret i16 %r } define signext i32 @and_i32_255(i32 signext %b) { +; MIPS-LABEL: and_i32_255: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: andi $2, $4, 255 +; +; MIPS32R2-LABEL: and_i32_255: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: andi $2, $4, 255 +; +; MIPS32R6-LABEL: and_i32_255: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: andi $2, $4, 255 +; +; MIPS64-LABEL: and_i32_255: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: andi $2, $4, 255 +; +; MIPS64R2-LABEL: and_i32_255: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: andi $2, $4, 255 +; +; MIPS64R6-LABEL: and_i32_255: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: andi $2, $4, 255 +; +; MM32R3-LABEL: and_i32_255: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: andi16 $2, $4, 255 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i32_255: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: andi16 $2, $4, 255 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i32_255: - - ; GP32: andi $2, $4, 255 - - ; GP64: andi $2, $4, 255 - - ; MM: andi16 $2, $4, 255 - %r = and i32 255, %b ret i32 %r } define signext i64 @and_i64_255(i64 signext %b) { +; MIPS-LABEL: and_i64_255: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: andi $3, $5, 255 +; MIPS-NEXT: jr $ra +; MIPS-NEXT: addiu $2, $zero, 0 +; +; MIPS32R2-LABEL: and_i64_255: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: andi $3, $5, 255 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: addiu $2, $zero, 0 +; +; MIPS32R6-LABEL: and_i64_255: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: andi $3, $5, 255 +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: addiu $2, $zero, 0 +; +; MIPS64-LABEL: and_i64_255: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: andi $2, $4, 255 +; +; MIPS64R2-LABEL: and_i64_255: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: andi $2, $4, 255 +; +; MIPS64R6-LABEL: and_i64_255: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: andi $2, $4, 255 +; +; MM32R3-LABEL: and_i64_255: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: andi16 $3, $5, 255 +; MM32R3-NEXT: li16 $2, 0 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i64_255: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: andi16 $3, $5, 255 +; MM32R6-NEXT: li16 $2, 0 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i64_255: - - ; GP32: andi $3, $5, 255 - ; GP32: addiu $2, $zero, 0 - - ; GP64: andi $2, $4, 255 - - ; MM32: andi16 $3, $5, 255 - ; MM32: li16 $2, 0 - %r = and i64 255, %b ret i64 %r } define signext i128 @and_i128_255(i128 signext %b) { +; MIPS-LABEL: and_i128_255: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: andi $5, $7, 255 +; MIPS-NEXT: addiu $2, $zero, 0 +; MIPS-NEXT: addiu $3, $zero, 0 +; MIPS-NEXT: jr $ra +; MIPS-NEXT: addiu $4, $zero, 0 +; +; MIPS32R2-LABEL: and_i128_255: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: andi $5, $7, 255 +; MIPS32R2-NEXT: addiu $2, $zero, 0 +; MIPS32R2-NEXT: addiu $3, $zero, 0 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: addiu $4, $zero, 0 +; +; MIPS32R6-LABEL: and_i128_255: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: andi $5, $7, 255 +; MIPS32R6-NEXT: addiu $2, $zero, 0 +; MIPS32R6-NEXT: addiu $3, $zero, 0 +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: addiu $4, $zero, 0 +; +; MIPS64-LABEL: and_i128_255: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: andi $3, $5, 255 +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: daddiu $2, $zero, 0 +; +; MIPS64R2-LABEL: and_i128_255: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: andi $3, $5, 255 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: daddiu $2, $zero, 0 +; +; MIPS64R6-LABEL: and_i128_255: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: andi $3, $5, 255 +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: daddiu $2, $zero, 0 +; +; MM32R3-LABEL: and_i128_255: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: andi16 $5, $7, 255 +; MM32R3-NEXT: li16 $2, 0 +; MM32R3-NEXT: li16 $3, 0 +; MM32R3-NEXT: li16 $4, 0 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i128_255: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: andi16 $5, $7, 255 +; MM32R6-NEXT: li16 $2, 0 +; MM32R6-NEXT: li16 $3, 0 +; MM32R6-NEXT: li16 $4, 0 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i128_255: - - ; GP32: andi $5, $7, 255 - ; GP32: addiu $2, $zero, 0 - ; GP32: addiu $3, $zero, 0 - ; GP32: addiu $4, $zero, 0 - - ; GP64: andi $3, $5, 255 - ; GP64: daddiu $2, $zero, 0 - - ; MM32: andi16 $5, $7, 255 - ; MM32: li16 $2, 0 - ; MM32: li16 $3, 0 - ; MM32: li16 $4, 0 - %r = and i128 255, %b ret i128 %r } define signext i1 @and_i1_32768(i1 signext %b) { +; MIPS-LABEL: and_i1_32768: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: addiu $2, $zero, 0 +; +; MIPS32R2-LABEL: and_i1_32768: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: addiu $2, $zero, 0 +; +; MIPS32R6-LABEL: and_i1_32768: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: addiu $2, $zero, 0 +; +; MIPS64-LABEL: and_i1_32768: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: addiu $2, $zero, 0 +; +; MIPS64R2-LABEL: and_i1_32768: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: addiu $2, $zero, 0 +; +; MIPS64R6-LABEL: and_i1_32768: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: addiu $2, $zero, 0 +; +; MM32R3-LABEL: and_i1_32768: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: li16 $2, 0 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i1_32768: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: li16 $2, 0 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i1_32768: - - ; GP32: addiu $2, $zero, 0 - - ; GP64: addiu $2, $zero, 0 - - ; MM: li16 $2, 0 - %r = and i1 32768, %b ret i1 %r } define signext i8 @and_i8_32768(i8 signext %b) { +; MIPS-LABEL: and_i8_32768: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: addiu $2, $zero, 0 +; +; MIPS32R2-LABEL: and_i8_32768: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: addiu $2, $zero, 0 +; +; MIPS32R6-LABEL: and_i8_32768: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: addiu $2, $zero, 0 +; +; MIPS64-LABEL: and_i8_32768: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: addiu $2, $zero, 0 +; +; MIPS64R2-LABEL: and_i8_32768: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: addiu $2, $zero, 0 +; +; MIPS64R6-LABEL: and_i8_32768: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: addiu $2, $zero, 0 +; +; MM32R3-LABEL: and_i8_32768: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: li16 $2, 0 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i8_32768: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: li16 $2, 0 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i8_32768: - - ; GP32: addiu $2, $zero, 0 - - ; GP64: addiu $2, $zero, 0 - - ; MM: li16 $2, 0 - %r = and i8 32768, %b ret i8 %r } define signext i16 @and_i16_32768(i16 signext %b) { +; MIPS-LABEL: and_i16_32768: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: addiu $1, $zero, -32768 +; MIPS-NEXT: jr $ra +; MIPS-NEXT: and $2, $4, $1 +; +; MIPS32R2-LABEL: and_i16_32768: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: addiu $1, $zero, -32768 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: and $2, $4, $1 +; +; MIPS32R6-LABEL: and_i16_32768: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: addiu $1, $zero, -32768 +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: and $2, $4, $1 +; +; MIPS64-LABEL: and_i16_32768: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: addiu $1, $zero, -32768 +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: and $2, $4, $1 +; +; MIPS64R2-LABEL: and_i16_32768: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: addiu $1, $zero, -32768 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: and $2, $4, $1 +; +; MIPS64R6-LABEL: and_i16_32768: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: addiu $1, $zero, -32768 +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: and $2, $4, $1 +; +; MM32R3-LABEL: and_i16_32768: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: addiu $2, $zero, -32768 +; MM32R3-NEXT: and16 $2, $4 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i16_32768: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: addiu $2, $zero, -32768 +; MM32R6-NEXT: and16 $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i16_32768: - - ; GP32: addiu $[[T0:[0-9]+]], $zero, -32768 - ; GP32: and $2, $4, $[[T0]] - - ; GP64: addiu $[[T0:[0-9]+]], $zero, -32768 - ; GP64: and $2, $4, $[[T0]] - - ; MM: addiu $2, $zero, -32768 - ; MM: and16 $2, $4 %r = and i16 32768, %b ret i16 %r } define signext i32 @and_i32_32768(i32 signext %b) { +; MIPS-LABEL: and_i32_32768: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: andi $2, $4, 32768 +; +; MIPS32R2-LABEL: and_i32_32768: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: andi $2, $4, 32768 +; +; MIPS32R6-LABEL: and_i32_32768: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: andi $2, $4, 32768 +; +; MIPS64-LABEL: and_i32_32768: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: andi $2, $4, 32768 +; +; MIPS64R2-LABEL: and_i32_32768: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: andi $2, $4, 32768 +; +; MIPS64R6-LABEL: and_i32_32768: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: andi $2, $4, 32768 +; +; MM32R3-LABEL: and_i32_32768: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: andi16 $2, $4, 32768 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i32_32768: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: andi16 $2, $4, 32768 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i32_32768: - - ; GP32: andi $2, $4, 32768 - - ; GP64: andi $2, $4, 32768 - - ; MM: andi16 $2, $4, 32768 - %r = and i32 32768, %b ret i32 %r } define signext i64 @and_i64_32768(i64 signext %b) { +; MIPS-LABEL: and_i64_32768: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: andi $3, $5, 32768 +; MIPS-NEXT: jr $ra +; MIPS-NEXT: addiu $2, $zero, 0 +; +; MIPS32R2-LABEL: and_i64_32768: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: andi $3, $5, 32768 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: addiu $2, $zero, 0 +; +; MIPS32R6-LABEL: and_i64_32768: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: andi $3, $5, 32768 +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: addiu $2, $zero, 0 +; +; MIPS64-LABEL: and_i64_32768: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: andi $2, $4, 32768 +; +; MIPS64R2-LABEL: and_i64_32768: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: andi $2, $4, 32768 +; +; MIPS64R6-LABEL: and_i64_32768: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: andi $2, $4, 32768 +; +; MM32R3-LABEL: and_i64_32768: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: andi16 $3, $5, 32768 +; MM32R3-NEXT: li16 $2, 0 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i64_32768: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: andi16 $3, $5, 32768 +; MM32R6-NEXT: li16 $2, 0 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i64_32768: - - ; GP32: andi $3, $5, 32768 - ; GP32: addiu $2, $zero, 0 - - ; GP64: andi $2, $4, 32768 - - ; MM32: andi16 $3, $5, 32768 - ; MM32: li16 $2, 0 - %r = and i64 32768, %b ret i64 %r } define signext i128 @and_i128_32768(i128 signext %b) { +; MIPS-LABEL: and_i128_32768: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: andi $5, $7, 32768 +; MIPS-NEXT: addiu $2, $zero, 0 +; MIPS-NEXT: addiu $3, $zero, 0 +; MIPS-NEXT: jr $ra +; MIPS-NEXT: addiu $4, $zero, 0 +; +; MIPS32R2-LABEL: and_i128_32768: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: andi $5, $7, 32768 +; MIPS32R2-NEXT: addiu $2, $zero, 0 +; MIPS32R2-NEXT: addiu $3, $zero, 0 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: addiu $4, $zero, 0 +; +; MIPS32R6-LABEL: and_i128_32768: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: andi $5, $7, 32768 +; MIPS32R6-NEXT: addiu $2, $zero, 0 +; MIPS32R6-NEXT: addiu $3, $zero, 0 +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: addiu $4, $zero, 0 +; +; MIPS64-LABEL: and_i128_32768: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: andi $3, $5, 32768 +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: daddiu $2, $zero, 0 +; +; MIPS64R2-LABEL: and_i128_32768: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: andi $3, $5, 32768 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: daddiu $2, $zero, 0 +; +; MIPS64R6-LABEL: and_i128_32768: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: andi $3, $5, 32768 +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: daddiu $2, $zero, 0 +; +; MM32R3-LABEL: and_i128_32768: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: andi16 $5, $7, 32768 +; MM32R3-NEXT: li16 $2, 0 +; MM32R3-NEXT: li16 $3, 0 +; MM32R3-NEXT: li16 $4, 0 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i128_32768: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: andi16 $5, $7, 32768 +; MM32R6-NEXT: li16 $2, 0 +; MM32R6-NEXT: li16 $3, 0 +; MM32R6-NEXT: li16 $4, 0 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i128_32768: - - ; GP32: andi $5, $7, 32768 - ; GP32: addiu $2, $zero, 0 - ; GP32: addiu $3, $zero, 0 - ; GP32: addiu $4, $zero, 0 - - ; GP64: andi $3, $5, 32768 - ; GP64: daddiu $2, $zero, 0 - - ; MM32: andi16 $5, $7, 32768 - ; MM32: li16 $2, 0 - ; MM32: li16 $3, 0 - ; MM32: li16 $4, 0 - %r = and i128 32768, %b ret i128 %r } define signext i1 @and_i1_65(i1 signext %b) { +; MIPS-LABEL: and_i1_65: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: move $2, $4 +; +; MIPS32R2-LABEL: and_i1_65: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: move $2, $4 +; +; MIPS32R6-LABEL: and_i1_65: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: move $2, $4 +; +; MIPS64-LABEL: and_i1_65: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: move $2, $4 +; +; MIPS64R2-LABEL: and_i1_65: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: move $2, $4 +; +; MIPS64R6-LABEL: and_i1_65: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: move $2, $4 +; +; MM32R3-LABEL: and_i1_65: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: move $2, $4 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i1_65: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i1_65: - - ; ALL: move $2, $4 - %r = and i1 65, %b ret i1 %r } define signext i8 @and_i8_65(i8 signext %b) { +; MIPS-LABEL: and_i8_65: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: andi $2, $4, 65 +; +; MIPS32R2-LABEL: and_i8_65: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: andi $2, $4, 65 +; +; MIPS32R6-LABEL: and_i8_65: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: andi $2, $4, 65 +; +; MIPS64-LABEL: and_i8_65: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: andi $2, $4, 65 +; +; MIPS64R2-LABEL: and_i8_65: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: andi $2, $4, 65 +; +; MIPS64R6-LABEL: and_i8_65: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: andi $2, $4, 65 +; +; MM32R3-LABEL: and_i8_65: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: jr $ra +; MM32R3-NEXT: andi $2, $4, 65 +; +; MM32R6-LABEL: and_i8_65: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: andi $2, $4, 65 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i8_65: - - ; ALL: andi $2, $4, 65 - %r = and i8 65, %b ret i8 %r } define signext i16 @and_i16_65(i16 signext %b) { +; MIPS-LABEL: and_i16_65: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: andi $2, $4, 65 +; +; MIPS32R2-LABEL: and_i16_65: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: andi $2, $4, 65 +; +; MIPS32R6-LABEL: and_i16_65: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: andi $2, $4, 65 +; +; MIPS64-LABEL: and_i16_65: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: andi $2, $4, 65 +; +; MIPS64R2-LABEL: and_i16_65: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: andi $2, $4, 65 +; +; MIPS64R6-LABEL: and_i16_65: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: andi $2, $4, 65 +; +; MM32R3-LABEL: and_i16_65: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: jr $ra +; MM32R3-NEXT: andi $2, $4, 65 +; +; MM32R6-LABEL: and_i16_65: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: andi $2, $4, 65 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i16_65: - - ; ALL: andi $2, $4, 65 - %r = and i16 65, %b ret i16 %r } define signext i32 @and_i32_65(i32 signext %b) { +; MIPS-LABEL: and_i32_65: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: andi $2, $4, 65 +; +; MIPS32R2-LABEL: and_i32_65: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: andi $2, $4, 65 +; +; MIPS32R6-LABEL: and_i32_65: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: andi $2, $4, 65 +; +; MIPS64-LABEL: and_i32_65: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: andi $2, $4, 65 +; +; MIPS64R2-LABEL: and_i32_65: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: andi $2, $4, 65 +; +; MIPS64R6-LABEL: and_i32_65: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: andi $2, $4, 65 +; +; MM32R3-LABEL: and_i32_65: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: jr $ra +; MM32R3-NEXT: andi $2, $4, 65 +; +; MM32R6-LABEL: and_i32_65: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: andi $2, $4, 65 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i32_65: - - ; ALL: andi $2, $4, 65 - %r = and i32 65, %b ret i32 %r } define signext i64 @and_i64_65(i64 signext %b) { +; MIPS-LABEL: and_i64_65: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: andi $3, $5, 65 +; MIPS-NEXT: jr $ra +; MIPS-NEXT: addiu $2, $zero, 0 +; +; MIPS32R2-LABEL: and_i64_65: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: andi $3, $5, 65 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: addiu $2, $zero, 0 +; +; MIPS32R6-LABEL: and_i64_65: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: andi $3, $5, 65 +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: addiu $2, $zero, 0 +; +; MIPS64-LABEL: and_i64_65: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: andi $2, $4, 65 +; +; MIPS64R2-LABEL: and_i64_65: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: andi $2, $4, 65 +; +; MIPS64R6-LABEL: and_i64_65: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: andi $2, $4, 65 +; +; MM32R3-LABEL: and_i64_65: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: li16 $2, 0 +; MM32R3-NEXT: jr $ra +; MM32R3-NEXT: andi $3, $5, 65 +; +; MM32R6-LABEL: and_i64_65: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: andi $3, $5, 65 +; MM32R6-NEXT: li16 $2, 0 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i64_65: - - ; GP32: andi $3, $5, 65 - ; GP32: addiu $2, $zero, 0 - - ; GP64: andi $2, $4, 65 - - ; MM32-DAG: andi $3, $5, 65 - ; MM32-DAG: li16 $2, 0 - %r = and i64 65, %b ret i64 %r } define signext i128 @and_i128_65(i128 signext %b) { +; MIPS-LABEL: and_i128_65: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: andi $5, $7, 65 +; MIPS-NEXT: addiu $2, $zero, 0 +; MIPS-NEXT: addiu $3, $zero, 0 +; MIPS-NEXT: jr $ra +; MIPS-NEXT: addiu $4, $zero, 0 +; +; MIPS32R2-LABEL: and_i128_65: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: andi $5, $7, 65 +; MIPS32R2-NEXT: addiu $2, $zero, 0 +; MIPS32R2-NEXT: addiu $3, $zero, 0 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: addiu $4, $zero, 0 +; +; MIPS32R6-LABEL: and_i128_65: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: andi $5, $7, 65 +; MIPS32R6-NEXT: addiu $2, $zero, 0 +; MIPS32R6-NEXT: addiu $3, $zero, 0 +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: addiu $4, $zero, 0 +; +; MIPS64-LABEL: and_i128_65: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: andi $3, $5, 65 +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: daddiu $2, $zero, 0 +; +; MIPS64R2-LABEL: and_i128_65: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: andi $3, $5, 65 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: daddiu $2, $zero, 0 +; +; MIPS64R6-LABEL: and_i128_65: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: andi $3, $5, 65 +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: daddiu $2, $zero, 0 +; +; MM32R3-LABEL: and_i128_65: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: li16 $2, 0 +; MM32R3-NEXT: li16 $3, 0 +; MM32R3-NEXT: li16 $4, 0 +; MM32R3-NEXT: jr $ra +; MM32R3-NEXT: andi $5, $7, 65 +; +; MM32R6-LABEL: and_i128_65: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: andi $5, $7, 65 +; MM32R6-NEXT: li16 $2, 0 +; MM32R6-NEXT: li16 $3, 0 +; MM32R6-NEXT: li16 $4, 0 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i128_65: - - ; GP32: andi $5, $7, 65 - ; GP32: addiu $2, $zero, 0 - ; GP32: addiu $3, $zero, 0 - ; GP32: addiu $4, $zero, 0 - - ; GP64: andi $3, $5, 65 - ; GP64: daddiu $2, $zero, 0 - - ; MM32-DAG: andi $5, $7, 65 - ; MM32-DAG: li16 $2, 0 - ; MM32-DAG: li16 $3, 0 - ; MM32-DAG: li16 $4, 0 - %r = and i128 65, %b ret i128 %r } define signext i1 @and_i1_256(i1 signext %b) { +; MIPS-LABEL: and_i1_256: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: addiu $2, $zero, 0 +; +; MIPS32R2-LABEL: and_i1_256: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: addiu $2, $zero, 0 +; +; MIPS32R6-LABEL: and_i1_256: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: addiu $2, $zero, 0 +; +; MIPS64-LABEL: and_i1_256: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: addiu $2, $zero, 0 +; +; MIPS64R2-LABEL: and_i1_256: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: addiu $2, $zero, 0 +; +; MIPS64R6-LABEL: and_i1_256: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: addiu $2, $zero, 0 +; +; MM32R3-LABEL: and_i1_256: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: li16 $2, 0 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i1_256: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: li16 $2, 0 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i1_256: - - ; GP32: addiu $2, $zero, 0 - - ; GP64: addiu $2, $zero, 0 - - ; MM: li16 $2, 0 - %r = and i1 256, %b ret i1 %r } define signext i8 @and_i8_256(i8 signext %b) { +; MIPS-LABEL: and_i8_256: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: addiu $2, $zero, 0 +; +; MIPS32R2-LABEL: and_i8_256: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: addiu $2, $zero, 0 +; +; MIPS32R6-LABEL: and_i8_256: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: addiu $2, $zero, 0 +; +; MIPS64-LABEL: and_i8_256: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: addiu $2, $zero, 0 +; +; MIPS64R2-LABEL: and_i8_256: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: addiu $2, $zero, 0 +; +; MIPS64R6-LABEL: and_i8_256: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: addiu $2, $zero, 0 +; +; MM32R3-LABEL: and_i8_256: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: li16 $2, 0 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i8_256: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: li16 $2, 0 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i8_256: - - ; GP32: addiu $2, $zero, 0 - - ; GP64: addiu $2, $zero, 0 - - ; MM: li16 $2, 0 - %r = and i8 256, %b ret i8 %r } define signext i16 @and_i16_256(i16 signext %b) { +; MIPS-LABEL: and_i16_256: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: andi $2, $4, 256 +; +; MIPS32R2-LABEL: and_i16_256: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: andi $2, $4, 256 +; +; MIPS32R6-LABEL: and_i16_256: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: andi $2, $4, 256 +; +; MIPS64-LABEL: and_i16_256: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: andi $2, $4, 256 +; +; MIPS64R2-LABEL: and_i16_256: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: andi $2, $4, 256 +; +; MIPS64R6-LABEL: and_i16_256: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: andi $2, $4, 256 +; +; MM32R3-LABEL: and_i16_256: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: jr $ra +; MM32R3-NEXT: andi $2, $4, 256 +; +; MM32R6-LABEL: and_i16_256: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: andi $2, $4, 256 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i16_256: - - ; ALL: andi $2, $4, 256 - %r = and i16 256, %b ret i16 %r } define signext i32 @and_i32_256(i32 signext %b) { +; MIPS-LABEL: and_i32_256: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: andi $2, $4, 256 +; +; MIPS32R2-LABEL: and_i32_256: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: andi $2, $4, 256 +; +; MIPS32R6-LABEL: and_i32_256: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: andi $2, $4, 256 +; +; MIPS64-LABEL: and_i32_256: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: andi $2, $4, 256 +; +; MIPS64R2-LABEL: and_i32_256: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: andi $2, $4, 256 +; +; MIPS64R6-LABEL: and_i32_256: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: andi $2, $4, 256 +; +; MM32R3-LABEL: and_i32_256: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: jr $ra +; MM32R3-NEXT: andi $2, $4, 256 +; +; MM32R6-LABEL: and_i32_256: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: andi $2, $4, 256 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i32_256: - - ; ALL: andi $2, $4, 256 - %r = and i32 256, %b ret i32 %r } define signext i64 @and_i64_256(i64 signext %b) { +; MIPS-LABEL: and_i64_256: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: andi $3, $5, 256 +; MIPS-NEXT: jr $ra +; MIPS-NEXT: addiu $2, $zero, 0 +; +; MIPS32R2-LABEL: and_i64_256: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: andi $3, $5, 256 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: addiu $2, $zero, 0 +; +; MIPS32R6-LABEL: and_i64_256: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: andi $3, $5, 256 +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: addiu $2, $zero, 0 +; +; MIPS64-LABEL: and_i64_256: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: andi $2, $4, 256 +; +; MIPS64R2-LABEL: and_i64_256: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: andi $2, $4, 256 +; +; MIPS64R6-LABEL: and_i64_256: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: andi $2, $4, 256 +; +; MM32R3-LABEL: and_i64_256: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: li16 $2, 0 +; MM32R3-NEXT: jr $ra +; MM32R3-NEXT: andi $3, $5, 256 +; +; MM32R6-LABEL: and_i64_256: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: andi $3, $5, 256 +; MM32R6-NEXT: li16 $2, 0 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i64_256: - - ; GP32: andi $3, $5, 256 - ; GP32: addiu $2, $zero, 0 - - ; GP64: andi $2, $4, 256 - - ; MM32-DAG: andi $3, $5, 256 - ; MM32-DAG: li16 $2, 0 - %r = and i64 256, %b ret i64 %r } define signext i128 @and_i128_256(i128 signext %b) { +; MIPS-LABEL: and_i128_256: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: andi $5, $7, 256 +; MIPS-NEXT: addiu $2, $zero, 0 +; MIPS-NEXT: addiu $3, $zero, 0 +; MIPS-NEXT: jr $ra +; MIPS-NEXT: addiu $4, $zero, 0 +; +; MIPS32R2-LABEL: and_i128_256: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: andi $5, $7, 256 +; MIPS32R2-NEXT: addiu $2, $zero, 0 +; MIPS32R2-NEXT: addiu $3, $zero, 0 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: addiu $4, $zero, 0 +; +; MIPS32R6-LABEL: and_i128_256: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: andi $5, $7, 256 +; MIPS32R6-NEXT: addiu $2, $zero, 0 +; MIPS32R6-NEXT: addiu $3, $zero, 0 +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: addiu $4, $zero, 0 +; +; MIPS64-LABEL: and_i128_256: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: andi $3, $5, 256 +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: daddiu $2, $zero, 0 +; +; MIPS64R2-LABEL: and_i128_256: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: andi $3, $5, 256 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: daddiu $2, $zero, 0 +; +; MIPS64R6-LABEL: and_i128_256: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: andi $3, $5, 256 +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: daddiu $2, $zero, 0 +; +; MM32R3-LABEL: and_i128_256: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: li16 $2, 0 +; MM32R3-NEXT: li16 $3, 0 +; MM32R3-NEXT: li16 $4, 0 +; MM32R3-NEXT: jr $ra +; MM32R3-NEXT: andi $5, $7, 256 +; +; MM32R6-LABEL: and_i128_256: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: andi $5, $7, 256 +; MM32R6-NEXT: li16 $2, 0 +; MM32R6-NEXT: li16 $3, 0 +; MM32R6-NEXT: li16 $4, 0 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i128_256: - - ; GP32: andi $5, $7, 256 - ; GP32: addiu $2, $zero, 0 - ; GP32: addiu $3, $zero, 0 - ; GP32: addiu $4, $zero, 0 - - ; GP64: andi $3, $5, 256 - ; GP64: daddiu $2, $zero, 0 - - ; MM32-DAG: andi $5, $7, 256 - ; MM32-DAG: li16 $2, 0 - ; MM32-DAG: li16 $3, 0 - ; MM32-DAG: li16 $4, 0 - %r = and i128 256, %b ret i128 %r } diff --git a/test/CodeGen/Mips/llvm-ir/ashr.ll b/test/CodeGen/Mips/llvm-ir/ashr.ll index f9fb91be090..ec1e9b03b45 100644 --- a/test/CodeGen/Mips/llvm-ir/ashr.ll +++ b/test/CodeGen/Mips/llvm-ir/ashr.ll @@ -1,225 +1,985 @@ -; RUN: llc < %s -march=mips -mcpu=mips2 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32,M2 -; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32,32R1-R5 -; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32,32R1-R5 -; RUN: llc < %s -march=mips -mcpu=mips32r3 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32,32R1-R5 -; RUN: llc < %s -march=mips -mcpu=mips32r5 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32,32R1-R5 -; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32,32R6 -; RUN: llc < %s -march=mips64 -mcpu=mips3 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64,M3 -; RUN: llc < %s -march=mips64 -mcpu=mips4 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64,64R6 -; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,MM,MMR3 -; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,MM,MMR6 +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS32 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=32R2 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=32R2 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r5 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=32R2 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=32R6 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS3 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips4 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS64 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS64 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS64R2 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS64R2 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r5 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS64R2 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS64R6 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MMR3 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MMR6 define signext i1 @ashr_i1(i1 signext %a, i1 signext %b) { +; MIPS-LABEL: ashr_i1: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: move $2, $4 +; +; MIPS32-LABEL: ashr_i1: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: move $2, $4 +; +; 32R2-LABEL: ashr_i1: +; 32R2: # %bb.0: # %entry +; 32R2-NEXT: jr $ra +; 32R2-NEXT: move $2, $4 +; +; 32R6-LABEL: ashr_i1: +; 32R6: # %bb.0: # %entry +; 32R6-NEXT: jr $ra +; 32R6-NEXT: move $2, $4 +; +; MIPS3-LABEL: ashr_i1: +; MIPS3: # %bb.0: # %entry +; MIPS3-NEXT: jr $ra +; MIPS3-NEXT: move $2, $4 +; +; MIPS64-LABEL: ashr_i1: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: move $2, $4 +; +; MIPS64R2-LABEL: ashr_i1: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: move $2, $4 +; +; MIPS64R6-LABEL: ashr_i1: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: move $2, $4 +; +; MMR3-LABEL: ashr_i1: +; MMR3: # %bb.0: # %entry +; MMR3-NEXT: move $2, $4 +; MMR3-NEXT: jrc $ra +; +; MMR6-LABEL: ashr_i1: +; MMR6: # %bb.0: # %entry +; MMR6-NEXT: move $2, $4 +; MMR6-NEXT: jrc $ra entry: -; ALL-LABEL: ashr_i1: - - ; ALL: move $2, $4 - %r = ashr i1 %a, %b ret i1 %r } define signext i8 @ashr_i8(i8 signext %a, i8 signext %b) { +; MIPS-LABEL: ashr_i8: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: andi $1, $5, 255 +; MIPS-NEXT: jr $ra +; MIPS-NEXT: srav $2, $4, $1 +; +; MIPS32-LABEL: ashr_i8: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: andi $1, $5, 255 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: srav $2, $4, $1 +; +; 32R2-LABEL: ashr_i8: +; 32R2: # %bb.0: # %entry +; 32R2-NEXT: andi $1, $5, 255 +; 32R2-NEXT: jr $ra +; 32R2-NEXT: srav $2, $4, $1 +; +; 32R6-LABEL: ashr_i8: +; 32R6: # %bb.0: # %entry +; 32R6-NEXT: andi $1, $5, 255 +; 32R6-NEXT: jr $ra +; 32R6-NEXT: srav $2, $4, $1 +; +; MIPS3-LABEL: ashr_i8: +; MIPS3: # %bb.0: # %entry +; MIPS3-NEXT: andi $1, $5, 255 +; MIPS3-NEXT: jr $ra +; MIPS3-NEXT: srav $2, $4, $1 +; +; MIPS64-LABEL: ashr_i8: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: andi $1, $5, 255 +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: srav $2, $4, $1 +; +; MIPS64R2-LABEL: ashr_i8: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: andi $1, $5, 255 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: srav $2, $4, $1 +; +; MIPS64R6-LABEL: ashr_i8: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: andi $1, $5, 255 +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: srav $2, $4, $1 +; +; MMR3-LABEL: ashr_i8: +; MMR3: # %bb.0: # %entry +; MMR3-NEXT: andi16 $2, $5, 255 +; MMR3-NEXT: jr $ra +; MMR3-NEXT: srav $2, $4, $2 +; +; MMR6-LABEL: ashr_i8: +; MMR6: # %bb.0: # %entry +; MMR6-NEXT: andi16 $2, $5, 255 +; MMR6-NEXT: srav $2, $4, $2 +; MMR6-NEXT: jrc $ra entry: -; ALL-LABEL: ashr_i8: - ; FIXME: The andi instruction is redundant. - ; GP32: andi $[[T0:[0-9]+]], $5, 255 - ; GP64: andi $[[T0:[0-9]+]], $5, 255 - ; MM: andi16 $[[T0:[0-9]+]], $5, 255 - ; ALL: srav $2, $4, $[[T0]] - %r = ashr i8 %a, %b ret i8 %r } define signext i16 @ashr_i16(i16 signext %a, i16 signext %b) { +; MIPS-LABEL: ashr_i16: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: andi $1, $5, 65535 +; MIPS-NEXT: jr $ra +; MIPS-NEXT: srav $2, $4, $1 +; +; MIPS32-LABEL: ashr_i16: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: andi $1, $5, 65535 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: srav $2, $4, $1 +; +; 32R2-LABEL: ashr_i16: +; 32R2: # %bb.0: # %entry +; 32R2-NEXT: andi $1, $5, 65535 +; 32R2-NEXT: jr $ra +; 32R2-NEXT: srav $2, $4, $1 +; +; 32R6-LABEL: ashr_i16: +; 32R6: # %bb.0: # %entry +; 32R6-NEXT: andi $1, $5, 65535 +; 32R6-NEXT: jr $ra +; 32R6-NEXT: srav $2, $4, $1 +; +; MIPS3-LABEL: ashr_i16: +; MIPS3: # %bb.0: # %entry +; MIPS3-NEXT: andi $1, $5, 65535 +; MIPS3-NEXT: jr $ra +; MIPS3-NEXT: srav $2, $4, $1 +; +; MIPS64-LABEL: ashr_i16: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: andi $1, $5, 65535 +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: srav $2, $4, $1 +; +; MIPS64R2-LABEL: ashr_i16: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: andi $1, $5, 65535 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: srav $2, $4, $1 +; +; MIPS64R6-LABEL: ashr_i16: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: andi $1, $5, 65535 +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: srav $2, $4, $1 +; +; MMR3-LABEL: ashr_i16: +; MMR3: # %bb.0: # %entry +; MMR3-NEXT: andi16 $2, $5, 65535 +; MMR3-NEXT: jr $ra +; MMR3-NEXT: srav $2, $4, $2 +; +; MMR6-LABEL: ashr_i16: +; MMR6: # %bb.0: # %entry +; MMR6-NEXT: andi16 $2, $5, 65535 +; MMR6-NEXT: srav $2, $4, $2 +; MMR6-NEXT: jrc $ra entry: -; ALL-LABEL: ashr_i16: - ; FIXME: The andi instruction is redundant. - ; GP32: andi $[[T0:[0-9]+]], $5, 65535 - ; GP64: andi $[[T0:[0-9]+]], $5, 65535 - ; MM: andi16 $[[T0:[0-9]+]], $5, 65535 - ; ALL: srav $2, $4, $[[T0]] - %r = ashr i16 %a, %b ret i16 %r } define signext i32 @ashr_i32(i32 signext %a, i32 signext %b) { +; MIPS-LABEL: ashr_i32: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: srav $2, $4, $5 +; +; MIPS32-LABEL: ashr_i32: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: srav $2, $4, $5 +; +; 32R2-LABEL: ashr_i32: +; 32R2: # %bb.0: # %entry +; 32R2-NEXT: jr $ra +; 32R2-NEXT: srav $2, $4, $5 +; +; 32R6-LABEL: ashr_i32: +; 32R6: # %bb.0: # %entry +; 32R6-NEXT: jr $ra +; 32R6-NEXT: srav $2, $4, $5 +; +; MIPS3-LABEL: ashr_i32: +; MIPS3: # %bb.0: # %entry +; MIPS3-NEXT: jr $ra +; MIPS3-NEXT: srav $2, $4, $5 +; +; MIPS64-LABEL: ashr_i32: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: srav $2, $4, $5 +; +; MIPS64R2-LABEL: ashr_i32: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: srav $2, $4, $5 +; +; MIPS64R6-LABEL: ashr_i32: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: srav $2, $4, $5 +; +; MMR3-LABEL: ashr_i32: +; MMR3: # %bb.0: # %entry +; MMR3-NEXT: jr $ra +; MMR3-NEXT: srav $2, $4, $5 +; +; MMR6-LABEL: ashr_i32: +; MMR6: # %bb.0: # %entry +; MMR6-NEXT: srav $2, $4, $5 +; MMR6-NEXT: jrc $ra entry: -; ALL-LABEL: ashr_i32: - - ; ALL: srav $2, $4, $5 - %r = ashr i32 %a, %b ret i32 %r } define signext i64 @ashr_i64(i64 signext %a, i64 signext %b) { +; MIPS-LABEL: ashr_i64: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: srav $2, $4, $7 +; MIPS-NEXT: andi $6, $7, 32 +; MIPS-NEXT: beqz $6, $BB4_3 +; MIPS-NEXT: move $3, $2 +; MIPS-NEXT: # %bb.1: # %entry +; MIPS-NEXT: bnez $6, $BB4_4 +; MIPS-NEXT: nop +; MIPS-NEXT: $BB4_2: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: nop +; MIPS-NEXT: $BB4_3: # %entry +; MIPS-NEXT: srlv $1, $5, $7 +; MIPS-NEXT: not $3, $7 +; MIPS-NEXT: sll $5, $4, 1 +; MIPS-NEXT: sllv $3, $5, $3 +; MIPS-NEXT: beqz $6, $BB4_2 +; MIPS-NEXT: or $3, $3, $1 +; MIPS-NEXT: $BB4_4: +; MIPS-NEXT: jr $ra +; MIPS-NEXT: sra $2, $4, 31 +; +; MIPS32-LABEL: ashr_i64: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: srlv $1, $5, $7 +; MIPS32-NEXT: not $2, $7 +; MIPS32-NEXT: sll $3, $4, 1 +; MIPS32-NEXT: sllv $2, $3, $2 +; MIPS32-NEXT: or $3, $2, $1 +; MIPS32-NEXT: srav $2, $4, $7 +; MIPS32-NEXT: andi $1, $7, 32 +; MIPS32-NEXT: movn $3, $2, $1 +; MIPS32-NEXT: sra $4, $4, 31 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: movn $2, $4, $1 +; +; 32R2-LABEL: ashr_i64: +; 32R2: # %bb.0: # %entry +; 32R2-NEXT: srlv $1, $5, $7 +; 32R2-NEXT: not $2, $7 +; 32R2-NEXT: sll $3, $4, 1 +; 32R2-NEXT: sllv $2, $3, $2 +; 32R2-NEXT: or $3, $2, $1 +; 32R2-NEXT: srav $2, $4, $7 +; 32R2-NEXT: andi $1, $7, 32 +; 32R2-NEXT: movn $3, $2, $1 +; 32R2-NEXT: sra $4, $4, 31 +; 32R2-NEXT: jr $ra +; 32R2-NEXT: movn $2, $4, $1 +; +; 32R6-LABEL: ashr_i64: +; 32R6: # %bb.0: # %entry +; 32R6-NEXT: srav $1, $4, $7 +; 32R6-NEXT: andi $3, $7, 32 +; 32R6-NEXT: seleqz $2, $1, $3 +; 32R6-NEXT: sra $6, $4, 31 +; 32R6-NEXT: selnez $6, $6, $3 +; 32R6-NEXT: or $2, $6, $2 +; 32R6-NEXT: srlv $5, $5, $7 +; 32R6-NEXT: not $6, $7 +; 32R6-NEXT: sll $4, $4, 1 +; 32R6-NEXT: sllv $4, $4, $6 +; 32R6-NEXT: or $4, $4, $5 +; 32R6-NEXT: seleqz $4, $4, $3 +; 32R6-NEXT: selnez $1, $1, $3 +; 32R6-NEXT: jr $ra +; 32R6-NEXT: or $3, $1, $4 +; +; MIPS3-LABEL: ashr_i64: +; MIPS3: # %bb.0: # %entry +; MIPS3-NEXT: jr $ra +; MIPS3-NEXT: dsrav $2, $4, $5 +; +; MIPS64-LABEL: ashr_i64: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: dsrav $2, $4, $5 +; +; MIPS64R2-LABEL: ashr_i64: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: dsrav $2, $4, $5 +; +; MIPS64R6-LABEL: ashr_i64: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: dsrav $2, $4, $5 +; +; MMR3-LABEL: ashr_i64: +; MMR3: # %bb.0: # %entry +; MMR3-NEXT: srlv $2, $5, $7 +; MMR3-NEXT: not16 $3, $7 +; MMR3-NEXT: sll16 $5, $4, 1 +; MMR3-NEXT: sllv $3, $5, $3 +; MMR3-NEXT: or16 $3, $2 +; MMR3-NEXT: srav $2, $4, $7 +; MMR3-NEXT: andi16 $5, $7, 32 +; MMR3-NEXT: movn $3, $2, $5 +; MMR3-NEXT: sra $1, $4, 31 +; MMR3-NEXT: jr $ra +; MMR3-NEXT: movn $2, $1, $5 +; +; MMR6-LABEL: ashr_i64: +; MMR6: # %bb.0: # %entry +; MMR6-NEXT: srav $1, $4, $7 +; MMR6-NEXT: andi16 $3, $7, 32 +; MMR6-NEXT: seleqz $2, $1, $3 +; MMR6-NEXT: sra $6, $4, 31 +; MMR6-NEXT: selnez $6, $6, $3 +; MMR6-NEXT: or $2, $6, $2 +; MMR6-NEXT: srlv $5, $5, $7 +; MMR6-NEXT: not16 $6, $7 +; MMR6-NEXT: sll16 $4, $4, 1 +; MMR6-NEXT: sllv $4, $4, $6 +; MMR6-NEXT: or16 $4, $5 +; MMR6-NEXT: seleqz $4, $4, $3 +; MMR6-NEXT: selnez $1, $1, $3 +; MMR6-NEXT: or $3, $1, $4 +; MMR6-NEXT: jrc $ra entry: -; ALL-LABEL: ashr_i64: - - ; M2: srav $[[T0:[0-9]+]], $4, $7 - ; M2: andi $[[T1:[0-9]+]], $7, 32 - ; M2: beqz $[[T1]], $[[BB0:BB[0-9_]+]] - ; M2: move $3, $[[T0]] - ; M2: bnez $[[T1]], $[[BB1:BB[0-9_]+]] - ; M2: nop - ; M2: $[[EXIT:BB[0-9_]+]]: - ; M2: jr $ra - ; M2: nop - ; M2: $[[BB0]]: - ; M2: srlv $[[T2:[0-9]+]], $5, $7 - ; M2: not $[[T3:[0-9]+]], $7 - ; M2: sll $[[T4:[0-9]+]], $4, 1 - ; M2: sllv $[[T5:[0-9]+]], $[[T4]], $[[T3]] - ; M2: beqz $[[T1]], $[[EXIT]] - ; M2: or $3, $[[T3]], $[[T2]] - ; M2: $[[BB1]]: - ; M2: jr $ra - ; M2: sra $2, $4, 31 - - ; 32R1-R5: srlv $[[T0:[0-9]+]], $5, $7 - ; 32R1-R5: not $[[T1:[0-9]+]], $7 - ; 32R1-R5: sll $[[T2:[0-9]+]], $4, 1 - ; 32R1-R5: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]] - ; 32R1-R5: or $3, $[[T3]], $[[T0]] - ; 32R1-R5: srav $[[T4:[0-9]+]], $4, $7 - ; 32R1-R5: andi $[[T5:[0-9]+]], $7, 32 - ; 32R1-R5: movn $3, $[[T4]], $[[T5]] - ; 32R1-R5: sra $4, $4, 31 - ; 32R1-R5: jr $ra - ; 32R1-R5: movn $2, $4, $[[T5]] - - ; 32R6: srav $[[T0:[0-9]+]], $4, $7 - ; 32R6: andi $[[T1:[0-9]+]], $7, 32 - ; 32R6: seleqz $[[T2:[0-9]+]], $[[T0]], $[[T1]] - ; 32R6: sra $[[T3:[0-9]+]], $4, 31 - ; 32R6: selnez $[[T4:[0-9]+]], $[[T3]], $[[T1]] - ; 32R6: or $[[T5:[0-9]+]], $[[T4]], $[[T2]] - ; 32R6: srlv $[[T6:[0-9]+]], $5, $7 - ; 32R6: not $[[T7:[0-9]+]], $7 - ; 32R6: sll $[[T8:[0-9]+]], $4, 1 - ; 32R6: sllv $[[T9:[0-9]+]], $[[T8]], $[[T7]] - ; 32R6: or $[[T10:[0-9]+]], $[[T9]], $[[T6]] - ; 32R6: seleqz $[[T11:[0-9]+]], $[[T10]], $[[T1]] - ; 32R6: selnez $[[T12:[0-9]+]], $[[T0]], $[[T1]] - ; 32R6: jr $ra - ; 32R6: or $3, $[[T0]], $[[T11]] - - ; GP64: dsrav $2, $4, $5 - - ; MMR3: srlv $[[T0:[0-9]+]], $5, $7 - ; MMR3: not16 $[[T1:[0-9]+]], $7 - ; MMR3: sll16 $[[T2:[0-9]+]], $4, 1 - ; MMR3: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]] - ; MMR3: or16 $[[T4:[0-9]+]], $[[T0]] - ; MMR3: srav $[[T5:[0-9]+]], $4, $7 - ; MMR3: andi16 $[[T6:[0-9]+]], $7, 32 - ; MMR3: movn $[[T7:[0-9]+]], $[[T5]], $[[T6]] - ; MMR3: sra $[[T8:[0-9]+]], $4, 31 - ; MMR3: movn $2, $[[T8]], $[[T6]] - - ; MMR6: srav $[[T0:[0-9]+]], $4, $7 - ; MMR6: andi16 $[[T1:[0-9]+]], $7, 32 - ; MMR6: seleqz $[[T2:[0-9]+]], $[[T0]], $[[T1]] - ; MMR6: sra $[[T3:[0-9]+]], $4, 31 - ; MMR6: selnez $[[T4:[0-9]+]], $[[T3]], $[[T1]] - ; MMR6: or $[[T5:[0-9]+]], $[[T4]], $[[T2]] - ; MMR6: srlv $[[T6:[0-9]+]], $5, $7 - ; MMR6: not16 $[[T7:[0-9]+]], $7 - ; MMR6: sll16 $[[T8:[0-9]+]], $4, 1 - ; MMR6: sllv $[[T9:[0-9]+]], $[[T8]], $[[T7]] - ; MMR6: or16 $[[T10:[0-9]+]], $[[T6]] - ; MMR6: seleqz $[[T11:[0-9]+]], $[[T10]], $[[T1]] - ; MMR6: selnez $[[T12:[0-9]+]], $[[T0]], $[[T1]] - ; MMR6: or $3, $[[T12]], $[[T11]] - %r = ashr i64 %a, %b ret i64 %r } define signext i128 @ashr_i128(i128 signext %a, i128 signext %b) { +; MIPS-LABEL: ashr_i128: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: addiu $sp, $sp, -8 +; MIPS-NEXT: .cfi_def_cfa_offset 8 +; MIPS-NEXT: sw $17, 4($sp) # 4-byte Folded Spill +; MIPS-NEXT: sw $16, 0($sp) # 4-byte Folded Spill +; MIPS-NEXT: .cfi_offset 17, -4 +; MIPS-NEXT: .cfi_offset 16, -8 +; MIPS-NEXT: lw $25, 36($sp) +; MIPS-NEXT: addiu $1, $zero, 64 +; MIPS-NEXT: subu $11, $1, $25 +; MIPS-NEXT: sllv $9, $5, $11 +; MIPS-NEXT: andi $13, $11, 32 +; MIPS-NEXT: addiu $2, $zero, 0 +; MIPS-NEXT: bnez $13, $BB5_2 +; MIPS-NEXT: addiu $3, $zero, 0 +; MIPS-NEXT: # %bb.1: # %entry +; MIPS-NEXT: move $3, $9 +; MIPS-NEXT: $BB5_2: # %entry +; MIPS-NEXT: not $gp, $25 +; MIPS-NEXT: srlv $12, $6, $25 +; MIPS-NEXT: andi $8, $25, 32 +; MIPS-NEXT: bnez $8, $BB5_4 +; MIPS-NEXT: move $15, $12 +; MIPS-NEXT: # %bb.3: # %entry +; MIPS-NEXT: srlv $1, $7, $25 +; MIPS-NEXT: sll $10, $6, 1 +; MIPS-NEXT: sllv $10, $10, $gp +; MIPS-NEXT: or $15, $10, $1 +; MIPS-NEXT: $BB5_4: # %entry +; MIPS-NEXT: addiu $10, $25, -64 +; MIPS-NEXT: sll $17, $4, 1 +; MIPS-NEXT: srav $14, $4, $10 +; MIPS-NEXT: andi $24, $10, 32 +; MIPS-NEXT: bnez $24, $BB5_6 +; MIPS-NEXT: move $16, $14 +; MIPS-NEXT: # %bb.5: # %entry +; MIPS-NEXT: srlv $1, $5, $10 +; MIPS-NEXT: not $10, $10 +; MIPS-NEXT: sllv $10, $17, $10 +; MIPS-NEXT: or $16, $10, $1 +; MIPS-NEXT: $BB5_6: # %entry +; MIPS-NEXT: sltiu $10, $25, 64 +; MIPS-NEXT: beqz $10, $BB5_8 +; MIPS-NEXT: nop +; MIPS-NEXT: # %bb.7: +; MIPS-NEXT: or $16, $15, $3 +; MIPS-NEXT: $BB5_8: # %entry +; MIPS-NEXT: srav $15, $4, $25 +; MIPS-NEXT: beqz $8, $BB5_20 +; MIPS-NEXT: move $3, $15 +; MIPS-NEXT: # %bb.9: # %entry +; MIPS-NEXT: sltiu $gp, $25, 1 +; MIPS-NEXT: beqz $gp, $BB5_21 +; MIPS-NEXT: nop +; MIPS-NEXT: $BB5_10: # %entry +; MIPS-NEXT: beqz $10, $BB5_22 +; MIPS-NEXT: sra $25, $4, 31 +; MIPS-NEXT: $BB5_11: # %entry +; MIPS-NEXT: beqz $13, $BB5_23 +; MIPS-NEXT: nop +; MIPS-NEXT: $BB5_12: # %entry +; MIPS-NEXT: beqz $8, $BB5_24 +; MIPS-NEXT: nop +; MIPS-NEXT: $BB5_13: # %entry +; MIPS-NEXT: beqz $24, $BB5_25 +; MIPS-NEXT: move $4, $25 +; MIPS-NEXT: $BB5_14: # %entry +; MIPS-NEXT: bnez $10, $BB5_26 +; MIPS-NEXT: nop +; MIPS-NEXT: $BB5_15: # %entry +; MIPS-NEXT: beqz $gp, $BB5_27 +; MIPS-NEXT: nop +; MIPS-NEXT: $BB5_16: # %entry +; MIPS-NEXT: beqz $8, $BB5_28 +; MIPS-NEXT: move $2, $25 +; MIPS-NEXT: $BB5_17: # %entry +; MIPS-NEXT: bnez $10, $BB5_19 +; MIPS-NEXT: nop +; MIPS-NEXT: $BB5_18: # %entry +; MIPS-NEXT: move $2, $25 +; MIPS-NEXT: $BB5_19: # %entry +; MIPS-NEXT: move $4, $6 +; MIPS-NEXT: move $5, $7 +; MIPS-NEXT: lw $16, 0($sp) # 4-byte Folded Reload +; MIPS-NEXT: lw $17, 4($sp) # 4-byte Folded Reload +; MIPS-NEXT: jr $ra +; MIPS-NEXT: addiu $sp, $sp, 8 +; MIPS-NEXT: $BB5_20: # %entry +; MIPS-NEXT: srlv $1, $5, $25 +; MIPS-NEXT: sllv $3, $17, $gp +; MIPS-NEXT: sltiu $gp, $25, 1 +; MIPS-NEXT: bnez $gp, $BB5_10 +; MIPS-NEXT: or $3, $3, $1 +; MIPS-NEXT: $BB5_21: # %entry +; MIPS-NEXT: move $7, $16 +; MIPS-NEXT: bnez $10, $BB5_11 +; MIPS-NEXT: sra $25, $4, 31 +; MIPS-NEXT: $BB5_22: # %entry +; MIPS-NEXT: bnez $13, $BB5_12 +; MIPS-NEXT: move $3, $25 +; MIPS-NEXT: $BB5_23: # %entry +; MIPS-NEXT: not $1, $11 +; MIPS-NEXT: srl $5, $5, 1 +; MIPS-NEXT: sllv $4, $4, $11 +; MIPS-NEXT: srlv $1, $5, $1 +; MIPS-NEXT: bnez $8, $BB5_13 +; MIPS-NEXT: or $9, $4, $1 +; MIPS-NEXT: $BB5_24: # %entry +; MIPS-NEXT: move $2, $12 +; MIPS-NEXT: bnez $24, $BB5_14 +; MIPS-NEXT: move $4, $25 +; MIPS-NEXT: $BB5_25: # %entry +; MIPS-NEXT: beqz $10, $BB5_15 +; MIPS-NEXT: move $4, $14 +; MIPS-NEXT: $BB5_26: +; MIPS-NEXT: bnez $gp, $BB5_16 +; MIPS-NEXT: or $4, $2, $9 +; MIPS-NEXT: $BB5_27: # %entry +; MIPS-NEXT: move $6, $4 +; MIPS-NEXT: bnez $8, $BB5_17 +; MIPS-NEXT: move $2, $25 +; MIPS-NEXT: $BB5_28: # %entry +; MIPS-NEXT: bnez $10, $BB5_19 +; MIPS-NEXT: move $2, $15 +; MIPS-NEXT: # %bb.29: # %entry +; MIPS-NEXT: b $BB5_18 +; MIPS-NEXT: nop +; +; MIPS32-LABEL: ashr_i128: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: lw $9, 28($sp) +; MIPS32-NEXT: srlv $1, $7, $9 +; MIPS32-NEXT: not $2, $9 +; MIPS32-NEXT: sll $3, $6, 1 +; MIPS32-NEXT: sllv $3, $3, $2 +; MIPS32-NEXT: addiu $8, $zero, 64 +; MIPS32-NEXT: or $1, $3, $1 +; MIPS32-NEXT: srlv $10, $6, $9 +; MIPS32-NEXT: subu $3, $8, $9 +; MIPS32-NEXT: sllv $11, $5, $3 +; MIPS32-NEXT: andi $12, $3, 32 +; MIPS32-NEXT: andi $13, $9, 32 +; MIPS32-NEXT: move $8, $11 +; MIPS32-NEXT: movn $8, $zero, $12 +; MIPS32-NEXT: movn $1, $10, $13 +; MIPS32-NEXT: addiu $14, $9, -64 +; MIPS32-NEXT: srlv $15, $5, $14 +; MIPS32-NEXT: sll $24, $4, 1 +; MIPS32-NEXT: not $25, $14 +; MIPS32-NEXT: sllv $25, $24, $25 +; MIPS32-NEXT: or $gp, $1, $8 +; MIPS32-NEXT: or $1, $25, $15 +; MIPS32-NEXT: srav $8, $4, $14 +; MIPS32-NEXT: andi $14, $14, 32 +; MIPS32-NEXT: movn $1, $8, $14 +; MIPS32-NEXT: sllv $15, $4, $3 +; MIPS32-NEXT: not $3, $3 +; MIPS32-NEXT: srl $25, $5, 1 +; MIPS32-NEXT: srlv $3, $25, $3 +; MIPS32-NEXT: sltiu $25, $9, 64 +; MIPS32-NEXT: movn $1, $gp, $25 +; MIPS32-NEXT: or $15, $15, $3 +; MIPS32-NEXT: srlv $3, $5, $9 +; MIPS32-NEXT: sllv $2, $24, $2 +; MIPS32-NEXT: or $5, $2, $3 +; MIPS32-NEXT: srav $24, $4, $9 +; MIPS32-NEXT: movn $5, $24, $13 +; MIPS32-NEXT: sra $2, $4, 31 +; MIPS32-NEXT: movz $1, $7, $9 +; MIPS32-NEXT: move $3, $2 +; MIPS32-NEXT: movn $3, $5, $25 +; MIPS32-NEXT: movn $15, $11, $12 +; MIPS32-NEXT: movn $10, $zero, $13 +; MIPS32-NEXT: or $4, $10, $15 +; MIPS32-NEXT: movn $8, $2, $14 +; MIPS32-NEXT: movn $8, $4, $25 +; MIPS32-NEXT: movz $8, $6, $9 +; MIPS32-NEXT: movn $24, $2, $13 +; MIPS32-NEXT: movn $2, $24, $25 +; MIPS32-NEXT: move $4, $8 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: move $5, $1 +; +; 32R2-LABEL: ashr_i128: +; 32R2: # %bb.0: # %entry +; 32R2-NEXT: lw $9, 28($sp) +; 32R2-NEXT: srlv $1, $7, $9 +; 32R2-NEXT: not $2, $9 +; 32R2-NEXT: sll $3, $6, 1 +; 32R2-NEXT: sllv $3, $3, $2 +; 32R2-NEXT: addiu $8, $zero, 64 +; 32R2-NEXT: or $1, $3, $1 +; 32R2-NEXT: srlv $10, $6, $9 +; 32R2-NEXT: subu $3, $8, $9 +; 32R2-NEXT: sllv $11, $5, $3 +; 32R2-NEXT: andi $12, $3, 32 +; 32R2-NEXT: andi $13, $9, 32 +; 32R2-NEXT: move $8, $11 +; 32R2-NEXT: movn $8, $zero, $12 +; 32R2-NEXT: movn $1, $10, $13 +; 32R2-NEXT: addiu $14, $9, -64 +; 32R2-NEXT: srlv $15, $5, $14 +; 32R2-NEXT: sll $24, $4, 1 +; 32R2-NEXT: not $25, $14 +; 32R2-NEXT: sllv $25, $24, $25 +; 32R2-NEXT: or $gp, $1, $8 +; 32R2-NEXT: or $1, $25, $15 +; 32R2-NEXT: srav $8, $4, $14 +; 32R2-NEXT: andi $14, $14, 32 +; 32R2-NEXT: movn $1, $8, $14 +; 32R2-NEXT: sllv $15, $4, $3 +; 32R2-NEXT: not $3, $3 +; 32R2-NEXT: srl $25, $5, 1 +; 32R2-NEXT: srlv $3, $25, $3 +; 32R2-NEXT: sltiu $25, $9, 64 +; 32R2-NEXT: movn $1, $gp, $25 +; 32R2-NEXT: or $15, $15, $3 +; 32R2-NEXT: srlv $3, $5, $9 +; 32R2-NEXT: sllv $2, $24, $2 +; 32R2-NEXT: or $5, $2, $3 +; 32R2-NEXT: srav $24, $4, $9 +; 32R2-NEXT: movn $5, $24, $13 +; 32R2-NEXT: sra $2, $4, 31 +; 32R2-NEXT: movz $1, $7, $9 +; 32R2-NEXT: move $3, $2 +; 32R2-NEXT: movn $3, $5, $25 +; 32R2-NEXT: movn $15, $11, $12 +; 32R2-NEXT: movn $10, $zero, $13 +; 32R2-NEXT: or $4, $10, $15 +; 32R2-NEXT: movn $8, $2, $14 +; 32R2-NEXT: movn $8, $4, $25 +; 32R2-NEXT: movz $8, $6, $9 +; 32R2-NEXT: movn $24, $2, $13 +; 32R2-NEXT: movn $2, $24, $25 +; 32R2-NEXT: move $4, $8 +; 32R2-NEXT: jr $ra +; 32R2-NEXT: move $5, $1 +; +; 32R6-LABEL: ashr_i128: +; 32R6: # %bb.0: # %entry +; 32R6-NEXT: lw $3, 28($sp) +; 32R6-NEXT: addiu $1, $zero, 64 +; 32R6-NEXT: subu $1, $1, $3 +; 32R6-NEXT: sllv $2, $5, $1 +; 32R6-NEXT: andi $8, $1, 32 +; 32R6-NEXT: selnez $9, $2, $8 +; 32R6-NEXT: sllv $10, $4, $1 +; 32R6-NEXT: not $1, $1 +; 32R6-NEXT: srl $11, $5, 1 +; 32R6-NEXT: srlv $1, $11, $1 +; 32R6-NEXT: or $1, $10, $1 +; 32R6-NEXT: seleqz $1, $1, $8 +; 32R6-NEXT: or $1, $9, $1 +; 32R6-NEXT: srlv $9, $7, $3 +; 32R6-NEXT: not $10, $3 +; 32R6-NEXT: sll $11, $6, 1 +; 32R6-NEXT: sllv $11, $11, $10 +; 32R6-NEXT: or $9, $11, $9 +; 32R6-NEXT: andi $11, $3, 32 +; 32R6-NEXT: seleqz $9, $9, $11 +; 32R6-NEXT: srlv $12, $6, $3 +; 32R6-NEXT: selnez $13, $12, $11 +; 32R6-NEXT: seleqz $12, $12, $11 +; 32R6-NEXT: or $1, $12, $1 +; 32R6-NEXT: seleqz $2, $2, $8 +; 32R6-NEXT: or $8, $13, $9 +; 32R6-NEXT: addiu $9, $3, -64 +; 32R6-NEXT: srlv $12, $5, $9 +; 32R6-NEXT: sll $13, $4, 1 +; 32R6-NEXT: not $14, $9 +; 32R6-NEXT: sllv $14, $13, $14 +; 32R6-NEXT: sltiu $15, $3, 64 +; 32R6-NEXT: or $2, $8, $2 +; 32R6-NEXT: selnez $1, $1, $15 +; 32R6-NEXT: or $8, $14, $12 +; 32R6-NEXT: srav $12, $4, $9 +; 32R6-NEXT: andi $9, $9, 32 +; 32R6-NEXT: seleqz $14, $12, $9 +; 32R6-NEXT: sra $24, $4, 31 +; 32R6-NEXT: selnez $25, $24, $9 +; 32R6-NEXT: seleqz $8, $8, $9 +; 32R6-NEXT: or $14, $25, $14 +; 32R6-NEXT: seleqz $14, $14, $15 +; 32R6-NEXT: selnez $9, $12, $9 +; 32R6-NEXT: seleqz $12, $24, $15 +; 32R6-NEXT: or $1, $1, $14 +; 32R6-NEXT: selnez $14, $1, $3 +; 32R6-NEXT: selnez $1, $2, $15 +; 32R6-NEXT: or $2, $9, $8 +; 32R6-NEXT: srav $8, $4, $3 +; 32R6-NEXT: seleqz $4, $8, $11 +; 32R6-NEXT: selnez $9, $24, $11 +; 32R6-NEXT: or $4, $9, $4 +; 32R6-NEXT: selnez $9, $4, $15 +; 32R6-NEXT: seleqz $2, $2, $15 +; 32R6-NEXT: seleqz $4, $6, $3 +; 32R6-NEXT: seleqz $6, $7, $3 +; 32R6-NEXT: or $1, $1, $2 +; 32R6-NEXT: selnez $1, $1, $3 +; 32R6-NEXT: or $1, $6, $1 +; 32R6-NEXT: or $4, $4, $14 +; 32R6-NEXT: or $2, $9, $12 +; 32R6-NEXT: srlv $3, $5, $3 +; 32R6-NEXT: sllv $5, $13, $10 +; 32R6-NEXT: or $3, $5, $3 +; 32R6-NEXT: seleqz $3, $3, $11 +; 32R6-NEXT: selnez $5, $8, $11 +; 32R6-NEXT: or $3, $5, $3 +; 32R6-NEXT: selnez $3, $3, $15 +; 32R6-NEXT: or $3, $3, $12 +; 32R6-NEXT: jr $ra +; 32R6-NEXT: move $5, $1 +; +; MIPS3-LABEL: ashr_i128: +; MIPS3: # %bb.0: # %entry +; MIPS3-NEXT: sll $8, $7, 0 +; MIPS3-NEXT: dsrav $2, $4, $7 +; MIPS3-NEXT: andi $6, $8, 64 +; MIPS3-NEXT: beqz $6, .LBB5_3 +; MIPS3-NEXT: move $3, $2 +; MIPS3-NEXT: # %bb.1: # %entry +; MIPS3-NEXT: bnez $6, .LBB5_4 +; MIPS3-NEXT: nop +; MIPS3-NEXT: .LBB5_2: # %entry +; MIPS3-NEXT: jr $ra +; MIPS3-NEXT: nop +; MIPS3-NEXT: .LBB5_3: # %entry +; MIPS3-NEXT: dsrlv $1, $5, $7 +; MIPS3-NEXT: dsll $3, $4, 1 +; MIPS3-NEXT: not $5, $8 +; MIPS3-NEXT: dsllv $3, $3, $5 +; MIPS3-NEXT: beqz $6, .LBB5_2 +; MIPS3-NEXT: or $3, $3, $1 +; MIPS3-NEXT: .LBB5_4: +; MIPS3-NEXT: jr $ra +; MIPS3-NEXT: dsra $2, $4, 63 +; +; MIPS64-LABEL: ashr_i128: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: dsrlv $1, $5, $7 +; MIPS64-NEXT: dsll $2, $4, 1 +; MIPS64-NEXT: sll $5, $7, 0 +; MIPS64-NEXT: not $3, $5 +; MIPS64-NEXT: dsllv $2, $2, $3 +; MIPS64-NEXT: or $3, $2, $1 +; MIPS64-NEXT: dsrav $2, $4, $7 +; MIPS64-NEXT: andi $1, $5, 64 +; MIPS64-NEXT: movn $3, $2, $1 +; MIPS64-NEXT: dsra $4, $4, 63 +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: movn $2, $4, $1 +; +; MIPS64R2-LABEL: ashr_i128: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: dsrlv $1, $5, $7 +; MIPS64R2-NEXT: dsll $2, $4, 1 +; MIPS64R2-NEXT: sll $5, $7, 0 +; MIPS64R2-NEXT: not $3, $5 +; MIPS64R2-NEXT: dsllv $2, $2, $3 +; MIPS64R2-NEXT: or $3, $2, $1 +; MIPS64R2-NEXT: dsrav $2, $4, $7 +; MIPS64R2-NEXT: andi $1, $5, 64 +; MIPS64R2-NEXT: movn $3, $2, $1 +; MIPS64R2-NEXT: dsra $4, $4, 63 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: movn $2, $4, $1 +; +; MIPS64R6-LABEL: ashr_i128: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: dsrav $1, $4, $7 +; MIPS64R6-NEXT: sll $3, $7, 0 +; MIPS64R6-NEXT: andi $2, $3, 64 +; MIPS64R6-NEXT: sll $6, $2, 0 +; MIPS64R6-NEXT: seleqz $2, $1, $6 +; MIPS64R6-NEXT: dsra $8, $4, 63 +; MIPS64R6-NEXT: selnez $8, $8, $6 +; MIPS64R6-NEXT: or $2, $8, $2 +; MIPS64R6-NEXT: dsrlv $5, $5, $7 +; MIPS64R6-NEXT: dsll $4, $4, 1 +; MIPS64R6-NEXT: not $3, $3 +; MIPS64R6-NEXT: dsllv $3, $4, $3 +; MIPS64R6-NEXT: or $3, $3, $5 +; MIPS64R6-NEXT: seleqz $3, $3, $6 +; MIPS64R6-NEXT: selnez $1, $1, $6 +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: or $3, $1, $3 +; +; MMR3-LABEL: ashr_i128: +; MMR3: # %bb.0: # %entry +; MMR3-NEXT: addiusp -48 +; MMR3-NEXT: .cfi_def_cfa_offset 48 +; MMR3-NEXT: sw $17, 44($sp) # 4-byte Folded Spill +; MMR3-NEXT: sw $16, 40($sp) # 4-byte Folded Spill +; MMR3-NEXT: .cfi_offset 17, -4 +; MMR3-NEXT: .cfi_offset 16, -8 +; MMR3-NEXT: move $8, $7 +; MMR3-NEXT: sw $6, 32($sp) # 4-byte Folded Spill +; MMR3-NEXT: sw $5, 36($sp) # 4-byte Folded Spill +; MMR3-NEXT: sw $4, 8($sp) # 4-byte Folded Spill +; MMR3-NEXT: lw $16, 76($sp) +; MMR3-NEXT: srlv $4, $8, $16 +; MMR3-NEXT: not16 $3, $16 +; MMR3-NEXT: sw $3, 24($sp) # 4-byte Folded Spill +; MMR3-NEXT: sll16 $2, $6, 1 +; MMR3-NEXT: sllv $3, $2, $3 +; MMR3-NEXT: li16 $2, 64 +; MMR3-NEXT: or16 $3, $4 +; MMR3-NEXT: srlv $6, $6, $16 +; MMR3-NEXT: sw $6, 12($sp) # 4-byte Folded Spill +; MMR3-NEXT: subu16 $7, $2, $16 +; MMR3-NEXT: sllv $9, $5, $7 +; MMR3-NEXT: andi16 $2, $7, 32 +; MMR3-NEXT: sw $2, 28($sp) # 4-byte Folded Spill +; MMR3-NEXT: andi16 $5, $16, 32 +; MMR3-NEXT: sw $5, 16($sp) # 4-byte Folded Spill +; MMR3-NEXT: move $4, $9 +; MMR3-NEXT: li16 $17, 0 +; MMR3-NEXT: movn $4, $17, $2 +; MMR3-NEXT: movn $3, $6, $5 +; MMR3-NEXT: addiu $2, $16, -64 +; MMR3-NEXT: lw $5, 36($sp) # 4-byte Folded Reload +; MMR3-NEXT: srlv $5, $5, $2 +; MMR3-NEXT: sw $5, 20($sp) # 4-byte Folded Spill +; MMR3-NEXT: lw $17, 8($sp) # 4-byte Folded Reload +; MMR3-NEXT: sll16 $6, $17, 1 +; MMR3-NEXT: sw $6, 4($sp) # 4-byte Folded Spill +; MMR3-NEXT: not16 $5, $2 +; MMR3-NEXT: sllv $5, $6, $5 +; MMR3-NEXT: or16 $3, $4 +; MMR3-NEXT: lw $4, 20($sp) # 4-byte Folded Reload +; MMR3-NEXT: or16 $5, $4 +; MMR3-NEXT: srav $1, $17, $2 +; MMR3-NEXT: andi16 $2, $2, 32 +; MMR3-NEXT: sw $2, 20($sp) # 4-byte Folded Spill +; MMR3-NEXT: movn $5, $1, $2 +; MMR3-NEXT: sllv $2, $17, $7 +; MMR3-NEXT: not16 $4, $7 +; MMR3-NEXT: lw $7, 36($sp) # 4-byte Folded Reload +; MMR3-NEXT: srl16 $6, $7, 1 +; MMR3-NEXT: srlv $6, $6, $4 +; MMR3-NEXT: sltiu $10, $16, 64 +; MMR3-NEXT: movn $5, $3, $10 +; MMR3-NEXT: or16 $6, $2 +; MMR3-NEXT: srlv $2, $7, $16 +; MMR3-NEXT: lw $3, 24($sp) # 4-byte Folded Reload +; MMR3-NEXT: lw $4, 4($sp) # 4-byte Folded Reload +; MMR3-NEXT: sllv $3, $4, $3 +; MMR3-NEXT: or16 $3, $2 +; MMR3-NEXT: srav $11, $17, $16 +; MMR3-NEXT: lw $4, 16($sp) # 4-byte Folded Reload +; MMR3-NEXT: movn $3, $11, $4 +; MMR3-NEXT: sra $2, $17, 31 +; MMR3-NEXT: movz $5, $8, $16 +; MMR3-NEXT: move $8, $2 +; MMR3-NEXT: movn $8, $3, $10 +; MMR3-NEXT: lw $3, 28($sp) # 4-byte Folded Reload +; MMR3-NEXT: movn $6, $9, $3 +; MMR3-NEXT: li16 $3, 0 +; MMR3-NEXT: lw $7, 12($sp) # 4-byte Folded Reload +; MMR3-NEXT: movn $7, $3, $4 +; MMR3-NEXT: or16 $7, $6 +; MMR3-NEXT: lw $3, 20($sp) # 4-byte Folded Reload +; MMR3-NEXT: movn $1, $2, $3 +; MMR3-NEXT: movn $1, $7, $10 +; MMR3-NEXT: lw $3, 32($sp) # 4-byte Folded Reload +; MMR3-NEXT: movz $1, $3, $16 +; MMR3-NEXT: movn $11, $2, $4 +; MMR3-NEXT: movn $2, $11, $10 +; MMR3-NEXT: move $3, $8 +; MMR3-NEXT: move $4, $1 +; MMR3-NEXT: lw $16, 40($sp) # 4-byte Folded Reload +; MMR3-NEXT: lw $17, 44($sp) # 4-byte Folded Reload +; MMR3-NEXT: addiusp 48 +; MMR3-NEXT: jrc $ra +; +; MMR6-LABEL: ashr_i128: +; MMR6: # %bb.0: # %entry +; MMR6-NEXT: addiu $sp, $sp, -40 +; MMR6-NEXT: .cfi_def_cfa_offset 40 +; MMR6-NEXT: sw $17, 36($sp) # 4-byte Folded Spill +; MMR6-NEXT: sw $16, 32($sp) # 4-byte Folded Spill +; MMR6-NEXT: .cfi_offset 17, -4 +; MMR6-NEXT: .cfi_offset 16, -8 +; MMR6-NEXT: move $1, $7 +; MMR6-NEXT: sw $6, 28($sp) # 4-byte Folded Spill +; MMR6-NEXT: move $6, $5 +; MMR6-NEXT: sw $4, 12($sp) # 4-byte Folded Spill +; MMR6-NEXT: lw $3, 68($sp) +; MMR6-NEXT: li16 $2, 64 +; MMR6-NEXT: subu16 $7, $2, $3 +; MMR6-NEXT: sllv $8, $6, $7 +; MMR6-NEXT: andi16 $5, $7, 32 +; MMR6-NEXT: selnez $9, $8, $5 +; MMR6-NEXT: sllv $16, $4, $7 +; MMR6-NEXT: not16 $7, $7 +; MMR6-NEXT: srl16 $17, $6, 1 +; MMR6-NEXT: sw $6, 20($sp) # 4-byte Folded Spill +; MMR6-NEXT: srlv $7, $17, $7 +; MMR6-NEXT: or16 $7, $16 +; MMR6-NEXT: seleqz $7, $7, $5 +; MMR6-NEXT: or $7, $9, $7 +; MMR6-NEXT: srlv $17, $1, $3 +; MMR6-NEXT: not16 $2, $3 +; MMR6-NEXT: sw $2, 24($sp) # 4-byte Folded Spill +; MMR6-NEXT: lw $4, 28($sp) # 4-byte Folded Reload +; MMR6-NEXT: sll16 $16, $4, 1 +; MMR6-NEXT: sllv $16, $16, $2 +; MMR6-NEXT: or16 $16, $17 +; MMR6-NEXT: andi16 $17, $3, 32 +; MMR6-NEXT: seleqz $9, $16, $17 +; MMR6-NEXT: srlv $10, $4, $3 +; MMR6-NEXT: selnez $11, $10, $17 +; MMR6-NEXT: seleqz $16, $10, $17 +; MMR6-NEXT: or16 $16, $7 +; MMR6-NEXT: seleqz $2, $8, $5 +; MMR6-NEXT: sw $2, 8($sp) # 4-byte Folded Spill +; MMR6-NEXT: or $7, $11, $9 +; MMR6-NEXT: addiu $2, $3, -64 +; MMR6-NEXT: srlv $4, $6, $2 +; MMR6-NEXT: sw $4, 4($sp) # 4-byte Folded Spill +; MMR6-NEXT: lw $5, 12($sp) # 4-byte Folded Reload +; MMR6-NEXT: sll16 $4, $5, 1 +; MMR6-NEXT: sw $4, 16($sp) # 4-byte Folded Spill +; MMR6-NEXT: not16 $6, $2 +; MMR6-NEXT: sllv $6, $4, $6 +; MMR6-NEXT: sltiu $8, $3, 64 +; MMR6-NEXT: move $4, $7 +; MMR6-NEXT: lw $7, 8($sp) # 4-byte Folded Reload +; MMR6-NEXT: or16 $4, $7 +; MMR6-NEXT: selnez $9, $16, $8 +; MMR6-NEXT: lw $7, 4($sp) # 4-byte Folded Reload +; MMR6-NEXT: or16 $6, $7 +; MMR6-NEXT: srav $7, $5, $2 +; MMR6-NEXT: andi16 $2, $2, 32 +; MMR6-NEXT: seleqz $10, $7, $2 +; MMR6-NEXT: sra $11, $5, 31 +; MMR6-NEXT: selnez $12, $11, $2 +; MMR6-NEXT: seleqz $6, $6, $2 +; MMR6-NEXT: or $10, $12, $10 +; MMR6-NEXT: seleqz $10, $10, $8 +; MMR6-NEXT: selnez $2, $7, $2 +; MMR6-NEXT: seleqz $7, $11, $8 +; MMR6-NEXT: or $9, $9, $10 +; MMR6-NEXT: selnez $9, $9, $3 +; MMR6-NEXT: selnez $4, $4, $8 +; MMR6-NEXT: or $2, $2, $6 +; MMR6-NEXT: srav $5, $5, $3 +; MMR6-NEXT: seleqz $6, $5, $17 +; MMR6-NEXT: selnez $10, $11, $17 +; MMR6-NEXT: or $6, $10, $6 +; MMR6-NEXT: selnez $6, $6, $8 +; MMR6-NEXT: seleqz $2, $2, $8 +; MMR6-NEXT: lw $16, 28($sp) # 4-byte Folded Reload +; MMR6-NEXT: seleqz $10, $16, $3 +; MMR6-NEXT: seleqz $1, $1, $3 +; MMR6-NEXT: or $2, $4, $2 +; MMR6-NEXT: selnez $2, $2, $3 +; MMR6-NEXT: or $1, $1, $2 +; MMR6-NEXT: or $4, $10, $9 +; MMR6-NEXT: or $2, $6, $7 +; MMR6-NEXT: lw $6, 20($sp) # 4-byte Folded Reload +; MMR6-NEXT: srlv $3, $6, $3 +; MMR6-NEXT: lw $6, 24($sp) # 4-byte Folded Reload +; MMR6-NEXT: lw $16, 16($sp) # 4-byte Folded Reload +; MMR6-NEXT: sllv $6, $16, $6 +; MMR6-NEXT: or16 $6, $3 +; MMR6-NEXT: seleqz $3, $6, $17 +; MMR6-NEXT: selnez $5, $5, $17 +; MMR6-NEXT: or $3, $5, $3 +; MMR6-NEXT: selnez $3, $3, $8 +; MMR6-NEXT: or $3, $3, $7 +; MMR6-NEXT: move $5, $1 +; MMR6-NEXT: lw $16, 32($sp) # 4-byte Folded Reload +; MMR6-NEXT: lw $17, 36($sp) # 4-byte Folded Reload +; MMR6-NEXT: addiu $sp, $sp, 40 +; MMR6-NEXT: jrc $ra entry: -; ALL-LABEL: ashr_i128: - - ; o32 shouldn't use TImode helpers. - ; GP32-NOT: lw $25, %call16(__ashrti3)($gp) - ; MM-NOT: lw $25, %call16(__ashrti3)($2) - - ; M3: sll $[[T0:[0-9]+]], $7, 0 - ; M3: dsrav $[[T1:[0-9]+]], $4, $7 - ; M3: andi $[[T2:[0-9]+]], $[[T0]], 64 - ; M3: beqz $[[T3:[0-9]+]], [[BB0:.LBB[0-9_]+]] - ; M3: move $3, $[[T1]] - ; M3: bnez $[[T3]], [[BB1:.LBB[0-9_]+]] - ; M3: nop - ; M3: [[EXIT:.LBB[0-9_]+]]: - ; M3: jr $ra - ; M3: nop - ; M3: [[BB0]]: - ; M3: dsrlv $[[T4:[0-9]+]], $5, $7 - ; M3: dsll $[[T5:[0-9]+]], $4, 1 - ; M3: not $[[T6:[0-9]+]], $[[T0]] - ; M3: dsllv $[[T7:[0-9]+]], $[[T5]], $[[T6]] - ; M3: beqz $[[T3]], [[EXIT]] - ; M3: or $3, $[[T7]], $[[T4]] - ; M3: [[BB1]]: - ; M3: jr $ra - ; M3: dsra $2, $4, 63 - - ; GP64-NOT-R6: dsrlv $[[T0:[0-9]+]], $5, $7 - ; GP64-NOT-R6: dsll $[[T1:[0-9]+]], $4, 1 - ; GP64-NOT-R6: sll $[[T2:[0-9]+]], $7, 0 - ; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T2]] - ; GP64-NOT-R6: dsllv $[[T4:[0-9]+]], $[[T1]], $[[T3]] - ; GP64-NOT-R6: or $3, $[[T4]], $[[T0]] - ; GP64-NOT-R6: dsrav $2, $4, $7 - ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T2]], 64 - ; GP64-NOT-R6: movn $3, $2, $[[T5]] - ; GP64-NOT-R6: dsra $[[T6:[0-9]+]], $4, 63 - ; GP64-NOT-R6: jr $ra - ; GP64-NOT-R6: movn $2, $[[T6]], $[[T5]] - - ; 64R6: dsrav $[[T0:[0-9]+]], $4, $7 - ; 64R6: sll $[[T1:[0-9]+]], $7, 0 - ; 64R6: andi $[[T2:[0-9]+]], $[[T1]], 64 - ; 64R6: sll $[[T3:[0-9]+]], $[[T2]], 0 - ; 64R6: seleqz $[[T4:[0-9]+]], $[[T0]], $[[T3]] - ; 64R6: dsra $[[T5:[0-9]+]], $4, 63 - ; 64R6: selnez $[[T6:[0-9]+]], $[[T5]], $[[T3]] - ; 64R6: or $2, $[[T6]], $[[T4]] - ; 64R6: dsrlv $[[T7:[0-9]+]], $5, $7 - ; 64R6: dsll $[[T8:[0-9]+]], $4, 1 - ; 64R6: not $[[T9:[0-9]+]], $[[T1]] - ; 64R6: dsllv $[[T10:[0-9]+]], $[[T8]], $[[T9]] - ; 64R6: or $[[T11:[0-9]+]], $[[T10]], $[[T7]] - ; 64R6: seleqz $[[T12:[0-9]+]], $[[T11]], $[[T3]] - ; 64R6: selnez $[[T13:[0-9]+]], $[[T0]], $[[T3]] - ; 64R6: jr $ra - ; 64R6: or $3, $[[T13]], $[[T12]] +; o32 shouldn't use TImode helpers. +; GP32-NOT: lw $25, %call16(__ashrti3)($gp) +; MM-NOT: lw $25, %call16(__ashrti3)($2) %r = ashr i128 %a, %b ret i128 %r diff --git a/test/CodeGen/Mips/llvm-ir/lshr.ll b/test/CodeGen/Mips/llvm-ir/lshr.ll index 926f3e4c8d7..057a7fb237e 100644 --- a/test/CodeGen/Mips/llvm-ir/lshr.ll +++ b/test/CodeGen/Mips/llvm-ir/lshr.ll @@ -1,214 +1,1017 @@ -; RUN: llc < %s -march=mips -mcpu=mips2 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32,M2 -; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32,32R1-R5 -; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32,32R1-R5 -; RUN: llc < %s -march=mips -mcpu=mips32r3 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32,32R1-R5 -; RUN: llc < %s -march=mips -mcpu=mips32r5 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32,32R1-R5 -; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32,32R6 -; RUN: llc < %s -march=mips64 -mcpu=mips3 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64,M3 -; RUN: llc < %s -march=mips64 -mcpu=mips4 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64,64R6 -; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,MM,MMR3 -; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,MM,MMR6 +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS2 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS32 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS32R2 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS32R2 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r5 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS32R2 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS32R6 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS3 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips4 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS4 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS64 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS64R2 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS64R2 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r5 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS64R2 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS64R6 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MMR3 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MMR6 define signext i1 @lshr_i1(i1 signext %a, i1 signext %b) { +; MIPS2-LABEL: lshr_i1: +; MIPS2: # %bb.0: # %entry +; MIPS2-NEXT: jr $ra +; MIPS2-NEXT: move $2, $4 +; +; MIPS32-LABEL: lshr_i1: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: move $2, $4 +; +; MIPS32R2-LABEL: lshr_i1: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: move $2, $4 +; +; MIPS32R6-LABEL: lshr_i1: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: move $2, $4 +; +; MIPS3-LABEL: lshr_i1: +; MIPS3: # %bb.0: # %entry +; MIPS3-NEXT: jr $ra +; MIPS3-NEXT: move $2, $4 +; +; MIPS4-LABEL: lshr_i1: +; MIPS4: # %bb.0: # %entry +; MIPS4-NEXT: jr $ra +; MIPS4-NEXT: move $2, $4 +; +; MIPS64-LABEL: lshr_i1: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: move $2, $4 +; +; MIPS64R2-LABEL: lshr_i1: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: move $2, $4 +; +; MIPS64R6-LABEL: lshr_i1: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: move $2, $4 +; +; MMR3-LABEL: lshr_i1: +; MMR3: # %bb.0: # %entry +; MMR3-NEXT: move $2, $4 +; MMR3-NEXT: jrc $ra +; +; MMR6-LABEL: lshr_i1: +; MMR6: # %bb.0: # %entry +; MMR6-NEXT: move $2, $4 +; MMR6-NEXT: jrc $ra entry: -; ALL-LABEL: lshr_i1: - - ; ALL: move $2, $4 %r = lshr i1 %a, %b ret i1 %r } define zeroext i8 @lshr_i8(i8 zeroext %a, i8 zeroext %b) { +; MIPS2-LABEL: lshr_i8: +; MIPS2: # %bb.0: # %entry +; MIPS2-NEXT: srlv $1, $4, $5 +; MIPS2-NEXT: jr $ra +; MIPS2-NEXT: andi $2, $1, 255 +; +; MIPS32-LABEL: lshr_i8: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: srlv $1, $4, $5 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: andi $2, $1, 255 +; +; MIPS32R2-LABEL: lshr_i8: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: srlv $1, $4, $5 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: andi $2, $1, 255 +; +; MIPS32R6-LABEL: lshr_i8: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: srlv $1, $4, $5 +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: andi $2, $1, 255 +; +; MIPS3-LABEL: lshr_i8: +; MIPS3: # %bb.0: # %entry +; MIPS3-NEXT: srlv $1, $4, $5 +; MIPS3-NEXT: jr $ra +; MIPS3-NEXT: andi $2, $1, 255 +; +; MIPS4-LABEL: lshr_i8: +; MIPS4: # %bb.0: # %entry +; MIPS4-NEXT: srlv $1, $4, $5 +; MIPS4-NEXT: jr $ra +; MIPS4-NEXT: andi $2, $1, 255 +; +; MIPS64-LABEL: lshr_i8: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: srlv $1, $4, $5 +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: andi $2, $1, 255 +; +; MIPS64R2-LABEL: lshr_i8: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: srlv $1, $4, $5 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: andi $2, $1, 255 +; +; MIPS64R6-LABEL: lshr_i8: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: srlv $1, $4, $5 +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: andi $2, $1, 255 +; +; MMR3-LABEL: lshr_i8: +; MMR3: # %bb.0: # %entry +; MMR3-NEXT: srlv $2, $4, $5 +; MMR3-NEXT: andi16 $2, $2, 255 +; MMR3-NEXT: jrc $ra +; +; MMR6-LABEL: lshr_i8: +; MMR6: # %bb.0: # %entry +; MMR6-NEXT: srlv $2, $4, $5 +; MMR6-NEXT: andi16 $2, $2, 255 +; MMR6-NEXT: jrc $ra entry: -; ALL-LABEL: lshr_i8: - - ; ALL: srlv $[[T0:[0-9]+]], $4, $5 - ; GP32: andi $2, $[[T0]], 255 - ; GP64: andi $2, $[[T0]], 255 - ; MM: andi16 $2, $[[T0]], 255 %r = lshr i8 %a, %b ret i8 %r } define zeroext i16 @lshr_i16(i16 zeroext %a, i16 zeroext %b) { +; MIPS2-LABEL: lshr_i16: +; MIPS2: # %bb.0: # %entry +; MIPS2-NEXT: srlv $1, $4, $5 +; MIPS2-NEXT: jr $ra +; MIPS2-NEXT: andi $2, $1, 65535 +; +; MIPS32-LABEL: lshr_i16: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: srlv $1, $4, $5 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: andi $2, $1, 65535 +; +; MIPS32R2-LABEL: lshr_i16: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: srlv $1, $4, $5 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: andi $2, $1, 65535 +; +; MIPS32R6-LABEL: lshr_i16: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: srlv $1, $4, $5 +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: andi $2, $1, 65535 +; +; MIPS3-LABEL: lshr_i16: +; MIPS3: # %bb.0: # %entry +; MIPS3-NEXT: srlv $1, $4, $5 +; MIPS3-NEXT: jr $ra +; MIPS3-NEXT: andi $2, $1, 65535 +; +; MIPS4-LABEL: lshr_i16: +; MIPS4: # %bb.0: # %entry +; MIPS4-NEXT: srlv $1, $4, $5 +; MIPS4-NEXT: jr $ra +; MIPS4-NEXT: andi $2, $1, 65535 +; +; MIPS64-LABEL: lshr_i16: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: srlv $1, $4, $5 +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: andi $2, $1, 65535 +; +; MIPS64R2-LABEL: lshr_i16: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: srlv $1, $4, $5 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: andi $2, $1, 65535 +; +; MIPS64R6-LABEL: lshr_i16: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: srlv $1, $4, $5 +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: andi $2, $1, 65535 +; +; MMR3-LABEL: lshr_i16: +; MMR3: # %bb.0: # %entry +; MMR3-NEXT: srlv $2, $4, $5 +; MMR3-NEXT: andi16 $2, $2, 65535 +; MMR3-NEXT: jrc $ra +; +; MMR6-LABEL: lshr_i16: +; MMR6: # %bb.0: # %entry +; MMR6-NEXT: srlv $2, $4, $5 +; MMR6-NEXT: andi16 $2, $2, 65535 +; MMR6-NEXT: jrc $ra entry: -; ALL-LABEL: lshr_i16: - - ; ALL: srlv $[[T0:[0-9]+]], $4, $5 - ; GP32: andi $2, $[[T0]], 65535 - ; GP64: andi $2, $[[T0]], 65535 - ; MM: andi16 $2, $[[T0]], 65535 %r = lshr i16 %a, %b ret i16 %r } define signext i32 @lshr_i32(i32 signext %a, i32 signext %b) { +; MIPS2-LABEL: lshr_i32: +; MIPS2: # %bb.0: # %entry +; MIPS2-NEXT: jr $ra +; MIPS2-NEXT: srlv $2, $4, $5 +; +; MIPS32-LABEL: lshr_i32: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: srlv $2, $4, $5 +; +; MIPS32R2-LABEL: lshr_i32: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: srlv $2, $4, $5 +; +; MIPS32R6-LABEL: lshr_i32: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: srlv $2, $4, $5 +; +; MIPS3-LABEL: lshr_i32: +; MIPS3: # %bb.0: # %entry +; MIPS3-NEXT: jr $ra +; MIPS3-NEXT: srlv $2, $4, $5 +; +; MIPS4-LABEL: lshr_i32: +; MIPS4: # %bb.0: # %entry +; MIPS4-NEXT: jr $ra +; MIPS4-NEXT: srlv $2, $4, $5 +; +; MIPS64-LABEL: lshr_i32: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: srlv $2, $4, $5 +; +; MIPS64R2-LABEL: lshr_i32: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: srlv $2, $4, $5 +; +; MIPS64R6-LABEL: lshr_i32: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: srlv $2, $4, $5 +; +; MMR3-LABEL: lshr_i32: +; MMR3: # %bb.0: # %entry +; MMR3-NEXT: jr $ra +; MMR3-NEXT: srlv $2, $4, $5 +; +; MMR6-LABEL: lshr_i32: +; MMR6: # %bb.0: # %entry +; MMR6-NEXT: srlv $2, $4, $5 +; MMR6-NEXT: jrc $ra entry: -; ALL-LABEL: lshr_i32: - - ; ALL: srlv $2, $4, $5 %r = lshr i32 %a, %b ret i32 %r } define signext i64 @lshr_i64(i64 signext %a, i64 signext %b) { +; MIPS2-LABEL: lshr_i64: +; MIPS2: # %bb.0: # %entry +; MIPS2-NEXT: srlv $6, $4, $7 +; MIPS2-NEXT: andi $8, $7, 32 +; MIPS2-NEXT: beqz $8, $BB4_3 +; MIPS2-NEXT: move $3, $6 +; MIPS2-NEXT: # %bb.1: # %entry +; MIPS2-NEXT: beqz $8, $BB4_4 +; MIPS2-NEXT: addiu $2, $zero, 0 +; MIPS2-NEXT: $BB4_2: # %entry +; MIPS2-NEXT: jr $ra +; MIPS2-NEXT: nop +; MIPS2-NEXT: $BB4_3: # %entry +; MIPS2-NEXT: srlv $1, $5, $7 +; MIPS2-NEXT: not $2, $7 +; MIPS2-NEXT: sll $3, $4, 1 +; MIPS2-NEXT: sllv $2, $3, $2 +; MIPS2-NEXT: or $3, $2, $1 +; MIPS2-NEXT: bnez $8, $BB4_2 +; MIPS2-NEXT: addiu $2, $zero, 0 +; MIPS2-NEXT: $BB4_4: # %entry +; MIPS2-NEXT: jr $ra +; MIPS2-NEXT: move $2, $6 +; +; MIPS32-LABEL: lshr_i64: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: srlv $1, $5, $7 +; MIPS32-NEXT: not $2, $7 +; MIPS32-NEXT: sll $3, $4, 1 +; MIPS32-NEXT: sllv $2, $3, $2 +; MIPS32-NEXT: or $3, $2, $1 +; MIPS32-NEXT: srlv $2, $4, $7 +; MIPS32-NEXT: andi $1, $7, 32 +; MIPS32-NEXT: movn $3, $2, $1 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: movn $2, $zero, $1 +; +; MIPS32R2-LABEL: lshr_i64: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: srlv $1, $5, $7 +; MIPS32R2-NEXT: not $2, $7 +; MIPS32R2-NEXT: sll $3, $4, 1 +; MIPS32R2-NEXT: sllv $2, $3, $2 +; MIPS32R2-NEXT: or $3, $2, $1 +; MIPS32R2-NEXT: srlv $2, $4, $7 +; MIPS32R2-NEXT: andi $1, $7, 32 +; MIPS32R2-NEXT: movn $3, $2, $1 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: movn $2, $zero, $1 +; +; MIPS32R6-LABEL: lshr_i64: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: srlv $1, $5, $7 +; MIPS32R6-NEXT: not $2, $7 +; MIPS32R6-NEXT: sll $3, $4, 1 +; MIPS32R6-NEXT: sllv $2, $3, $2 +; MIPS32R6-NEXT: or $1, $2, $1 +; MIPS32R6-NEXT: andi $2, $7, 32 +; MIPS32R6-NEXT: seleqz $1, $1, $2 +; MIPS32R6-NEXT: srlv $4, $4, $7 +; MIPS32R6-NEXT: selnez $3, $4, $2 +; MIPS32R6-NEXT: or $3, $3, $1 +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: seleqz $2, $4, $2 +; +; MIPS3-LABEL: lshr_i64: +; MIPS3: # %bb.0: # %entry +; MIPS3-NEXT: jr $ra +; MIPS3-NEXT: dsrlv $2, $4, $5 +; +; MIPS4-LABEL: lshr_i64: +; MIPS4: # %bb.0: # %entry +; MIPS4-NEXT: jr $ra +; MIPS4-NEXT: dsrlv $2, $4, $5 +; +; MIPS64-LABEL: lshr_i64: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: dsrlv $2, $4, $5 +; +; MIPS64R2-LABEL: lshr_i64: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: dsrlv $2, $4, $5 +; +; MIPS64R6-LABEL: lshr_i64: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: dsrlv $2, $4, $5 +; +; MMR3-LABEL: lshr_i64: +; MMR3: # %bb.0: # %entry +; MMR3-NEXT: srlv $2, $5, $7 +; MMR3-NEXT: not16 $3, $7 +; MMR3-NEXT: sll16 $5, $4, 1 +; MMR3-NEXT: sllv $3, $5, $3 +; MMR3-NEXT: or16 $3, $2 +; MMR3-NEXT: srlv $2, $4, $7 +; MMR3-NEXT: andi16 $4, $7, 32 +; MMR3-NEXT: movn $3, $2, $4 +; MMR3-NEXT: li16 $5, 0 +; MMR3-NEXT: jr $ra +; MMR3-NEXT: movn $2, $5, $4 +; +; MMR6-LABEL: lshr_i64: +; MMR6: # %bb.0: # %entry +; MMR6-NEXT: srlv $2, $5, $7 +; MMR6-NEXT: not16 $3, $7 +; MMR6-NEXT: sll16 $5, $4, 1 +; MMR6-NEXT: sllv $3, $5, $3 +; MMR6-NEXT: or16 $3, $2 +; MMR6-NEXT: andi16 $2, $7, 32 +; MMR6-NEXT: seleqz $1, $3, $2 +; MMR6-NEXT: srlv $4, $4, $7 +; MMR6-NEXT: selnez $3, $4, $2 +; MMR6-NEXT: or $3, $3, $1 +; MMR6-NEXT: seleqz $2, $4, $2 +; MMR6-NEXT: jrc $ra entry: -; ALL-LABEL: lshr_i64: - - ; M2: srlv $[[T0:[0-9]+]], $4, $7 - ; M2: andi $[[T1:[0-9]+]], $7, 32 - ; M2: beqz $[[T1]], $[[BB0:BB[0-9_]+]] - ; M2: move $3, $[[T0]] - ; M2: beqz $[[T1]], $[[BB1:BB[0-9_]+]] - ; M2: addiu $2, $zero, 0 - ; M2: $[[EXIT:BB[0-9_]+]]: - ; M2: jr $ra - ; M2: nop - ; M2: $[[BB0]]: - ; M2: srlv $[[T2:[0-9]+]], $5, $7 - ; M2: not $[[T3:[0-9]+]], $7 - ; M2: sll $[[T4:[0-9]+]], $4, 1 - ; M2: sllv $[[T5:[0-9]+]], $[[T4]], $[[T3]] - ; M2: or $3, $[[T3]], $[[T2]] - ; M2: bnez $[[T1]], $[[EXIT:BB[0-9_]+]] - ; M2: addiu $2, $zero, 0 - ; M2: $[[BB1]]: - ; M2: jr $ra - ; M2: move $2, $[[T0]] - - ; 32R1-R5: srlv $[[T0:[0-9]+]], $5, $7 - ; 32R1-R5: not $[[T1:[0-9]+]], $7 - ; 32R1-R5: sll $[[T2:[0-9]+]], $4, 1 - ; 32R1-R5: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]] - ; 32R1-R5: or $3, $[[T3]], $[[T0]] - ; 32R1-R5: srlv $[[T4:[0-9]+]], $4, $7 - ; 32R1-R5: andi $[[T5:[0-9]+]], $7, 32 - ; 32R1-R5: movn $3, $[[T4]], $[[T5]] - ; 32R1-R5: jr $ra - ; 32R1-R5: movn $2, $zero, $[[T5]] - - ; 32R6: srlv $[[T0:[0-9]+]], $5, $7 - ; 32R6: not $[[T1:[0-9]+]], $7 - ; 32R6: sll $[[T2:[0-9]+]], $4, 1 - ; 32R6: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]] - ; 32R6: or $[[T4:[0-9]+]], $[[T3]], $[[T0]] - ; 32R6: andi $[[T5:[0-9]+]], $7, 32 - ; 32R6: seleqz $[[T6:[0-9]+]], $[[T4]], $[[T3]] - ; 32R6: srlv $[[T7:[0-9]+]], $4, $7 - ; 32R6: selnez $[[T8:[0-9]+]], $[[T7]], $[[T5]] - ; 32R6: or $3, $[[T8]], $[[T6]] - ; 32R6: jr $ra - ; 32R6: seleqz $2, $[[T7]], $[[T5]] - - ; GP64: dsrlv $2, $4, $5 - - ; MMR3: srlv $[[T0:[0-9]+]], $5, $7 - ; MMR3: not16 $[[T1:[0-9]+]], $7 - ; MMR3: sll16 $[[T2:[0-9]+]], $4, 1 - ; MMR3: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]] - ; MMR3: or16 $[[T4:[0-9]+]], $[[T0]] - ; MMR3: srlv $[[T5:[0-9]+]], $4, $7 - ; MMR3: andi16 $[[T6:[0-9]+]], $7, 32 - ; MMR3: movn $[[T7:[0-9]+]], $[[T5]], $[[T6]] - ; MMR3: li16 $[[T8:[0-9]+]], 0 - ; MMR3: movn $2, $[[T8]], $[[T6]] - - ; MMR6: srlv $[[T0:[0-9]+]], $5, $7 - ; MMR6: not16 $[[T1:[0-9]+]], $7 - ; MMR6: sll16 $[[T2:[0-9]+]], $4, 1 - ; MMR6: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]] - ; MMR6: or16 $[[T4:[0-9]+]], $[[T0]] - ; MMR6: andi16 $[[T5:[0-9]+]], $7, 32 - ; MMR6: seleqz $[[T6:[0-9]+]], $[[T4]], $[[T5]] - ; MMR6: srlv $[[T7:[0-9]+]], $4, $7 - ; MMR6: selnez $[[T8:[0-9]+]], $[[T7]], $[[T5]] - ; MMR6: or $3, $[[T8]], $[[T6]] - ; MMR6: seleqz $2, $[[T7]], $[[T5]] %r = lshr i64 %a, %b ret i64 %r } define signext i128 @lshr_i128(i128 signext %a, i128 signext %b) { +; MIPS2-LABEL: lshr_i128: +; MIPS2: # %bb.0: # %entry +; MIPS2-NEXT: addiu $sp, $sp, -8 +; MIPS2-NEXT: .cfi_def_cfa_offset 8 +; MIPS2-NEXT: sw $17, 4($sp) # 4-byte Folded Spill +; MIPS2-NEXT: sw $16, 0($sp) # 4-byte Folded Spill +; MIPS2-NEXT: .cfi_offset 17, -4 +; MIPS2-NEXT: .cfi_offset 16, -8 +; MIPS2-NEXT: lw $2, 36($sp) +; MIPS2-NEXT: addiu $1, $zero, 64 +; MIPS2-NEXT: subu $10, $1, $2 +; MIPS2-NEXT: sllv $9, $5, $10 +; MIPS2-NEXT: andi $13, $10, 32 +; MIPS2-NEXT: addiu $8, $zero, 0 +; MIPS2-NEXT: bnez $13, $BB5_2 +; MIPS2-NEXT: addiu $25, $zero, 0 +; MIPS2-NEXT: # %bb.1: # %entry +; MIPS2-NEXT: move $25, $9 +; MIPS2-NEXT: $BB5_2: # %entry +; MIPS2-NEXT: not $3, $2 +; MIPS2-NEXT: srlv $11, $6, $2 +; MIPS2-NEXT: andi $12, $2, 32 +; MIPS2-NEXT: bnez $12, $BB5_4 +; MIPS2-NEXT: move $16, $11 +; MIPS2-NEXT: # %bb.3: # %entry +; MIPS2-NEXT: srlv $1, $7, $2 +; MIPS2-NEXT: sll $14, $6, 1 +; MIPS2-NEXT: sllv $14, $14, $3 +; MIPS2-NEXT: or $16, $14, $1 +; MIPS2-NEXT: $BB5_4: # %entry +; MIPS2-NEXT: addiu $24, $2, -64 +; MIPS2-NEXT: sll $17, $4, 1 +; MIPS2-NEXT: srlv $14, $4, $24 +; MIPS2-NEXT: andi $15, $24, 32 +; MIPS2-NEXT: bnez $15, $BB5_6 +; MIPS2-NEXT: move $gp, $14 +; MIPS2-NEXT: # %bb.5: # %entry +; MIPS2-NEXT: srlv $1, $5, $24 +; MIPS2-NEXT: not $24, $24 +; MIPS2-NEXT: sllv $24, $17, $24 +; MIPS2-NEXT: or $gp, $24, $1 +; MIPS2-NEXT: $BB5_6: # %entry +; MIPS2-NEXT: sltiu $24, $2, 64 +; MIPS2-NEXT: beqz $24, $BB5_8 +; MIPS2-NEXT: nop +; MIPS2-NEXT: # %bb.7: +; MIPS2-NEXT: or $gp, $16, $25 +; MIPS2-NEXT: $BB5_8: # %entry +; MIPS2-NEXT: srlv $25, $4, $2 +; MIPS2-NEXT: bnez $12, $BB5_10 +; MIPS2-NEXT: move $16, $25 +; MIPS2-NEXT: # %bb.9: # %entry +; MIPS2-NEXT: srlv $1, $5, $2 +; MIPS2-NEXT: sllv $3, $17, $3 +; MIPS2-NEXT: or $16, $3, $1 +; MIPS2-NEXT: $BB5_10: # %entry +; MIPS2-NEXT: bnez $12, $BB5_12 +; MIPS2-NEXT: addiu $3, $zero, 0 +; MIPS2-NEXT: # %bb.11: # %entry +; MIPS2-NEXT: move $3, $25 +; MIPS2-NEXT: $BB5_12: # %entry +; MIPS2-NEXT: addiu $1, $zero, 63 +; MIPS2-NEXT: sltiu $25, $2, 1 +; MIPS2-NEXT: beqz $25, $BB5_22 +; MIPS2-NEXT: sltu $17, $1, $2 +; MIPS2-NEXT: # %bb.13: # %entry +; MIPS2-NEXT: beqz $17, $BB5_23 +; MIPS2-NEXT: addiu $2, $zero, 0 +; MIPS2-NEXT: $BB5_14: # %entry +; MIPS2-NEXT: beqz $17, $BB5_24 +; MIPS2-NEXT: addiu $3, $zero, 0 +; MIPS2-NEXT: $BB5_15: # %entry +; MIPS2-NEXT: beqz $13, $BB5_25 +; MIPS2-NEXT: nop +; MIPS2-NEXT: $BB5_16: # %entry +; MIPS2-NEXT: beqz $12, $BB5_26 +; MIPS2-NEXT: addiu $4, $zero, 0 +; MIPS2-NEXT: $BB5_17: # %entry +; MIPS2-NEXT: beqz $15, $BB5_27 +; MIPS2-NEXT: nop +; MIPS2-NEXT: $BB5_18: # %entry +; MIPS2-NEXT: bnez $24, $BB5_28 +; MIPS2-NEXT: nop +; MIPS2-NEXT: $BB5_19: # %entry +; MIPS2-NEXT: bnez $25, $BB5_21 +; MIPS2-NEXT: nop +; MIPS2-NEXT: $BB5_20: # %entry +; MIPS2-NEXT: move $6, $8 +; MIPS2-NEXT: $BB5_21: # %entry +; MIPS2-NEXT: move $4, $6 +; MIPS2-NEXT: move $5, $7 +; MIPS2-NEXT: lw $16, 0($sp) # 4-byte Folded Reload +; MIPS2-NEXT: lw $17, 4($sp) # 4-byte Folded Reload +; MIPS2-NEXT: jr $ra +; MIPS2-NEXT: addiu $sp, $sp, 8 +; MIPS2-NEXT: $BB5_22: # %entry +; MIPS2-NEXT: move $7, $gp +; MIPS2-NEXT: bnez $17, $BB5_14 +; MIPS2-NEXT: addiu $2, $zero, 0 +; MIPS2-NEXT: $BB5_23: # %entry +; MIPS2-NEXT: move $2, $3 +; MIPS2-NEXT: bnez $17, $BB5_15 +; MIPS2-NEXT: addiu $3, $zero, 0 +; MIPS2-NEXT: $BB5_24: # %entry +; MIPS2-NEXT: bnez $13, $BB5_16 +; MIPS2-NEXT: move $3, $16 +; MIPS2-NEXT: $BB5_25: # %entry +; MIPS2-NEXT: not $1, $10 +; MIPS2-NEXT: srl $5, $5, 1 +; MIPS2-NEXT: sllv $4, $4, $10 +; MIPS2-NEXT: srlv $1, $5, $1 +; MIPS2-NEXT: or $9, $4, $1 +; MIPS2-NEXT: bnez $12, $BB5_17 +; MIPS2-NEXT: addiu $4, $zero, 0 +; MIPS2-NEXT: $BB5_26: # %entry +; MIPS2-NEXT: bnez $15, $BB5_18 +; MIPS2-NEXT: move $4, $11 +; MIPS2-NEXT: $BB5_27: # %entry +; MIPS2-NEXT: beqz $24, $BB5_19 +; MIPS2-NEXT: move $8, $14 +; MIPS2-NEXT: $BB5_28: +; MIPS2-NEXT: bnez $25, $BB5_21 +; MIPS2-NEXT: or $8, $4, $9 +; MIPS2-NEXT: # %bb.29: +; MIPS2-NEXT: b $BB5_20 +; MIPS2-NEXT: nop +; +; MIPS32-LABEL: lshr_i128: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: lw $9, 28($sp) +; MIPS32-NEXT: addiu $1, $zero, 64 +; MIPS32-NEXT: subu $2, $1, $9 +; MIPS32-NEXT: sllv $10, $5, $2 +; MIPS32-NEXT: andi $11, $2, 32 +; MIPS32-NEXT: move $1, $10 +; MIPS32-NEXT: movn $1, $zero, $11 +; MIPS32-NEXT: srlv $3, $7, $9 +; MIPS32-NEXT: not $12, $9 +; MIPS32-NEXT: sll $8, $6, 1 +; MIPS32-NEXT: sllv $8, $8, $12 +; MIPS32-NEXT: or $3, $8, $3 +; MIPS32-NEXT: srlv $13, $6, $9 +; MIPS32-NEXT: andi $14, $9, 32 +; MIPS32-NEXT: movn $3, $13, $14 +; MIPS32-NEXT: addiu $15, $9, -64 +; MIPS32-NEXT: or $3, $3, $1 +; MIPS32-NEXT: srlv $1, $5, $15 +; MIPS32-NEXT: sll $24, $4, 1 +; MIPS32-NEXT: not $8, $15 +; MIPS32-NEXT: sllv $8, $24, $8 +; MIPS32-NEXT: or $1, $8, $1 +; MIPS32-NEXT: srlv $8, $4, $15 +; MIPS32-NEXT: andi $15, $15, 32 +; MIPS32-NEXT: movn $1, $8, $15 +; MIPS32-NEXT: sltiu $25, $9, 64 +; MIPS32-NEXT: movn $1, $3, $25 +; MIPS32-NEXT: sllv $3, $4, $2 +; MIPS32-NEXT: not $2, $2 +; MIPS32-NEXT: srl $gp, $5, 1 +; MIPS32-NEXT: srlv $2, $gp, $2 +; MIPS32-NEXT: or $gp, $3, $2 +; MIPS32-NEXT: srlv $2, $5, $9 +; MIPS32-NEXT: sllv $3, $24, $12 +; MIPS32-NEXT: or $3, $3, $2 +; MIPS32-NEXT: srlv $2, $4, $9 +; MIPS32-NEXT: movn $3, $2, $14 +; MIPS32-NEXT: movz $1, $7, $9 +; MIPS32-NEXT: movz $3, $zero, $25 +; MIPS32-NEXT: movn $gp, $10, $11 +; MIPS32-NEXT: movn $13, $zero, $14 +; MIPS32-NEXT: or $4, $13, $gp +; MIPS32-NEXT: movn $8, $zero, $15 +; MIPS32-NEXT: movn $8, $4, $25 +; MIPS32-NEXT: movz $8, $6, $9 +; MIPS32-NEXT: movn $2, $zero, $14 +; MIPS32-NEXT: movz $2, $zero, $25 +; MIPS32-NEXT: move $4, $8 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: move $5, $1 +; +; MIPS32R2-LABEL: lshr_i128: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: lw $9, 28($sp) +; MIPS32R2-NEXT: addiu $1, $zero, 64 +; MIPS32R2-NEXT: subu $2, $1, $9 +; MIPS32R2-NEXT: sllv $10, $5, $2 +; MIPS32R2-NEXT: andi $11, $2, 32 +; MIPS32R2-NEXT: move $1, $10 +; MIPS32R2-NEXT: movn $1, $zero, $11 +; MIPS32R2-NEXT: srlv $3, $7, $9 +; MIPS32R2-NEXT: not $12, $9 +; MIPS32R2-NEXT: sll $8, $6, 1 +; MIPS32R2-NEXT: sllv $8, $8, $12 +; MIPS32R2-NEXT: or $3, $8, $3 +; MIPS32R2-NEXT: srlv $13, $6, $9 +; MIPS32R2-NEXT: andi $14, $9, 32 +; MIPS32R2-NEXT: movn $3, $13, $14 +; MIPS32R2-NEXT: addiu $15, $9, -64 +; MIPS32R2-NEXT: or $3, $3, $1 +; MIPS32R2-NEXT: srlv $1, $5, $15 +; MIPS32R2-NEXT: sll $24, $4, 1 +; MIPS32R2-NEXT: not $8, $15 +; MIPS32R2-NEXT: sllv $8, $24, $8 +; MIPS32R2-NEXT: or $1, $8, $1 +; MIPS32R2-NEXT: srlv $8, $4, $15 +; MIPS32R2-NEXT: andi $15, $15, 32 +; MIPS32R2-NEXT: movn $1, $8, $15 +; MIPS32R2-NEXT: sltiu $25, $9, 64 +; MIPS32R2-NEXT: movn $1, $3, $25 +; MIPS32R2-NEXT: sllv $3, $4, $2 +; MIPS32R2-NEXT: not $2, $2 +; MIPS32R2-NEXT: srl $gp, $5, 1 +; MIPS32R2-NEXT: srlv $2, $gp, $2 +; MIPS32R2-NEXT: or $gp, $3, $2 +; MIPS32R2-NEXT: srlv $2, $5, $9 +; MIPS32R2-NEXT: sllv $3, $24, $12 +; MIPS32R2-NEXT: or $3, $3, $2 +; MIPS32R2-NEXT: srlv $2, $4, $9 +; MIPS32R2-NEXT: movn $3, $2, $14 +; MIPS32R2-NEXT: movz $1, $7, $9 +; MIPS32R2-NEXT: movz $3, $zero, $25 +; MIPS32R2-NEXT: movn $gp, $10, $11 +; MIPS32R2-NEXT: movn $13, $zero, $14 +; MIPS32R2-NEXT: or $4, $13, $gp +; MIPS32R2-NEXT: movn $8, $zero, $15 +; MIPS32R2-NEXT: movn $8, $4, $25 +; MIPS32R2-NEXT: movz $8, $6, $9 +; MIPS32R2-NEXT: movn $2, $zero, $14 +; MIPS32R2-NEXT: movz $2, $zero, $25 +; MIPS32R2-NEXT: move $4, $8 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: move $5, $1 +; +; MIPS32R6-LABEL: lshr_i128: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: addiu $sp, $sp, -8 +; MIPS32R6-NEXT: .cfi_def_cfa_offset 8 +; MIPS32R6-NEXT: sw $16, 4($sp) # 4-byte Folded Spill +; MIPS32R6-NEXT: .cfi_offset 16, -4 +; MIPS32R6-NEXT: lw $1, 36($sp) +; MIPS32R6-NEXT: srlv $2, $7, $1 +; MIPS32R6-NEXT: not $3, $1 +; MIPS32R6-NEXT: sll $8, $6, 1 +; MIPS32R6-NEXT: sllv $8, $8, $3 +; MIPS32R6-NEXT: or $2, $8, $2 +; MIPS32R6-NEXT: addiu $8, $1, -64 +; MIPS32R6-NEXT: srlv $9, $5, $8 +; MIPS32R6-NEXT: sll $10, $4, 1 +; MIPS32R6-NEXT: not $11, $8 +; MIPS32R6-NEXT: sllv $11, $10, $11 +; MIPS32R6-NEXT: andi $12, $1, 32 +; MIPS32R6-NEXT: seleqz $2, $2, $12 +; MIPS32R6-NEXT: or $9, $11, $9 +; MIPS32R6-NEXT: srlv $11, $6, $1 +; MIPS32R6-NEXT: selnez $13, $11, $12 +; MIPS32R6-NEXT: addiu $14, $zero, 64 +; MIPS32R6-NEXT: subu $14, $14, $1 +; MIPS32R6-NEXT: sllv $15, $5, $14 +; MIPS32R6-NEXT: andi $24, $14, 32 +; MIPS32R6-NEXT: andi $25, $8, 32 +; MIPS32R6-NEXT: seleqz $9, $9, $25 +; MIPS32R6-NEXT: seleqz $gp, $15, $24 +; MIPS32R6-NEXT: or $2, $13, $2 +; MIPS32R6-NEXT: selnez $13, $15, $24 +; MIPS32R6-NEXT: sllv $15, $4, $14 +; MIPS32R6-NEXT: not $14, $14 +; MIPS32R6-NEXT: srl $16, $5, 1 +; MIPS32R6-NEXT: srlv $14, $16, $14 +; MIPS32R6-NEXT: or $14, $15, $14 +; MIPS32R6-NEXT: seleqz $14, $14, $24 +; MIPS32R6-NEXT: srlv $8, $4, $8 +; MIPS32R6-NEXT: or $13, $13, $14 +; MIPS32R6-NEXT: or $2, $2, $gp +; MIPS32R6-NEXT: srlv $5, $5, $1 +; MIPS32R6-NEXT: selnez $14, $8, $25 +; MIPS32R6-NEXT: sltiu $15, $1, 64 +; MIPS32R6-NEXT: selnez $2, $2, $15 +; MIPS32R6-NEXT: or $9, $14, $9 +; MIPS32R6-NEXT: sllv $3, $10, $3 +; MIPS32R6-NEXT: seleqz $10, $11, $12 +; MIPS32R6-NEXT: or $10, $10, $13 +; MIPS32R6-NEXT: or $3, $3, $5 +; MIPS32R6-NEXT: seleqz $5, $9, $15 +; MIPS32R6-NEXT: seleqz $9, $zero, $15 +; MIPS32R6-NEXT: srlv $4, $4, $1 +; MIPS32R6-NEXT: seleqz $11, $4, $12 +; MIPS32R6-NEXT: selnez $11, $11, $15 +; MIPS32R6-NEXT: seleqz $7, $7, $1 +; MIPS32R6-NEXT: or $2, $2, $5 +; MIPS32R6-NEXT: selnez $2, $2, $1 +; MIPS32R6-NEXT: or $5, $7, $2 +; MIPS32R6-NEXT: or $2, $9, $11 +; MIPS32R6-NEXT: seleqz $3, $3, $12 +; MIPS32R6-NEXT: selnez $7, $4, $12 +; MIPS32R6-NEXT: seleqz $4, $6, $1 +; MIPS32R6-NEXT: selnez $6, $10, $15 +; MIPS32R6-NEXT: seleqz $8, $8, $25 +; MIPS32R6-NEXT: seleqz $8, $8, $15 +; MIPS32R6-NEXT: or $6, $6, $8 +; MIPS32R6-NEXT: selnez $1, $6, $1 +; MIPS32R6-NEXT: or $4, $4, $1 +; MIPS32R6-NEXT: or $1, $7, $3 +; MIPS32R6-NEXT: selnez $1, $1, $15 +; MIPS32R6-NEXT: or $3, $9, $1 +; MIPS32R6-NEXT: lw $16, 4($sp) # 4-byte Folded Reload +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: addiu $sp, $sp, 8 +; +; MIPS3-LABEL: lshr_i128: +; MIPS3: # %bb.0: # %entry +; MIPS3-NEXT: sll $2, $7, 0 +; MIPS3-NEXT: dsrlv $6, $4, $7 +; MIPS3-NEXT: andi $8, $2, 64 +; MIPS3-NEXT: beqz $8, .LBB5_3 +; MIPS3-NEXT: move $3, $6 +; MIPS3-NEXT: # %bb.1: # %entry +; MIPS3-NEXT: beqz $8, .LBB5_4 +; MIPS3-NEXT: daddiu $2, $zero, 0 +; MIPS3-NEXT: .LBB5_2: # %entry +; MIPS3-NEXT: jr $ra +; MIPS3-NEXT: nop +; MIPS3-NEXT: .LBB5_3: # %entry +; MIPS3-NEXT: dsrlv $1, $5, $7 +; MIPS3-NEXT: dsll $3, $4, 1 +; MIPS3-NEXT: not $2, $2 +; MIPS3-NEXT: dsllv $2, $3, $2 +; MIPS3-NEXT: or $3, $2, $1 +; MIPS3-NEXT: bnez $8, .LBB5_2 +; MIPS3-NEXT: daddiu $2, $zero, 0 +; MIPS3-NEXT: .LBB5_4: # %entry +; MIPS3-NEXT: jr $ra +; MIPS3-NEXT: move $2, $6 +; +; MIPS4-LABEL: lshr_i128: +; MIPS4: # %bb.0: # %entry +; MIPS4-NEXT: dsrlv $1, $5, $7 +; MIPS4-NEXT: dsll $2, $4, 1 +; MIPS4-NEXT: sll $5, $7, 0 +; MIPS4-NEXT: not $3, $5 +; MIPS4-NEXT: dsllv $2, $2, $3 +; MIPS4-NEXT: or $3, $2, $1 +; MIPS4-NEXT: dsrlv $2, $4, $7 +; MIPS4-NEXT: andi $1, $5, 64 +; MIPS4-NEXT: movn $3, $2, $1 +; MIPS4-NEXT: jr $ra +; MIPS4-NEXT: movn $2, $zero, $1 +; +; MIPS64-LABEL: lshr_i128: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: dsrlv $1, $5, $7 +; MIPS64-NEXT: dsll $2, $4, 1 +; MIPS64-NEXT: sll $5, $7, 0 +; MIPS64-NEXT: not $3, $5 +; MIPS64-NEXT: dsllv $2, $2, $3 +; MIPS64-NEXT: or $3, $2, $1 +; MIPS64-NEXT: dsrlv $2, $4, $7 +; MIPS64-NEXT: andi $1, $5, 64 +; MIPS64-NEXT: movn $3, $2, $1 +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: movn $2, $zero, $1 +; +; MIPS64R2-LABEL: lshr_i128: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: dsrlv $1, $5, $7 +; MIPS64R2-NEXT: dsll $2, $4, 1 +; MIPS64R2-NEXT: sll $5, $7, 0 +; MIPS64R2-NEXT: not $3, $5 +; MIPS64R2-NEXT: dsllv $2, $2, $3 +; MIPS64R2-NEXT: or $3, $2, $1 +; MIPS64R2-NEXT: dsrlv $2, $4, $7 +; MIPS64R2-NEXT: andi $1, $5, 64 +; MIPS64R2-NEXT: movn $3, $2, $1 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: movn $2, $zero, $1 +; +; MIPS64R6-LABEL: lshr_i128: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: dsrlv $1, $5, $7 +; MIPS64R6-NEXT: dsll $2, $4, 1 +; MIPS64R6-NEXT: sll $3, $7, 0 +; MIPS64R6-NEXT: not $5, $3 +; MIPS64R6-NEXT: dsllv $2, $2, $5 +; MIPS64R6-NEXT: or $1, $2, $1 +; MIPS64R6-NEXT: andi $2, $3, 64 +; MIPS64R6-NEXT: sll $2, $2, 0 +; MIPS64R6-NEXT: seleqz $1, $1, $2 +; MIPS64R6-NEXT: dsrlv $4, $4, $7 +; MIPS64R6-NEXT: selnez $3, $4, $2 +; MIPS64R6-NEXT: or $3, $3, $1 +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: seleqz $2, $4, $2 +; +; MMR3-LABEL: lshr_i128: +; MMR3: # %bb.0: # %entry +; MMR3-NEXT: addiusp -48 +; MMR3-NEXT: .cfi_def_cfa_offset 48 +; MMR3-NEXT: sw $17, 44($sp) # 4-byte Folded Spill +; MMR3-NEXT: sw $16, 40($sp) # 4-byte Folded Spill +; MMR3-NEXT: .cfi_offset 17, -4 +; MMR3-NEXT: .cfi_offset 16, -8 +; MMR3-NEXT: move $8, $7 +; MMR3-NEXT: sw $6, 32($sp) # 4-byte Folded Spill +; MMR3-NEXT: sw $5, 36($sp) # 4-byte Folded Spill +; MMR3-NEXT: move $17, $5 +; MMR3-NEXT: sw $4, 8($sp) # 4-byte Folded Spill +; MMR3-NEXT: lw $16, 76($sp) +; MMR3-NEXT: srlv $7, $8, $16 +; MMR3-NEXT: not16 $3, $16 +; MMR3-NEXT: sw $3, 24($sp) # 4-byte Folded Spill +; MMR3-NEXT: sll16 $2, $6, 1 +; MMR3-NEXT: sllv $3, $2, $3 +; MMR3-NEXT: li16 $4, 64 +; MMR3-NEXT: or16 $3, $7 +; MMR3-NEXT: srlv $5, $6, $16 +; MMR3-NEXT: sw $5, 12($sp) # 4-byte Folded Spill +; MMR3-NEXT: subu16 $7, $4, $16 +; MMR3-NEXT: sllv $9, $17, $7 +; MMR3-NEXT: andi16 $2, $7, 32 +; MMR3-NEXT: sw $2, 28($sp) # 4-byte Folded Spill +; MMR3-NEXT: andi16 $17, $16, 32 +; MMR3-NEXT: sw $17, 16($sp) # 4-byte Folded Spill +; MMR3-NEXT: move $4, $9 +; MMR3-NEXT: li16 $6, 0 +; MMR3-NEXT: movn $4, $6, $2 +; MMR3-NEXT: movn $3, $5, $17 +; MMR3-NEXT: addiu $2, $16, -64 +; MMR3-NEXT: lw $5, 36($sp) # 4-byte Folded Reload +; MMR3-NEXT: srlv $5, $5, $2 +; MMR3-NEXT: sw $5, 20($sp) # 4-byte Folded Spill +; MMR3-NEXT: lw $17, 8($sp) # 4-byte Folded Reload +; MMR3-NEXT: sll16 $6, $17, 1 +; MMR3-NEXT: sw $6, 4($sp) # 4-byte Folded Spill +; MMR3-NEXT: not16 $5, $2 +; MMR3-NEXT: sllv $5, $6, $5 +; MMR3-NEXT: or16 $3, $4 +; MMR3-NEXT: lw $4, 20($sp) # 4-byte Folded Reload +; MMR3-NEXT: or16 $5, $4 +; MMR3-NEXT: srlv $1, $17, $2 +; MMR3-NEXT: andi16 $2, $2, 32 +; MMR3-NEXT: sw $2, 20($sp) # 4-byte Folded Spill +; MMR3-NEXT: movn $5, $1, $2 +; MMR3-NEXT: sllv $2, $17, $7 +; MMR3-NEXT: not16 $4, $7 +; MMR3-NEXT: lw $7, 36($sp) # 4-byte Folded Reload +; MMR3-NEXT: srl16 $6, $7, 1 +; MMR3-NEXT: srlv $4, $6, $4 +; MMR3-NEXT: sltiu $11, $16, 64 +; MMR3-NEXT: movn $5, $3, $11 +; MMR3-NEXT: or16 $4, $2 +; MMR3-NEXT: srlv $2, $7, $16 +; MMR3-NEXT: lw $3, 24($sp) # 4-byte Folded Reload +; MMR3-NEXT: lw $6, 4($sp) # 4-byte Folded Reload +; MMR3-NEXT: sllv $3, $6, $3 +; MMR3-NEXT: or16 $3, $2 +; MMR3-NEXT: srlv $2, $17, $16 +; MMR3-NEXT: lw $6, 16($sp) # 4-byte Folded Reload +; MMR3-NEXT: movn $3, $2, $6 +; MMR3-NEXT: sltiu $10, $16, 64 +; MMR3-NEXT: movz $5, $8, $16 +; MMR3-NEXT: li16 $7, 0 +; MMR3-NEXT: movz $3, $7, $10 +; MMR3-NEXT: lw $17, 28($sp) # 4-byte Folded Reload +; MMR3-NEXT: movn $4, $9, $17 +; MMR3-NEXT: lw $7, 12($sp) # 4-byte Folded Reload +; MMR3-NEXT: li16 $17, 0 +; MMR3-NEXT: movn $7, $17, $6 +; MMR3-NEXT: or16 $7, $4 +; MMR3-NEXT: lw $4, 20($sp) # 4-byte Folded Reload +; MMR3-NEXT: movn $1, $17, $4 +; MMR3-NEXT: li16 $17, 0 +; MMR3-NEXT: movn $1, $7, $11 +; MMR3-NEXT: lw $4, 32($sp) # 4-byte Folded Reload +; MMR3-NEXT: movz $1, $4, $16 +; MMR3-NEXT: movn $2, $17, $6 +; MMR3-NEXT: li16 $4, 0 +; MMR3-NEXT: movz $2, $4, $10 +; MMR3-NEXT: move $4, $1 +; MMR3-NEXT: lw $16, 40($sp) # 4-byte Folded Reload +; MMR3-NEXT: lw $17, 44($sp) # 4-byte Folded Reload +; MMR3-NEXT: addiusp 48 +; MMR3-NEXT: jrc $ra +; +; MMR6-LABEL: lshr_i128: +; MMR6: # %bb.0: # %entry +; MMR6-NEXT: addiu $sp, $sp, -48 +; MMR6-NEXT: .cfi_def_cfa_offset 48 +; MMR6-NEXT: sw $17, 44($sp) # 4-byte Folded Spill +; MMR6-NEXT: sw $16, 40($sp) # 4-byte Folded Spill +; MMR6-NEXT: .cfi_offset 17, -4 +; MMR6-NEXT: .cfi_offset 16, -8 +; MMR6-NEXT: move $1, $7 +; MMR6-NEXT: sw $5, 8($sp) # 4-byte Folded Spill +; MMR6-NEXT: move $16, $4 +; MMR6-NEXT: sw $16, 32($sp) # 4-byte Folded Spill +; MMR6-NEXT: lw $3, 76($sp) +; MMR6-NEXT: srlv $2, $1, $3 +; MMR6-NEXT: not16 $5, $3 +; MMR6-NEXT: sw $5, 24($sp) # 4-byte Folded Spill +; MMR6-NEXT: move $4, $6 +; MMR6-NEXT: sw $4, 28($sp) # 4-byte Folded Spill +; MMR6-NEXT: sll16 $6, $4, 1 +; MMR6-NEXT: sllv $17, $6, $5 +; MMR6-NEXT: or16 $17, $2 +; MMR6-NEXT: addiu $7, $3, -64 +; MMR6-NEXT: sw $7, 36($sp) # 4-byte Folded Spill +; MMR6-NEXT: lw $5, 8($sp) # 4-byte Folded Reload +; MMR6-NEXT: srlv $6, $5, $7 +; MMR6-NEXT: sll16 $2, $16, 1 +; MMR6-NEXT: sw $2, 20($sp) # 4-byte Folded Spill +; MMR6-NEXT: not16 $16, $7 +; MMR6-NEXT: sllv $7, $2, $16 +; MMR6-NEXT: andi16 $16, $3, 32 +; MMR6-NEXT: seleqz $8, $17, $16 +; MMR6-NEXT: or16 $7, $6 +; MMR6-NEXT: srlv $10, $4, $3 +; MMR6-NEXT: selnez $9, $10, $16 +; MMR6-NEXT: li16 $17, 64 +; MMR6-NEXT: subu16 $6, $17, $3 +; MMR6-NEXT: sllv $11, $5, $6 +; MMR6-NEXT: move $17, $5 +; MMR6-NEXT: andi16 $4, $6, 32 +; MMR6-NEXT: lw $2, 36($sp) # 4-byte Folded Reload +; MMR6-NEXT: andi16 $2, $2, 32 +; MMR6-NEXT: sw $2, 16($sp) # 4-byte Folded Spill +; MMR6-NEXT: seleqz $12, $7, $2 +; MMR6-NEXT: seleqz $2, $11, $4 +; MMR6-NEXT: sw $2, 12($sp) # 4-byte Folded Spill +; MMR6-NEXT: or $5, $9, $8 +; MMR6-NEXT: selnez $8, $11, $4 +; MMR6-NEXT: lw $2, 32($sp) # 4-byte Folded Reload +; MMR6-NEXT: sllv $7, $2, $6 +; MMR6-NEXT: sw $7, 4($sp) # 4-byte Folded Spill +; MMR6-NEXT: not16 $6, $6 +; MMR6-NEXT: move $7, $17 +; MMR6-NEXT: srl16 $17, $7, 1 +; MMR6-NEXT: srlv $6, $17, $6 +; MMR6-NEXT: lw $17, 4($sp) # 4-byte Folded Reload +; MMR6-NEXT: or16 $6, $17 +; MMR6-NEXT: seleqz $4, $6, $4 +; MMR6-NEXT: lw $6, 36($sp) # 4-byte Folded Reload +; MMR6-NEXT: srlv $9, $2, $6 +; MMR6-NEXT: or $4, $8, $4 +; MMR6-NEXT: lw $2, 12($sp) # 4-byte Folded Reload +; MMR6-NEXT: or16 $5, $2 +; MMR6-NEXT: srlv $2, $7, $3 +; MMR6-NEXT: lw $17, 16($sp) # 4-byte Folded Reload +; MMR6-NEXT: selnez $6, $9, $17 +; MMR6-NEXT: sltiu $8, $3, 64 +; MMR6-NEXT: selnez $13, $5, $8 +; MMR6-NEXT: or $11, $6, $12 +; MMR6-NEXT: lw $5, 24($sp) # 4-byte Folded Reload +; MMR6-NEXT: lw $6, 20($sp) # 4-byte Folded Reload +; MMR6-NEXT: sllv $7, $6, $5 +; MMR6-NEXT: seleqz $6, $10, $16 +; MMR6-NEXT: li16 $5, 0 +; MMR6-NEXT: or16 $6, $4 +; MMR6-NEXT: or16 $7, $2 +; MMR6-NEXT: seleqz $4, $11, $8 +; MMR6-NEXT: seleqz $10, $5, $8 +; MMR6-NEXT: lw $2, 32($sp) # 4-byte Folded Reload +; MMR6-NEXT: srlv $11, $2, $3 +; MMR6-NEXT: seleqz $5, $11, $16 +; MMR6-NEXT: selnez $12, $5, $8 +; MMR6-NEXT: seleqz $1, $1, $3 +; MMR6-NEXT: or $2, $13, $4 +; MMR6-NEXT: selnez $2, $2, $3 +; MMR6-NEXT: or $5, $1, $2 +; MMR6-NEXT: or $2, $10, $12 +; MMR6-NEXT: seleqz $1, $7, $16 +; MMR6-NEXT: selnez $7, $11, $16 +; MMR6-NEXT: lw $4, 28($sp) # 4-byte Folded Reload +; MMR6-NEXT: seleqz $4, $4, $3 +; MMR6-NEXT: selnez $6, $6, $8 +; MMR6-NEXT: seleqz $9, $9, $17 +; MMR6-NEXT: seleqz $9, $9, $8 +; MMR6-NEXT: or $6, $6, $9 +; MMR6-NEXT: selnez $3, $6, $3 +; MMR6-NEXT: or $4, $4, $3 +; MMR6-NEXT: or $1, $7, $1 +; MMR6-NEXT: selnez $1, $1, $8 +; MMR6-NEXT: or $3, $10, $1 +; MMR6-NEXT: lw $16, 40($sp) # 4-byte Folded Reload +; MMR6-NEXT: lw $17, 44($sp) # 4-byte Folded Reload +; MMR6-NEXT: addiu $sp, $sp, 48 +; MMR6-NEXT: jrc $ra entry: -; ALL-LABEL: lshr_i128: - - ; o32 shouldn't use TImode helpers. - ; GP32-NOT: lw $25, %call16(__lshrti3)($gp) - ; MM-NOT: lw $25, %call16(__lshrti3)($2) - - ; M3: sll $[[T0:[0-9]+]], $7, 0 - ; M3: dsrlv $[[T1:[0-9]+]], $4, $7 - ; M3: andi $[[T2:[0-9]+]], $[[T0]], 64 - ; M3: beqz $[[T3:[0-9]+]], [[BB0:\.LBB[0-9_]+]] - ; M3: move $3, $[[T1]] - ; M3: beqz $[[T3]], [[BB1:\.LBB[0-9_]+]] - ; M3: daddiu $2, $zero, 0 - ; M3: [[EXIT:\.LBB[0-9_]+]]: - ; M3: jr $ra - ; M3: nop - ; M3: [[BB0]]: - ; M3: dsrlv $[[T4:[0-9]+]], $5, $7 - ; M3: dsll $[[T5:[0-9]+]], $4, 1 - ; M3: not $[[T6:[0-9]+]], $[[T0]] - ; M3: dsllv $[[T7:[0-9]+]], $[[T5]], $[[T6]] - ; M3: or $3, $[[T7]], $[[T4]] - ; M3: bnez $[[T3]], [[EXIT]] - ; M3: daddiu $2, $zero, 0 - ; M3: [[BB1]]: - ; M3: jr $ra - ; M3: move $2, $[[T1]] - - ; GP64-NOT-R6: dsrlv $[[T0:[0-9]+]], $5, $7 - ; GP64-NOT-R6: dsll $[[T1:[0-9]+]], $4, 1 - ; GP64-NOT-R6: sll $[[T2:[0-9]+]], $7, 0 - ; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T2]] - ; GP64-NOT-R6: dsllv $[[T4:[0-9]+]], $[[T1]], $[[T3]] - ; GP64-NOT-R6: or $3, $[[T4]], $[[T0]] - ; GP64-NOT-R6: dsrlv $2, $4, $7 - ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T2]], 64 - ; GP64-NOT-R6: movn $3, $2, $[[T5]] - ; GP64-NOT-R6: jr $ra - ; GP64-NOT-R6: movn $2, $zero, $1 - ; 64R6: dsrlv $[[T0:[0-9]+]], $5, $7 - ; 64R6: dsll $[[T1:[0-9]+]], $4, 1 - ; 64R6: sll $[[T2:[0-9]+]], $7, 0 - ; 64R6: not $[[T3:[0-9]+]], $[[T2]] - ; 64R6: dsllv $[[T4:[0-9]+]], $[[T1]], $[[T3]] - ; 64R6: or $[[T5:[0-9]+]], $[[T4]], $[[T0]] - ; 64R6: andi $[[T6:[0-9]+]], $[[T2]], 64 - ; 64R6: sll $[[T7:[0-9]+]], $[[T6]], 0 - ; 64R6: seleqz $[[T8:[0-9]+]], $[[T5]], $[[T7]] - ; 64R6: dsrlv $[[T9:[0-9]+]], $4, $7 - ; 64R6: selnez $[[T10:[0-9]+]], $[[T9]], $[[T7]] - ; 64R6: or $3, $[[T10]], $[[T8]] - ; 64R6: jr $ra - ; 64R6: seleqz $2, $[[T9]], $[[T7]] +; o32 shouldn't use TImode helpers. +; GP32-NOT: lw $25, %call16(__lshrti3)($gp) +; MM-NOT: lw $25, %call16(__lshrti3)($2) %r = lshr i128 %a, %b ret i128 %r diff --git a/test/CodeGen/Mips/llvm-ir/or.ll b/test/CodeGen/Mips/llvm-ir/or.ll index 6850bed9659..4eae6e49f8a 100644 --- a/test/CodeGen/Mips/llvm-ir/or.ll +++ b/test/CodeGen/Mips/llvm-ir/or.ll @@ -1,623 +1,1209 @@ -; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefixes=ALL,GP32 -; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s -check-prefixes=ALL,GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -check-prefixes=ALL,GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s -check-prefixes=ALL,GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s -check-prefixes=ALL,GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s -check-prefixes=ALL,GP32 -; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s -check-prefixes=ALL,GP64 -; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s -check-prefixes=ALL,GP64 -; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s -check-prefixes=ALL,GP64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s -check-prefixes=ALL,GP64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s -check-prefixes=ALL,GP64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s -check-prefixes=ALL,GP64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s -check-prefixes=ALL,GP64 -; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \ -; RUN: -check-prefixes=ALL,MM,MM32 -; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ -; RUN: -check-prefixes=ALL,MM,MM32 +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips2 | FileCheck %s -check-prefix=GP32 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32 | FileCheck %s -check-prefix=GP32 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r2 | FileCheck %s -check-prefix=GP32 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 | FileCheck %s -check-prefix=GP32 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r5 | FileCheck %s -check-prefix=GP32 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 | FileCheck %s -check-prefix=GP32 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips3 | FileCheck %s -check-prefix=GP64 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips4 | FileCheck %s -check-prefix=GP64 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64 | FileCheck %s -check-prefix=GP64 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r2 | FileCheck %s -check-prefix=GP64 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r3 | FileCheck %s -check-prefix=GP64 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r5 | FileCheck %s -check-prefix=GP64 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r6 | FileCheck %s -check-prefix=GP64 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefix=MM32 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefix=MM32R6 define signext i1 @or_i1(i1 signext %a, i1 signext %b) { +; GP32-LABEL: or_i1: +; GP32: # %bb.0: # %entry +; GP32-NEXT: jr $ra +; GP32-NEXT: or $2, $4, $5 +; +; GP64-LABEL: or_i1: +; GP64: # %bb.0: # %entry +; GP64-NEXT: or $1, $4, $5 +; GP64-NEXT: jr $ra +; GP64-NEXT: sll $2, $1, 0 +; +; MM32-LABEL: or_i1: +; MM32: # %bb.0: # %entry +; MM32-NEXT: or16 $4, $5 +; MM32-NEXT: move $2, $4 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i1: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: or16 $4, $5 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i1: - - ; GP32: or $2, $4, $5 - - ; GP64: or $1, $4, $5 - - ; MM32: or16 $[[T0:[0-9]+]], $5 - ; MM32 move $2, $[[T0]] - %r = or i1 %a, %b ret i1 %r } define signext i8 @or_i8(i8 signext %a, i8 signext %b) { +; GP32-LABEL: or_i8: +; GP32: # %bb.0: # %entry +; GP32-NEXT: jr $ra +; GP32-NEXT: or $2, $4, $5 +; +; GP64-LABEL: or_i8: +; GP64: # %bb.0: # %entry +; GP64-NEXT: or $1, $4, $5 +; GP64-NEXT: jr $ra +; GP64-NEXT: sll $2, $1, 0 +; +; MM32-LABEL: or_i8: +; MM32: # %bb.0: # %entry +; MM32-NEXT: or16 $4, $5 +; MM32-NEXT: move $2, $4 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i8: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: or16 $4, $5 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i8: - - ; GP32: or $2, $4, $5 - - ; GP64: or $1, $4, $5 - - ; MM32: or16 $[[T0:[0-9]+]], $5 - ; MM32 move $2, $[[T0]] - %r = or i8 %a, %b ret i8 %r } define signext i16 @or_i16(i16 signext %a, i16 signext %b) { +; GP32-LABEL: or_i16: +; GP32: # %bb.0: # %entry +; GP32-NEXT: jr $ra +; GP32-NEXT: or $2, $4, $5 +; +; GP64-LABEL: or_i16: +; GP64: # %bb.0: # %entry +; GP64-NEXT: or $1, $4, $5 +; GP64-NEXT: jr $ra +; GP64-NEXT: sll $2, $1, 0 +; +; MM32-LABEL: or_i16: +; MM32: # %bb.0: # %entry +; MM32-NEXT: or16 $4, $5 +; MM32-NEXT: move $2, $4 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i16: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: or16 $4, $5 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i16: - - ; GP32: or $2, $4, $5 - - ; GP64: or $1, $4, $5 - - ; MM32: or16 $[[T0:[0-9]+]], $5 - ; MM32 move $2, $[[T0]] - %r = or i16 %a, %b ret i16 %r } define signext i32 @or_i32(i32 signext %a, i32 signext %b) { +; GP32-LABEL: or_i32: +; GP32: # %bb.0: # %entry +; GP32-NEXT: jr $ra +; GP32-NEXT: or $2, $4, $5 +; +; GP64-LABEL: or_i32: +; GP64: # %bb.0: # %entry +; GP64-NEXT: or $1, $4, $5 +; GP64-NEXT: jr $ra +; GP64-NEXT: sll $2, $1, 0 +; +; MM32-LABEL: or_i32: +; MM32: # %bb.0: # %entry +; MM32-NEXT: or16 $4, $5 +; MM32-NEXT: move $2, $4 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i32: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: or16 $4, $5 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i32: - - ; GP32: or $2, $4, $5 - - ; GP64: or $[[T0:[0-9]+]], $4, $5 - ; FIXME: The sll instruction below is redundant. - ; GP64: sll $2, $[[T0]], 0 - - ; MM32: or16 $[[T0:[0-9]+]], $5 - ; MM32: move $2, $[[T0]] - %r = or i32 %a, %b ret i32 %r } define signext i64 @or_i64(i64 signext %a, i64 signext %b) { +; GP32-LABEL: or_i64: +; GP32: # %bb.0: # %entry +; GP32-NEXT: or $2, $4, $6 +; GP32-NEXT: jr $ra +; GP32-NEXT: or $3, $5, $7 +; +; GP64-LABEL: or_i64: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: or $2, $4, $5 +; +; MM32-LABEL: or_i64: +; MM32: # %bb.0: # %entry +; MM32-NEXT: or16 $4, $6 +; MM32-NEXT: or16 $5, $7 +; MM32-NEXT: move $2, $4 +; MM32-NEXT: move $3, $5 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i64: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: or16 $4, $6 +; MM32R6-NEXT: or16 $5, $7 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: move $3, $5 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i64: - - ; GP32: or $2, $4, $6 - ; GP32: or $3, $5, $7 - - ; GP64: or $2, $4, $5 - - ; MM32: or16 $[[T0:[0-9]+]], $6 - ; MM32: or16 $[[T1:[0-9]+]], $7 - ; MM32: move $2, $[[T0]] - ; MM32: move $3, $[[T1]] - %r = or i64 %a, %b ret i64 %r } define signext i128 @or_i128(i128 signext %a, i128 signext %b) { +; GP32-LABEL: or_i128: +; GP32: # %bb.0: # %entry +; GP32-NEXT: lw $1, 20($sp) +; GP32-NEXT: lw $2, 16($sp) +; GP32-NEXT: or $2, $4, $2 +; GP32-NEXT: or $3, $5, $1 +; GP32-NEXT: lw $1, 24($sp) +; GP32-NEXT: or $4, $6, $1 +; GP32-NEXT: lw $1, 28($sp) +; GP32-NEXT: jr $ra +; GP32-NEXT: or $5, $7, $1 +; +; GP64-LABEL: or_i128: +; GP64: # %bb.0: # %entry +; GP64-NEXT: or $2, $4, $6 +; GP64-NEXT: jr $ra +; GP64-NEXT: or $3, $5, $7 +; +; MM32-LABEL: or_i128: +; MM32: # %bb.0: # %entry +; MM32-NEXT: lw $3, 20($sp) +; MM32-NEXT: lw $2, 16($sp) +; MM32-NEXT: or16 $2, $4 +; MM32-NEXT: or16 $3, $5 +; MM32-NEXT: lw $4, 24($sp) +; MM32-NEXT: or16 $4, $6 +; MM32-NEXT: lw $5, 28($sp) +; MM32-NEXT: or16 $5, $7 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i128: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: lw $3, 20($sp) +; MM32R6-NEXT: lw $2, 16($sp) +; MM32R6-NEXT: or16 $2, $4 +; MM32R6-NEXT: or16 $3, $5 +; MM32R6-NEXT: lw $4, 24($sp) +; MM32R6-NEXT: or16 $4, $6 +; MM32R6-NEXT: lw $5, 28($sp) +; MM32R6-NEXT: or16 $5, $7 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i128: - - ; GP32: lw $[[T1:[0-9]+]], 20($sp) - ; GP32: lw $[[T2:[0-9]+]], 16($sp) - ; GP32: or $2, $4, $[[T2]] - ; GP32: or $3, $5, $[[T1]] - ; GP32: lw $[[T0:[0-9]+]], 24($sp) - ; GP32: or $4, $6, $[[T0]] - ; GP32: lw $[[T3:[0-9]+]], 28($sp) - ; GP32: or $5, $7, $[[T3]] - - ; GP64: or $2, $4, $6 - ; GP64: or $3, $5, $7 - - ; MM32: lw $[[T1:[0-9]+]], 20($sp) - ; MM32: lw $[[T2:[0-9]+]], 16($sp) - ; MM32: or16 $[[T2]], $4 - ; MM32: or16 $[[T1]], $5 - ; MM32: lw $[[T0:[0-9]+]], 24($sp) - ; MM32: or16 $[[T0]], $6 - ; MM32: lw $[[T3:[0-9]+]], 28($sp) - ; MM32: or16 $[[T3]], $7 - %r = or i128 %a, %b ret i128 %r } define signext i1 @or_i1_4(i1 signext %b) { +; GP32-LABEL: or_i1_4: +; GP32: # %bb.0: # %entry +; GP32-NEXT: jr $ra +; GP32-NEXT: move $2, $4 +; +; GP64-LABEL: or_i1_4: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: move $2, $4 +; +; MM32-LABEL: or_i1_4: +; MM32: # %bb.0: # %entry +; MM32-NEXT: move $2, $4 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i1_4: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i1_4: - - ; ALL: move $2, $4 - %r = or i1 4, %b ret i1 %r } define signext i8 @or_i8_4(i8 signext %b) { +; GP32-LABEL: or_i8_4: +; GP32: # %bb.0: # %entry +; GP32-NEXT: jr $ra +; GP32-NEXT: ori $2, $4, 4 +; +; GP64-LABEL: or_i8_4: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: ori $2, $4, 4 +; +; MM32-LABEL: or_i8_4: +; MM32: # %bb.0: # %entry +; MM32-NEXT: jr $ra +; MM32-NEXT: ori $2, $4, 4 +; +; MM32R6-LABEL: or_i8_4: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: ori $2, $4, 4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i8_4: - - ; ALL: ori $2, $4, 4 - %r = or i8 4, %b ret i8 %r } define signext i16 @or_i16_4(i16 signext %b) { +; GP32-LABEL: or_i16_4: +; GP32: # %bb.0: # %entry +; GP32-NEXT: jr $ra +; GP32-NEXT: ori $2, $4, 4 +; +; GP64-LABEL: or_i16_4: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: ori $2, $4, 4 +; +; MM32-LABEL: or_i16_4: +; MM32: # %bb.0: # %entry +; MM32-NEXT: jr $ra +; MM32-NEXT: ori $2, $4, 4 +; +; MM32R6-LABEL: or_i16_4: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: ori $2, $4, 4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i16_4: - - ; ALL: ori $2, $4, 4 - %r = or i16 4, %b ret i16 %r } define signext i32 @or_i32_4(i32 signext %b) { +; GP32-LABEL: or_i32_4: +; GP32: # %bb.0: # %entry +; GP32-NEXT: jr $ra +; GP32-NEXT: ori $2, $4, 4 +; +; GP64-LABEL: or_i32_4: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: ori $2, $4, 4 +; +; MM32-LABEL: or_i32_4: +; MM32: # %bb.0: # %entry +; MM32-NEXT: jr $ra +; MM32-NEXT: ori $2, $4, 4 +; +; MM32R6-LABEL: or_i32_4: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: ori $2, $4, 4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i32_4: - - ; ALL: ori $2, $4, 4 - %r = or i32 4, %b ret i32 %r } define signext i64 @or_i64_4(i64 signext %b) { +; GP32-LABEL: or_i64_4: +; GP32: # %bb.0: # %entry +; GP32-NEXT: ori $3, $5, 4 +; GP32-NEXT: jr $ra +; GP32-NEXT: move $2, $4 +; +; GP64-LABEL: or_i64_4: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: ori $2, $4, 4 +; +; MM32-LABEL: or_i64_4: +; MM32: # %bb.0: # %entry +; MM32-NEXT: ori $3, $5, 4 +; MM32-NEXT: move $2, $4 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i64_4: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: ori $3, $5, 4 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i64_4: - - ; GP32: ori $3, $5, 4 - ; GP32: move $2, $4 - - ; GP64: ori $2, $4, 4 - - ; MM32: ori $3, $5, 4 - ; MM32: move $2, $4 - %r = or i64 4, %b ret i64 %r } define signext i128 @or_i128_4(i128 signext %b) { +; GP32-LABEL: or_i128_4: +; GP32: # %bb.0: # %entry +; GP32-NEXT: ori $1, $7, 4 +; GP32-NEXT: move $2, $4 +; GP32-NEXT: move $3, $5 +; GP32-NEXT: move $4, $6 +; GP32-NEXT: jr $ra +; GP32-NEXT: move $5, $1 +; +; GP64-LABEL: or_i128_4: +; GP64: # %bb.0: # %entry +; GP64-NEXT: ori $3, $5, 4 +; GP64-NEXT: jr $ra +; GP64-NEXT: move $2, $4 +; +; MM32-LABEL: or_i128_4: +; MM32: # %bb.0: # %entry +; MM32-NEXT: ori $1, $7, 4 +; MM32-NEXT: move $2, $4 +; MM32-NEXT: move $3, $5 +; MM32-NEXT: move $4, $6 +; MM32-NEXT: move $5, $1 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i128_4: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: ori $1, $7, 4 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: move $3, $5 +; MM32R6-NEXT: move $4, $6 +; MM32R6-NEXT: move $5, $1 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i128_4: - - ; GP32: ori $[[T0:[0-9]+]], $7, 4 - ; GP32: move $2, $4 - ; GP32: move $3, $5 - ; GP32: move $4, $6 - ; GP32: move $5, $[[T0]] - - ; GP64: ori $3, $5, 4 - ; GP64: move $2, $4 - - ; MM32: ori $[[T0:[0-9]+]], $7, 4 - ; MM32: move $2, $4 - ; MM32: move $3, $5 - ; MM32: move $4, $6 - ; MM32: move $5, $[[T0]] - %r = or i128 4, %b ret i128 %r } define signext i1 @or_i1_31(i1 signext %b) { +; GP32-LABEL: or_i1_31: +; GP32: # %bb.0: # %entry +; GP32-NEXT: jr $ra +; GP32-NEXT: addiu $2, $zero, -1 +; +; GP64-LABEL: or_i1_31: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: addiu $2, $zero, -1 +; +; MM32-LABEL: or_i1_31: +; MM32: # %bb.0: # %entry +; MM32-NEXT: li16 $2, -1 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i1_31: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: li16 $2, -1 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i1_31: - - ; GP32: addiu $2, $zero, -1 - - ; GP64: addiu $2, $zero, -1 - - ; MM: li16 $2, -1 - %r = or i1 31, %b ret i1 %r } define signext i8 @or_i8_31(i8 signext %b) { +; GP32-LABEL: or_i8_31: +; GP32: # %bb.0: # %entry +; GP32-NEXT: jr $ra +; GP32-NEXT: ori $2, $4, 31 +; +; GP64-LABEL: or_i8_31: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: ori $2, $4, 31 +; +; MM32-LABEL: or_i8_31: +; MM32: # %bb.0: # %entry +; MM32-NEXT: jr $ra +; MM32-NEXT: ori $2, $4, 31 +; +; MM32R6-LABEL: or_i8_31: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: ori $2, $4, 31 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i8_31: - - ; ALL: ori $2, $4, 31 - %r = or i8 31, %b ret i8 %r } define signext i16 @or_i16_31(i16 signext %b) { +; GP32-LABEL: or_i16_31: +; GP32: # %bb.0: # %entry +; GP32-NEXT: jr $ra +; GP32-NEXT: ori $2, $4, 31 +; +; GP64-LABEL: or_i16_31: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: ori $2, $4, 31 +; +; MM32-LABEL: or_i16_31: +; MM32: # %bb.0: # %entry +; MM32-NEXT: jr $ra +; MM32-NEXT: ori $2, $4, 31 +; +; MM32R6-LABEL: or_i16_31: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: ori $2, $4, 31 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i16_31: - - ; ALL: ori $2, $4, 31 - %r = or i16 31, %b ret i16 %r } define signext i32 @or_i32_31(i32 signext %b) { +; GP32-LABEL: or_i32_31: +; GP32: # %bb.0: # %entry +; GP32-NEXT: jr $ra +; GP32-NEXT: ori $2, $4, 31 +; +; GP64-LABEL: or_i32_31: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: ori $2, $4, 31 +; +; MM32-LABEL: or_i32_31: +; MM32: # %bb.0: # %entry +; MM32-NEXT: jr $ra +; MM32-NEXT: ori $2, $4, 31 +; +; MM32R6-LABEL: or_i32_31: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: ori $2, $4, 31 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i32_31: - - ; ALL: ori $2, $4, 31 - %r = or i32 31, %b ret i32 %r } define signext i64 @or_i64_31(i64 signext %b) { +; GP32-LABEL: or_i64_31: +; GP32: # %bb.0: # %entry +; GP32-NEXT: ori $3, $5, 31 +; GP32-NEXT: jr $ra +; GP32-NEXT: move $2, $4 +; +; GP64-LABEL: or_i64_31: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: ori $2, $4, 31 +; +; MM32-LABEL: or_i64_31: +; MM32: # %bb.0: # %entry +; MM32-NEXT: ori $3, $5, 31 +; MM32-NEXT: move $2, $4 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i64_31: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: ori $3, $5, 31 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i64_31: - - ; GP32: ori $3, $5, 31 - ; GP32: move $2, $4 - - ; GP64: ori $2, $4, 31 - - ; MM32: ori $3, $5, 31 - ; MM32: move $2, $4 - %r = or i64 31, %b ret i64 %r } define signext i128 @or_i128_31(i128 signext %b) { +; GP32-LABEL: or_i128_31: +; GP32: # %bb.0: # %entry +; GP32-NEXT: ori $1, $7, 31 +; GP32-NEXT: move $2, $4 +; GP32-NEXT: move $3, $5 +; GP32-NEXT: move $4, $6 +; GP32-NEXT: jr $ra +; GP32-NEXT: move $5, $1 +; +; GP64-LABEL: or_i128_31: +; GP64: # %bb.0: # %entry +; GP64-NEXT: ori $3, $5, 31 +; GP64-NEXT: jr $ra +; GP64-NEXT: move $2, $4 +; +; MM32-LABEL: or_i128_31: +; MM32: # %bb.0: # %entry +; MM32-NEXT: ori $1, $7, 31 +; MM32-NEXT: move $2, $4 +; MM32-NEXT: move $3, $5 +; MM32-NEXT: move $4, $6 +; MM32-NEXT: move $5, $1 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i128_31: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: ori $1, $7, 31 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: move $3, $5 +; MM32R6-NEXT: move $4, $6 +; MM32R6-NEXT: move $5, $1 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i128_31: - - ; GP32: ori $[[T0:[0-9]+]], $7, 31 - ; GP32: move $2, $4 - ; GP32: move $3, $5 - ; GP32: move $4, $6 - ; GP32: move $5, $[[T0]] - - ; GP64: ori $3, $5, 31 - ; GP64: move $2, $4 - - ; MM32: ori $[[T0:[0-9]+]], $7, 31 - ; MM32: move $2, $4 - ; MM32: move $3, $5 - ; MM32: move $4, $6 - ; MM32: move $5, $[[T0]] - %r = or i128 31, %b ret i128 %r } define signext i1 @or_i1_255(i1 signext %b) { +; GP32-LABEL: or_i1_255: +; GP32: # %bb.0: # %entry +; GP32-NEXT: jr $ra +; GP32-NEXT: addiu $2, $zero, -1 +; +; GP64-LABEL: or_i1_255: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: addiu $2, $zero, -1 +; +; MM32-LABEL: or_i1_255: +; MM32: # %bb.0: # %entry +; MM32-NEXT: li16 $2, -1 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i1_255: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: li16 $2, -1 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i1_255: - - ; GP32: addiu $2, $zero, -1 - - ; GP64: addiu $2, $zero, -1 - - ; MM: li16 $2, -1 - %r = or i1 255, %b ret i1 %r } define signext i8 @or_i8_255(i8 signext %b) { +; GP32-LABEL: or_i8_255: +; GP32: # %bb.0: # %entry +; GP32-NEXT: jr $ra +; GP32-NEXT: addiu $2, $zero, -1 +; +; GP64-LABEL: or_i8_255: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: addiu $2, $zero, -1 +; +; MM32-LABEL: or_i8_255: +; MM32: # %bb.0: # %entry +; MM32-NEXT: li16 $2, -1 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i8_255: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: li16 $2, -1 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i8_255: - - ; GP32: addiu $2, $zero, -1 - - ; GP64: addiu $2, $zero, -1 - - ; MM: li16 $2, -1 - %r = or i8 255, %b ret i8 %r } define signext i16 @or_i16_255(i16 signext %b) { +; GP32-LABEL: or_i16_255: +; GP32: # %bb.0: # %entry +; GP32-NEXT: jr $ra +; GP32-NEXT: ori $2, $4, 255 +; +; GP64-LABEL: or_i16_255: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: ori $2, $4, 255 +; +; MM32-LABEL: or_i16_255: +; MM32: # %bb.0: # %entry +; MM32-NEXT: jr $ra +; MM32-NEXT: ori $2, $4, 255 +; +; MM32R6-LABEL: or_i16_255: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: ori $2, $4, 255 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i16_255: - - ; ALL: ori $2, $4, 255 - %r = or i16 255, %b ret i16 %r } define signext i32 @or_i32_255(i32 signext %b) { +; GP32-LABEL: or_i32_255: +; GP32: # %bb.0: # %entry +; GP32-NEXT: jr $ra +; GP32-NEXT: ori $2, $4, 255 +; +; GP64-LABEL: or_i32_255: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: ori $2, $4, 255 +; +; MM32-LABEL: or_i32_255: +; MM32: # %bb.0: # %entry +; MM32-NEXT: jr $ra +; MM32-NEXT: ori $2, $4, 255 +; +; MM32R6-LABEL: or_i32_255: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: ori $2, $4, 255 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i32_255: - - ; ALL: ori $2, $4, 255 - %r = or i32 255, %b ret i32 %r } define signext i64 @or_i64_255(i64 signext %b) { +; GP32-LABEL: or_i64_255: +; GP32: # %bb.0: # %entry +; GP32-NEXT: ori $3, $5, 255 +; GP32-NEXT: jr $ra +; GP32-NEXT: move $2, $4 +; +; GP64-LABEL: or_i64_255: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: ori $2, $4, 255 +; +; MM32-LABEL: or_i64_255: +; MM32: # %bb.0: # %entry +; MM32-NEXT: ori $3, $5, 255 +; MM32-NEXT: move $2, $4 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i64_255: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: ori $3, $5, 255 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i64_255: - - ; GP32: ori $3, $5, 255 - ; GP32: move $2, $4 - - ; GP64: ori $2, $4, 255 - - ; MM32: ori $3, $5, 255 - ; MM32: move $2, $4 - %r = or i64 255, %b ret i64 %r } define signext i128 @or_i128_255(i128 signext %b) { +; GP32-LABEL: or_i128_255: +; GP32: # %bb.0: # %entry +; GP32-NEXT: ori $1, $7, 255 +; GP32-NEXT: move $2, $4 +; GP32-NEXT: move $3, $5 +; GP32-NEXT: move $4, $6 +; GP32-NEXT: jr $ra +; GP32-NEXT: move $5, $1 +; +; GP64-LABEL: or_i128_255: +; GP64: # %bb.0: # %entry +; GP64-NEXT: ori $3, $5, 255 +; GP64-NEXT: jr $ra +; GP64-NEXT: move $2, $4 +; +; MM32-LABEL: or_i128_255: +; MM32: # %bb.0: # %entry +; MM32-NEXT: ori $1, $7, 255 +; MM32-NEXT: move $2, $4 +; MM32-NEXT: move $3, $5 +; MM32-NEXT: move $4, $6 +; MM32-NEXT: move $5, $1 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i128_255: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: ori $1, $7, 255 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: move $3, $5 +; MM32R6-NEXT: move $4, $6 +; MM32R6-NEXT: move $5, $1 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i128_255: - - ; GP32: ori $[[T0:[0-9]+]], $7, 255 - ; GP32: move $2, $4 - ; GP32: move $3, $5 - ; GP32: move $4, $6 - ; GP32: move $5, $[[T0]] - - ; GP64: ori $3, $5, 255 - ; GP64: move $2, $4 - - ; MM32: ori $[[T0:[0-9]+]], $7, 255 - ; MM32: move $2, $4 - ; MM32: move $3, $5 - ; MM32: move $4, $6 - ; MM32: move $5, $[[T0]] - %r = or i128 255, %b ret i128 %r } define signext i1 @or_i1_32768(i1 signext %b) { +; GP32-LABEL: or_i1_32768: +; GP32: # %bb.0: # %entry +; GP32-NEXT: jr $ra +; GP32-NEXT: move $2, $4 +; +; GP64-LABEL: or_i1_32768: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: move $2, $4 +; +; MM32-LABEL: or_i1_32768: +; MM32: # %bb.0: # %entry +; MM32-NEXT: move $2, $4 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i1_32768: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i1_32768: - - ; ALL: move $2, $4 - %r = or i1 32768, %b ret i1 %r } define signext i8 @or_i8_32768(i8 signext %b) { +; GP32-LABEL: or_i8_32768: +; GP32: # %bb.0: # %entry +; GP32-NEXT: jr $ra +; GP32-NEXT: move $2, $4 +; +; GP64-LABEL: or_i8_32768: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: move $2, $4 +; +; MM32-LABEL: or_i8_32768: +; MM32: # %bb.0: # %entry +; MM32-NEXT: move $2, $4 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i8_32768: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i8_32768: - - ; ALL: move $2, $4 - %r = or i8 32768, %b ret i8 %r } define signext i16 @or_i16_32768(i16 signext %b) { +; GP32-LABEL: or_i16_32768: +; GP32: # %bb.0: # %entry +; GP32-NEXT: addiu $1, $zero, -32768 +; GP32-NEXT: jr $ra +; GP32-NEXT: or $2, $4, $1 +; +; GP64-LABEL: or_i16_32768: +; GP64: # %bb.0: # %entry +; GP64-NEXT: addiu $1, $zero, -32768 +; GP64-NEXT: jr $ra +; GP64-NEXT: or $2, $4, $1 +; +; MM32-LABEL: or_i16_32768: +; MM32: # %bb.0: # %entry +; MM32-NEXT: addiu $2, $zero, -32768 +; MM32-NEXT: or16 $2, $4 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i16_32768: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: addiu $2, $zero, -32768 +; MM32R6-NEXT: or16 $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i16_32768: - - ; GP32: addiu $[[T0:[0-9]+]], $zero, -32768 - ; GP32: or $2, $4, $[[T0]] - - ; GP64: addiu $[[T0:[0-9]+]], $zero, -32768 - ; GP64: or $2, $4, $[[T0]] - - ; MM: addiu $2, $zero, -32768 - ; MM: or16 $2, $4 - %r = or i16 32768, %b ret i16 %r } define signext i32 @or_i32_32768(i32 signext %b) { +; GP32-LABEL: or_i32_32768: +; GP32: # %bb.0: # %entry +; GP32-NEXT: jr $ra +; GP32-NEXT: ori $2, $4, 32768 +; +; GP64-LABEL: or_i32_32768: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: ori $2, $4, 32768 +; +; MM32-LABEL: or_i32_32768: +; MM32: # %bb.0: # %entry +; MM32-NEXT: jr $ra +; MM32-NEXT: ori $2, $4, 32768 +; +; MM32R6-LABEL: or_i32_32768: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: ori $2, $4, 32768 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i32_32768: - - ; ALL: ori $2, $4, 32768 - %r = or i32 32768, %b ret i32 %r } define signext i64 @or_i64_32768(i64 signext %b) { +; GP32-LABEL: or_i64_32768: +; GP32: # %bb.0: # %entry +; GP32-NEXT: ori $3, $5, 32768 +; GP32-NEXT: jr $ra +; GP32-NEXT: move $2, $4 +; +; GP64-LABEL: or_i64_32768: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: ori $2, $4, 32768 +; +; MM32-LABEL: or_i64_32768: +; MM32: # %bb.0: # %entry +; MM32-NEXT: ori $3, $5, 32768 +; MM32-NEXT: move $2, $4 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i64_32768: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: ori $3, $5, 32768 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i64_32768: - - ; GP32: ori $3, $5, 32768 - ; GP32: move $2, $4 - - ; GP64: ori $2, $4, 32768 - - ; MM32: ori $3, $5, 32768 - ; MM32: move $2, $4 - %r = or i64 32768, %b ret i64 %r } define signext i128 @or_i128_32768(i128 signext %b) { +; GP32-LABEL: or_i128_32768: +; GP32: # %bb.0: # %entry +; GP32-NEXT: ori $1, $7, 32768 +; GP32-NEXT: move $2, $4 +; GP32-NEXT: move $3, $5 +; GP32-NEXT: move $4, $6 +; GP32-NEXT: jr $ra +; GP32-NEXT: move $5, $1 +; +; GP64-LABEL: or_i128_32768: +; GP64: # %bb.0: # %entry +; GP64-NEXT: ori $3, $5, 32768 +; GP64-NEXT: jr $ra +; GP64-NEXT: move $2, $4 +; +; MM32-LABEL: or_i128_32768: +; MM32: # %bb.0: # %entry +; MM32-NEXT: ori $1, $7, 32768 +; MM32-NEXT: move $2, $4 +; MM32-NEXT: move $3, $5 +; MM32-NEXT: move $4, $6 +; MM32-NEXT: move $5, $1 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i128_32768: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: ori $1, $7, 32768 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: move $3, $5 +; MM32R6-NEXT: move $4, $6 +; MM32R6-NEXT: move $5, $1 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i128_32768: - - ; GP32: ori $[[T0:[0-9]+]], $7, 32768 - ; GP32: move $2, $4 - ; GP32: move $3, $5 - ; GP32: move $4, $6 - ; GP32: move $5, $[[T0]] - - ; GP64: ori $3, $5, 32768 - ; GP64: move $2, $4 - - ; MM32: ori $[[T0:[0-9]+]], $7, 32768 - ; MM32: move $2, $4 - ; MM32: move $3, $5 - ; MM32: move $4, $6 - ; MM32: move $5, $[[T0]] - %r = or i128 32768, %b ret i128 %r } define signext i1 @or_i1_65(i1 signext %b) { +; GP32-LABEL: or_i1_65: +; GP32: # %bb.0: # %entry +; GP32-NEXT: jr $ra +; GP32-NEXT: addiu $2, $zero, -1 +; +; GP64-LABEL: or_i1_65: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: addiu $2, $zero, -1 +; +; MM32-LABEL: or_i1_65: +; MM32: # %bb.0: # %entry +; MM32-NEXT: li16 $2, -1 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i1_65: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: li16 $2, -1 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i1_65: - - ; GP32: addiu $2, $zero, -1 - - ; GP64: addiu $2, $zero, -1 - - ; MM: li16 $2, -1 - %r = or i1 65, %b ret i1 %r } define signext i8 @or_i8_65(i8 signext %b) { +; GP32-LABEL: or_i8_65: +; GP32: # %bb.0: # %entry +; GP32-NEXT: jr $ra +; GP32-NEXT: ori $2, $4, 65 +; +; GP64-LABEL: or_i8_65: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: ori $2, $4, 65 +; +; MM32-LABEL: or_i8_65: +; MM32: # %bb.0: # %entry +; MM32-NEXT: jr $ra +; MM32-NEXT: ori $2, $4, 65 +; +; MM32R6-LABEL: or_i8_65: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: ori $2, $4, 65 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i8_65: - - ; ALL: ori $2, $4, 65 - %r = or i8 65, %b ret i8 %r } define signext i16 @or_i16_65(i16 signext %b) { +; GP32-LABEL: or_i16_65: +; GP32: # %bb.0: # %entry +; GP32-NEXT: jr $ra +; GP32-NEXT: ori $2, $4, 65 +; +; GP64-LABEL: or_i16_65: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: ori $2, $4, 65 +; +; MM32-LABEL: or_i16_65: +; MM32: # %bb.0: # %entry +; MM32-NEXT: jr $ra +; MM32-NEXT: ori $2, $4, 65 +; +; MM32R6-LABEL: or_i16_65: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: ori $2, $4, 65 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i16_65: - - ; ALL: ori $2, $4, 65 - %r = or i16 65, %b ret i16 %r } define signext i32 @or_i32_65(i32 signext %b) { +; GP32-LABEL: or_i32_65: +; GP32: # %bb.0: # %entry +; GP32-NEXT: jr $ra +; GP32-NEXT: ori $2, $4, 65 +; +; GP64-LABEL: or_i32_65: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: ori $2, $4, 65 +; +; MM32-LABEL: or_i32_65: +; MM32: # %bb.0: # %entry +; MM32-NEXT: jr $ra +; MM32-NEXT: ori $2, $4, 65 +; +; MM32R6-LABEL: or_i32_65: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: ori $2, $4, 65 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i32_65: - - ; ALL: ori $2, $4, 65 - %r = or i32 65, %b ret i32 %r } define signext i64 @or_i64_65(i64 signext %b) { +; GP32-LABEL: or_i64_65: +; GP32: # %bb.0: # %entry +; GP32-NEXT: ori $3, $5, 65 +; GP32-NEXT: jr $ra +; GP32-NEXT: move $2, $4 +; +; GP64-LABEL: or_i64_65: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: ori $2, $4, 65 +; +; MM32-LABEL: or_i64_65: +; MM32: # %bb.0: # %entry +; MM32-NEXT: ori $3, $5, 65 +; MM32-NEXT: move $2, $4 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i64_65: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: ori $3, $5, 65 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i64_65: - - ; GP32: ori $3, $5, 65 - ; GP32: move $2, $4 - - ; GP64: ori $2, $4, 65 - - ; MM32: ori $3, $5, 65 - ; MM32: move $2, $4 - %r = or i64 65, %b ret i64 %r } define signext i128 @or_i128_65(i128 signext %b) { +; GP32-LABEL: or_i128_65: +; GP32: # %bb.0: # %entry +; GP32-NEXT: ori $1, $7, 65 +; GP32-NEXT: move $2, $4 +; GP32-NEXT: move $3, $5 +; GP32-NEXT: move $4, $6 +; GP32-NEXT: jr $ra +; GP32-NEXT: move $5, $1 +; +; GP64-LABEL: or_i128_65: +; GP64: # %bb.0: # %entry +; GP64-NEXT: ori $3, $5, 65 +; GP64-NEXT: jr $ra +; GP64-NEXT: move $2, $4 +; +; MM32-LABEL: or_i128_65: +; MM32: # %bb.0: # %entry +; MM32-NEXT: ori $1, $7, 65 +; MM32-NEXT: move $2, $4 +; MM32-NEXT: move $3, $5 +; MM32-NEXT: move $4, $6 +; MM32-NEXT: move $5, $1 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i128_65: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: ori $1, $7, 65 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: move $3, $5 +; MM32R6-NEXT: move $4, $6 +; MM32R6-NEXT: move $5, $1 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i128_65: - - ; GP32: ori $[[T0:[0-9]+]], $7, 65 - ; GP32: move $2, $4 - ; GP32: move $3, $5 - ; GP32: move $4, $6 - ; GP32: move $5, $[[T0]] - - ; GP64: ori $3, $5, 65 - ; GP64: move $2, $4 - - ; MM32: ori $[[T0:[0-9]+]], $7, 65 - ; MM32: move $2, $4 - ; MM32: move $3, $5 - ; MM32: move $4, $6 - ; MM32: move $5, $[[T0]] - %r = or i128 65, %b ret i128 %r } define signext i1 @or_i1_256(i1 signext %b) { +; GP32-LABEL: or_i1_256: +; GP32: # %bb.0: # %entry +; GP32-NEXT: jr $ra +; GP32-NEXT: move $2, $4 +; +; GP64-LABEL: or_i1_256: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: move $2, $4 +; +; MM32-LABEL: or_i1_256: +; MM32: # %bb.0: # %entry +; MM32-NEXT: move $2, $4 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i1_256: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i1_256: - - ; ALL: move $2, $4 - %r = or i1 256, %b ret i1 %r } define signext i8 @or_i8_256(i8 signext %b) { +; GP32-LABEL: or_i8_256: +; GP32: # %bb.0: # %entry +; GP32-NEXT: jr $ra +; GP32-NEXT: move $2, $4 +; +; GP64-LABEL: or_i8_256: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: move $2, $4 +; +; MM32-LABEL: or_i8_256: +; MM32: # %bb.0: # %entry +; MM32-NEXT: move $2, $4 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i8_256: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i8_256: - - ; ALL: move $2, $4 - %r = or i8 256, %b ret i8 %r } define signext i16 @or_i16_256(i16 signext %b) { +; GP32-LABEL: or_i16_256: +; GP32: # %bb.0: # %entry +; GP32-NEXT: jr $ra +; GP32-NEXT: ori $2, $4, 256 +; +; GP64-LABEL: or_i16_256: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: ori $2, $4, 256 +; +; MM32-LABEL: or_i16_256: +; MM32: # %bb.0: # %entry +; MM32-NEXT: jr $ra +; MM32-NEXT: ori $2, $4, 256 +; +; MM32R6-LABEL: or_i16_256: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: ori $2, $4, 256 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i16_256: - - ; ALL: ori $2, $4, 256 - %r = or i16 256, %b ret i16 %r } define signext i32 @or_i32_256(i32 signext %b) { +; GP32-LABEL: or_i32_256: +; GP32: # %bb.0: # %entry +; GP32-NEXT: jr $ra +; GP32-NEXT: ori $2, $4, 256 +; +; GP64-LABEL: or_i32_256: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: ori $2, $4, 256 +; +; MM32-LABEL: or_i32_256: +; MM32: # %bb.0: # %entry +; MM32-NEXT: jr $ra +; MM32-NEXT: ori $2, $4, 256 +; +; MM32R6-LABEL: or_i32_256: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: ori $2, $4, 256 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i32_256: - - ; ALL: ori $2, $4, 256 - %r = or i32 256, %b ret i32 %r } define signext i64 @or_i64_256(i64 signext %b) { +; GP32-LABEL: or_i64_256: +; GP32: # %bb.0: # %entry +; GP32-NEXT: ori $3, $5, 256 +; GP32-NEXT: jr $ra +; GP32-NEXT: move $2, $4 +; +; GP64-LABEL: or_i64_256: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: ori $2, $4, 256 +; +; MM32-LABEL: or_i64_256: +; MM32: # %bb.0: # %entry +; MM32-NEXT: ori $3, $5, 256 +; MM32-NEXT: move $2, $4 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i64_256: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: ori $3, $5, 256 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i64_256: - - ; GP32: ori $3, $5, 256 - ; GP32: move $2, $4 - - ; GP64: ori $2, $4, 256 - - ; MM32: ori $3, $5, 256 - ; MM32: move $2, $4 - %r = or i64 256, %b ret i64 %r } define signext i128 @or_i128_256(i128 signext %b) { +; GP32-LABEL: or_i128_256: +; GP32: # %bb.0: # %entry +; GP32-NEXT: ori $1, $7, 256 +; GP32-NEXT: move $2, $4 +; GP32-NEXT: move $3, $5 +; GP32-NEXT: move $4, $6 +; GP32-NEXT: jr $ra +; GP32-NEXT: move $5, $1 +; +; GP64-LABEL: or_i128_256: +; GP64: # %bb.0: # %entry +; GP64-NEXT: ori $3, $5, 256 +; GP64-NEXT: jr $ra +; GP64-NEXT: move $2, $4 +; +; MM32-LABEL: or_i128_256: +; MM32: # %bb.0: # %entry +; MM32-NEXT: ori $1, $7, 256 +; MM32-NEXT: move $2, $4 +; MM32-NEXT: move $3, $5 +; MM32-NEXT: move $4, $6 +; MM32-NEXT: move $5, $1 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i128_256: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: ori $1, $7, 256 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: move $3, $5 +; MM32R6-NEXT: move $4, $6 +; MM32R6-NEXT: move $5, $1 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i128_256: - - ; GP32: ori $[[T0:[0-9]+]], $7, 256 - ; GP32: move $2, $4 - ; GP32: move $3, $5 - ; GP32: move $4, $6 - ; GP32: move $5, $[[T0]] - - ; GP64: ori $3, $5, 256 - ; GP64: move $2, $4 - - ; MM32: ori $[[T0:[0-9]+]], $7, 256 - ; MM32: move $2, $4 - ; MM32: move $3, $5 - ; MM32: move $4, $6 - ; MM32: move $5, $[[T0]] - %r = or i128 256, %b ret i128 %r } diff --git a/test/CodeGen/Mips/llvm-ir/shl.ll b/test/CodeGen/Mips/llvm-ir/shl.ll index 13545907e21..6c764b8ad43 100644 --- a/test/CodeGen/Mips/llvm-ir/shl.ll +++ b/test/CodeGen/Mips/llvm-ir/shl.ll @@ -1,230 +1,1039 @@ -; RUN: llc < %s -march=mips -mcpu=mips2 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32,M2,NOT-R2-R6 -; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32,NOT-R2-R6,32R1-R5 -; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32,32R1-R5,R2-R6 -; RUN: llc < %s -march=mips -mcpu=mips32r3 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32,32R1-R5,R2-R6 -; RUN: llc < %s -march=mips -mcpu=mips32r5 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32,32R1-R5,R2-R6 -; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32,32R6,R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips3 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64,M3,NOT-R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips4 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6,NOT-R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6,NOT-R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6,R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6,R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6,R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64,64R6,R2-R6 -; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,MM,MMR3 -; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,MM,MMR6 +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS2 +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS32 +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS32R2 +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS32R2 +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r5 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS32R2 +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS32R6 +; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS3 +; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips4 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS4 +; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips64 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS64 +; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips64r2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS64R2 +; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips64r3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS64R2 +; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips64r5 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS64R2 +; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS64R6 +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MMR3 +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MMR6 define signext i1 @shl_i1(i1 signext %a, i1 signext %b) { +; MIPS2-LABEL: shl_i1: +; MIPS2: # %bb.0: # %entry +; MIPS2-NEXT: jr $ra +; MIPS2-NEXT: move $2, $4 +; +; MIPS32-LABEL: shl_i1: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: move $2, $4 +; +; MIPS32R2-LABEL: shl_i1: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: move $2, $4 +; +; MIPS32R6-LABEL: shl_i1: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: move $2, $4 +; +; MIPS3-LABEL: shl_i1: +; MIPS3: # %bb.0: # %entry +; MIPS3-NEXT: jr $ra +; MIPS3-NEXT: move $2, $4 +; +; MIPS4-LABEL: shl_i1: +; MIPS4: # %bb.0: # %entry +; MIPS4-NEXT: jr $ra +; MIPS4-NEXT: move $2, $4 +; +; MIPS64-LABEL: shl_i1: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: move $2, $4 +; +; MIPS64R2-LABEL: shl_i1: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: move $2, $4 +; +; MIPS64R6-LABEL: shl_i1: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: move $2, $4 +; +; MMR3-LABEL: shl_i1: +; MMR3: # %bb.0: # %entry +; MMR3-NEXT: move $2, $4 +; MMR3-NEXT: jrc $ra +; +; MMR6-LABEL: shl_i1: +; MMR6: # %bb.0: # %entry +; MMR6-NEXT: move $2, $4 +; MMR6-NEXT: jrc $ra entry: -; ALL-LABEL: shl_i1: - - ; ALL: move $2, $4 %r = shl i1 %a, %b ret i1 %r } define signext i8 @shl_i8(i8 signext %a, i8 signext %b) { +; MIPS2-LABEL: shl_i8: +; MIPS2: # %bb.0: # %entry +; MIPS2-NEXT: andi $1, $5, 255 +; MIPS2-NEXT: sllv $1, $4, $1 +; MIPS2-NEXT: sll $1, $1, 24 +; MIPS2-NEXT: jr $ra +; MIPS2-NEXT: sra $2, $1, 24 +; +; MIPS32-LABEL: shl_i8: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: andi $1, $5, 255 +; MIPS32-NEXT: sllv $1, $4, $1 +; MIPS32-NEXT: sll $1, $1, 24 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: sra $2, $1, 24 +; +; MIPS32R2-LABEL: shl_i8: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: andi $1, $5, 255 +; MIPS32R2-NEXT: sllv $1, $4, $1 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: seb $2, $1 +; +; MIPS32R6-LABEL: shl_i8: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: andi $1, $5, 255 +; MIPS32R6-NEXT: sllv $1, $4, $1 +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: seb $2, $1 +; +; MIPS3-LABEL: shl_i8: +; MIPS3: # %bb.0: # %entry +; MIPS3-NEXT: andi $1, $5, 255 +; MIPS3-NEXT: sllv $1, $4, $1 +; MIPS3-NEXT: sll $1, $1, 24 +; MIPS3-NEXT: jr $ra +; MIPS3-NEXT: sra $2, $1, 24 +; +; MIPS4-LABEL: shl_i8: +; MIPS4: # %bb.0: # %entry +; MIPS4-NEXT: andi $1, $5, 255 +; MIPS4-NEXT: sllv $1, $4, $1 +; MIPS4-NEXT: sll $1, $1, 24 +; MIPS4-NEXT: jr $ra +; MIPS4-NEXT: sra $2, $1, 24 +; +; MIPS64-LABEL: shl_i8: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: andi $1, $5, 255 +; MIPS64-NEXT: sllv $1, $4, $1 +; MIPS64-NEXT: sll $1, $1, 24 +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: sra $2, $1, 24 +; +; MIPS64R2-LABEL: shl_i8: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: andi $1, $5, 255 +; MIPS64R2-NEXT: sllv $1, $4, $1 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: seb $2, $1 +; +; MIPS64R6-LABEL: shl_i8: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: andi $1, $5, 255 +; MIPS64R6-NEXT: sllv $1, $4, $1 +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: seb $2, $1 +; +; MMR3-LABEL: shl_i8: +; MMR3: # %bb.0: # %entry +; MMR3-NEXT: andi16 $2, $5, 255 +; MMR3-NEXT: sllv $1, $4, $2 +; MMR3-NEXT: jr $ra +; MMR3-NEXT: seb $2, $1 +; +; MMR6-LABEL: shl_i8: +; MMR6: # %bb.0: # %entry +; MMR6-NEXT: andi16 $2, $5, 255 +; MMR6-NEXT: sllv $1, $4, $2 +; MMR6-NEXT: seb $2, $1 +; MMR6-NEXT: jrc $ra entry: -; ALL-LABEL: shl_i8: - - ; NOT-R2-R6: andi $[[T0:[0-9]+]], $5, 255 - ; NOT-R2-R6: sllv $[[T1:[0-9]+]], $4, $[[T0]] - ; NOT-R2-R6: sll $[[T2:[0-9]+]], $[[T1]], 24 - ; NOT-R2-R6: sra $2, $[[T2]], 24 - - ; R2-R6: andi $[[T0:[0-9]+]], $5, 255 - ; R2-R6: sllv $[[T1:[0-9]+]], $4, $[[T0]] - ; R2-R6: seb $2, $[[T1]] - - ; MM: andi16 $[[T0:[0-9]+]], $5, 255 - ; MM: sllv $[[T1:[0-9]+]], $4, $[[T0]] - ; MM: seb $2, $[[T1]] %r = shl i8 %a, %b ret i8 %r } define signext i16 @shl_i16(i16 signext %a, i16 signext %b) { +; MIPS2-LABEL: shl_i16: +; MIPS2: # %bb.0: # %entry +; MIPS2-NEXT: andi $1, $5, 65535 +; MIPS2-NEXT: sllv $1, $4, $1 +; MIPS2-NEXT: sll $1, $1, 16 +; MIPS2-NEXT: jr $ra +; MIPS2-NEXT: sra $2, $1, 16 +; +; MIPS32-LABEL: shl_i16: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: andi $1, $5, 65535 +; MIPS32-NEXT: sllv $1, $4, $1 +; MIPS32-NEXT: sll $1, $1, 16 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: sra $2, $1, 16 +; +; MIPS32R2-LABEL: shl_i16: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: andi $1, $5, 65535 +; MIPS32R2-NEXT: sllv $1, $4, $1 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: seh $2, $1 +; +; MIPS32R6-LABEL: shl_i16: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: andi $1, $5, 65535 +; MIPS32R6-NEXT: sllv $1, $4, $1 +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: seh $2, $1 +; +; MIPS3-LABEL: shl_i16: +; MIPS3: # %bb.0: # %entry +; MIPS3-NEXT: andi $1, $5, 65535 +; MIPS3-NEXT: sllv $1, $4, $1 +; MIPS3-NEXT: sll $1, $1, 16 +; MIPS3-NEXT: jr $ra +; MIPS3-NEXT: sra $2, $1, 16 +; +; MIPS4-LABEL: shl_i16: +; MIPS4: # %bb.0: # %entry +; MIPS4-NEXT: andi $1, $5, 65535 +; MIPS4-NEXT: sllv $1, $4, $1 +; MIPS4-NEXT: sll $1, $1, 16 +; MIPS4-NEXT: jr $ra +; MIPS4-NEXT: sra $2, $1, 16 +; +; MIPS64-LABEL: shl_i16: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: andi $1, $5, 65535 +; MIPS64-NEXT: sllv $1, $4, $1 +; MIPS64-NEXT: sll $1, $1, 16 +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: sra $2, $1, 16 +; +; MIPS64R2-LABEL: shl_i16: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: andi $1, $5, 65535 +; MIPS64R2-NEXT: sllv $1, $4, $1 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: seh $2, $1 +; +; MIPS64R6-LABEL: shl_i16: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: andi $1, $5, 65535 +; MIPS64R6-NEXT: sllv $1, $4, $1 +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: seh $2, $1 +; +; MMR3-LABEL: shl_i16: +; MMR3: # %bb.0: # %entry +; MMR3-NEXT: andi16 $2, $5, 65535 +; MMR3-NEXT: sllv $1, $4, $2 +; MMR3-NEXT: jr $ra +; MMR3-NEXT: seh $2, $1 +; +; MMR6-LABEL: shl_i16: +; MMR6: # %bb.0: # %entry +; MMR6-NEXT: andi16 $2, $5, 65535 +; MMR6-NEXT: sllv $1, $4, $2 +; MMR6-NEXT: seh $2, $1 +; MMR6-NEXT: jrc $ra entry: -; ALL-LABEL: shl_i16: - - ; NOT-R2-R6: andi $[[T0:[0-9]+]], $5, 65535 - ; NOT-R2-R6: sllv $[[T1:[0-9]+]], $4, $[[T0]] - ; NOT-R2-R6: sll $[[T2:[0-9]+]], $[[T1]], 16 - ; NOT-R2-R6: sra $2, $[[T2]], 16 - - ; R2-R6: andi $[[T0:[0-9]+]], $5, 65535 - ; R2-R6: sllv $[[T1:[0-9]+]], $4, $[[T0]] - ; R2-R6: seh $2, $[[T1]] - - ; MM: andi16 $[[T0:[0-9]+]], $5, 65535 - ; MM: sllv $[[T1:[0-9]+]], $4, $[[T0]] - ; MM: seh $2, $[[T1]] %r = shl i16 %a, %b ret i16 %r } define signext i32 @shl_i32(i32 signext %a, i32 signext %b) { +; MIPS2-LABEL: shl_i32: +; MIPS2: # %bb.0: # %entry +; MIPS2-NEXT: jr $ra +; MIPS2-NEXT: sllv $2, $4, $5 +; +; MIPS32-LABEL: shl_i32: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: sllv $2, $4, $5 +; +; MIPS32R2-LABEL: shl_i32: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: sllv $2, $4, $5 +; +; MIPS32R6-LABEL: shl_i32: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: sllv $2, $4, $5 +; +; MIPS3-LABEL: shl_i32: +; MIPS3: # %bb.0: # %entry +; MIPS3-NEXT: jr $ra +; MIPS3-NEXT: sllv $2, $4, $5 +; +; MIPS4-LABEL: shl_i32: +; MIPS4: # %bb.0: # %entry +; MIPS4-NEXT: jr $ra +; MIPS4-NEXT: sllv $2, $4, $5 +; +; MIPS64-LABEL: shl_i32: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: sllv $2, $4, $5 +; +; MIPS64R2-LABEL: shl_i32: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: sllv $2, $4, $5 +; +; MIPS64R6-LABEL: shl_i32: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: sllv $2, $4, $5 +; +; MMR3-LABEL: shl_i32: +; MMR3: # %bb.0: # %entry +; MMR3-NEXT: jr $ra +; MMR3-NEXT: sllv $2, $4, $5 +; +; MMR6-LABEL: shl_i32: +; MMR6: # %bb.0: # %entry +; MMR6-NEXT: sllv $2, $4, $5 +; MMR6-NEXT: jrc $ra entry: -; ALL-LABEL: shl_i32: - - ; ALL: sllv $2, $4, $5 %r = shl i32 %a, %b ret i32 %r } define signext i64 @shl_i64(i64 signext %a, i64 signext %b) { +; MIPS2-LABEL: shl_i64: +; MIPS2: # %bb.0: # %entry +; MIPS2-NEXT: sllv $6, $5, $7 +; MIPS2-NEXT: andi $8, $7, 32 +; MIPS2-NEXT: beqz $8, $BB4_3 +; MIPS2-NEXT: move $2, $6 +; MIPS2-NEXT: # %bb.1: # %entry +; MIPS2-NEXT: beqz $8, $BB4_4 +; MIPS2-NEXT: addiu $3, $zero, 0 +; MIPS2-NEXT: $BB4_2: # %entry +; MIPS2-NEXT: jr $ra +; MIPS2-NEXT: nop +; MIPS2-NEXT: $BB4_3: # %entry +; MIPS2-NEXT: sllv $1, $4, $7 +; MIPS2-NEXT: not $2, $7 +; MIPS2-NEXT: srl $3, $5, 1 +; MIPS2-NEXT: srlv $2, $3, $2 +; MIPS2-NEXT: or $2, $1, $2 +; MIPS2-NEXT: bnez $8, $BB4_2 +; MIPS2-NEXT: addiu $3, $zero, 0 +; MIPS2-NEXT: $BB4_4: # %entry +; MIPS2-NEXT: jr $ra +; MIPS2-NEXT: move $3, $6 +; +; MIPS32-LABEL: shl_i64: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: sllv $1, $4, $7 +; MIPS32-NEXT: not $2, $7 +; MIPS32-NEXT: srl $3, $5, 1 +; MIPS32-NEXT: srlv $2, $3, $2 +; MIPS32-NEXT: or $2, $1, $2 +; MIPS32-NEXT: sllv $3, $5, $7 +; MIPS32-NEXT: andi $1, $7, 32 +; MIPS32-NEXT: movn $2, $3, $1 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: movn $3, $zero, $1 +; +; MIPS32R2-LABEL: shl_i64: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: sllv $1, $4, $7 +; MIPS32R2-NEXT: not $2, $7 +; MIPS32R2-NEXT: srl $3, $5, 1 +; MIPS32R2-NEXT: srlv $2, $3, $2 +; MIPS32R2-NEXT: or $2, $1, $2 +; MIPS32R2-NEXT: sllv $3, $5, $7 +; MIPS32R2-NEXT: andi $1, $7, 32 +; MIPS32R2-NEXT: movn $2, $3, $1 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: movn $3, $zero, $1 +; +; MIPS32R6-LABEL: shl_i64: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: sllv $1, $4, $7 +; MIPS32R6-NEXT: not $2, $7 +; MIPS32R6-NEXT: srl $3, $5, 1 +; MIPS32R6-NEXT: srlv $2, $3, $2 +; MIPS32R6-NEXT: or $1, $1, $2 +; MIPS32R6-NEXT: andi $3, $7, 32 +; MIPS32R6-NEXT: seleqz $1, $1, $3 +; MIPS32R6-NEXT: sllv $4, $5, $7 +; MIPS32R6-NEXT: selnez $2, $4, $3 +; MIPS32R6-NEXT: or $2, $2, $1 +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: seleqz $3, $4, $3 +; +; MIPS3-LABEL: shl_i64: +; MIPS3: # %bb.0: # %entry +; MIPS3-NEXT: jr $ra +; MIPS3-NEXT: dsllv $2, $4, $5 +; +; MIPS4-LABEL: shl_i64: +; MIPS4: # %bb.0: # %entry +; MIPS4-NEXT: jr $ra +; MIPS4-NEXT: dsllv $2, $4, $5 +; +; MIPS64-LABEL: shl_i64: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: dsllv $2, $4, $5 +; +; MIPS64R2-LABEL: shl_i64: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: dsllv $2, $4, $5 +; +; MIPS64R6-LABEL: shl_i64: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: dsllv $2, $4, $5 +; +; MMR3-LABEL: shl_i64: +; MMR3: # %bb.0: # %entry +; MMR3-NEXT: sllv $3, $4, $7 +; MMR3-NEXT: not16 $2, $7 +; MMR3-NEXT: srl16 $4, $5, 1 +; MMR3-NEXT: srlv $2, $4, $2 +; MMR3-NEXT: or16 $2, $3 +; MMR3-NEXT: sllv $3, $5, $7 +; MMR3-NEXT: andi16 $4, $7, 32 +; MMR3-NEXT: movn $2, $3, $4 +; MMR3-NEXT: li16 $5, 0 +; MMR3-NEXT: jr $ra +; MMR3-NEXT: movn $3, $5, $4 +; +; MMR6-LABEL: shl_i64: +; MMR6: # %bb.0: # %entry +; MMR6-NEXT: sllv $2, $4, $7 +; MMR6-NEXT: not16 $3, $7 +; MMR6-NEXT: srl16 $4, $5, 1 +; MMR6-NEXT: srlv $3, $4, $3 +; MMR6-NEXT: or16 $3, $2 +; MMR6-NEXT: andi16 $4, $7, 32 +; MMR6-NEXT: seleqz $1, $3, $4 +; MMR6-NEXT: sllv $3, $5, $7 +; MMR6-NEXT: selnez $2, $3, $4 +; MMR6-NEXT: or $2, $2, $1 +; MMR6-NEXT: seleqz $3, $3, $4 +; MMR6-NEXT: jrc $ra entry: -; ALL-LABEL: shl_i64: - - ; M2: sllv $[[T0:[0-9]+]], $5, $7 - ; M2: andi $[[T1:[0-9]+]], $7, 32 - ; M2: beqz $[[T1]], $[[BB0:BB[0-9_]+]] - ; M2: move $2, $[[T0]] - ; M2: beqz $[[T1]], $[[BB1:BB[0-9_]+]] - ; M2: addiu $3, $zero, 0 - ; M2: $[[EXIT:BB[0-9_]+]]: - ; M2: jr $ra - ; M2: nop - ; M2: $[[BB0]]: - ; M2: sllv $[[T2:[0-9]+]], $4, $7 - ; M2: not $[[T3:[0-9]+]], $7 - ; M2: srl $[[T4:[0-9]+]], $5, 1 - ; M2: srlv $[[T5:[0-9]+]], $[[T4]], $[[T3]] - ; M2: or $2, $[[T2]], $[[T3]] - ; M2: bnez $[[T1]], $[[EXIT]] - ; M2: addiu $3, $zero, 0 - ; M2: $[[BB1]]: - ; M2: jr $ra - ; M2: move $3, $[[T0]] - - ; 32R1-R5: sllv $[[T0:[0-9]+]], $4, $7 - ; 32R1-R5: not $[[T1:[0-9]+]], $7 - ; 32R1-R5: srl $[[T2:[0-9]+]], $5, 1 - ; 32R1-R5: srlv $[[T3:[0-9]+]], $[[T2]], $[[T1]] - ; 32R1-R5: or $2, $[[T0]], $[[T3]] - ; 32R1-R5: sllv $[[T4:[0-9]+]], $5, $7 - ; 32R1-R5: andi $[[T5:[0-9]+]], $7, 32 - ; 32R1-R5: movn $2, $[[T4]], $[[T5]] - ; 32R1-R5: jr $ra - ; 32R1-R5: movn $3, $zero, $[[T5]] - - ; 32R6: sllv $[[T0:[0-9]+]], $4, $7 - ; 32R6: not $[[T1:[0-9]+]], $7 - ; 32R6: srl $[[T2:[0-9]+]], $5, 1 - ; 32R6: srlv $[[T3:[0-9]+]], $[[T2]], $[[T1]] - ; 32R6: or $[[T4:[0-9]+]], $[[T0]], $[[T3]] - ; 32R6: andi $[[T5:[0-9]+]], $7, 32 - ; 32R6: seleqz $[[T6:[0-9]+]], $[[T4]], $[[T2]] - ; 32R6: sllv $[[T7:[0-9]+]], $5, $7 - ; 32R6: selnez $[[T8:[0-9]+]], $[[T7]], $[[T5]] - ; 32R6: or $2, $[[T8]], $[[T6]] - ; 32R6: jr $ra - ; 32R6: seleqz $3, $[[T7]], $[[T5]] - - ; GP64: dsllv $2, $4, $5 - - ; MMR3: sllv $[[T0:[0-9]+]], $4, $7 - ; MMR3: not16 $[[T1:[0-9]+]], $7 - ; MMR3: srl16 $[[T2:[0-9]+]], $5, 1 - ; MMR3: srlv $[[T3:[0-9]+]], $[[T2]], $[[T1]] - ; MMR3: or16 $[[T4:[0-9]+]], $[[T0]] - ; MMR3: sllv $[[T5:[0-9]+]], $5, $7 - ; MMR3: andi16 $[[T6:[0-9]+]], $7, 32 - ; MMR3: movn $[[T7:[0-9]+]], $[[T5]], $[[T6]] - ; MMR3: li16 $[[T8:[0-9]+]], 0 - ; MMR3: movn $3, $[[T8]], $[[T6]] - - ; MMR6: sllv $[[T0:[0-9]+]], $4, $7 - ; MMR6: not16 $[[T1:[0-9]+]], $7 - ; MMR6: srl16 $[[T2:[0-9]+]], $5, 1 - ; MMR6: srlv $[[T3:[0-9]+]], $[[T2]], $[[T1]] - ; MMR6: or16 $[[T4:[0-9]+]], $[[T0]] - ; MMR6: andi16 $[[T5:[0-9]+]], $7, 32 - ; MMR6: seleqz $[[T6:[0-9]+]], $[[T4]], $[[T5]] - ; MMR6: sllv $[[T7:[0-9]+]], $5, $7 - ; MMR6: selnez $[[T8:[0-9]+]], $[[T7]], $[[T5]] - ; MMR6: or $2, $[[T8]], $[[T6]] - ; MMR6: seleqz $3, $[[T7]], $[[T5]] %r = shl i64 %a, %b ret i64 %r } define signext i128 @shl_i128(i128 signext %a, i128 signext %b) { +; MIPS2-LABEL: shl_i128: +; MIPS2: # %bb.0: # %entry +; MIPS2-NEXT: addiu $sp, $sp, -8 +; MIPS2-NEXT: .cfi_def_cfa_offset 8 +; MIPS2-NEXT: sw $17, 4($sp) # 4-byte Folded Spill +; MIPS2-NEXT: sw $16, 0($sp) # 4-byte Folded Spill +; MIPS2-NEXT: .cfi_offset 17, -4 +; MIPS2-NEXT: .cfi_offset 16, -8 +; MIPS2-NEXT: lw $8, 36($sp) +; MIPS2-NEXT: addiu $1, $zero, 64 +; MIPS2-NEXT: subu $10, $1, $8 +; MIPS2-NEXT: srlv $3, $6, $10 +; MIPS2-NEXT: andi $13, $10, 32 +; MIPS2-NEXT: addiu $2, $zero, 0 +; MIPS2-NEXT: bnez $13, $BB5_2 +; MIPS2-NEXT: addiu $25, $zero, 0 +; MIPS2-NEXT: # %bb.1: # %entry +; MIPS2-NEXT: move $25, $3 +; MIPS2-NEXT: $BB5_2: # %entry +; MIPS2-NEXT: not $9, $8 +; MIPS2-NEXT: sllv $11, $5, $8 +; MIPS2-NEXT: andi $12, $8, 32 +; MIPS2-NEXT: bnez $12, $BB5_4 +; MIPS2-NEXT: move $16, $11 +; MIPS2-NEXT: # %bb.3: # %entry +; MIPS2-NEXT: sllv $1, $4, $8 +; MIPS2-NEXT: srl $14, $5, 1 +; MIPS2-NEXT: srlv $14, $14, $9 +; MIPS2-NEXT: or $16, $1, $14 +; MIPS2-NEXT: $BB5_4: # %entry +; MIPS2-NEXT: addiu $24, $8, -64 +; MIPS2-NEXT: srl $17, $7, 1 +; MIPS2-NEXT: sllv $14, $7, $24 +; MIPS2-NEXT: andi $15, $24, 32 +; MIPS2-NEXT: bnez $15, $BB5_6 +; MIPS2-NEXT: move $gp, $14 +; MIPS2-NEXT: # %bb.5: # %entry +; MIPS2-NEXT: sllv $1, $6, $24 +; MIPS2-NEXT: not $24, $24 +; MIPS2-NEXT: srlv $24, $17, $24 +; MIPS2-NEXT: or $gp, $1, $24 +; MIPS2-NEXT: $BB5_6: # %entry +; MIPS2-NEXT: sltiu $24, $8, 64 +; MIPS2-NEXT: beqz $24, $BB5_8 +; MIPS2-NEXT: nop +; MIPS2-NEXT: # %bb.7: +; MIPS2-NEXT: or $gp, $16, $25 +; MIPS2-NEXT: $BB5_8: # %entry +; MIPS2-NEXT: sllv $25, $7, $8 +; MIPS2-NEXT: bnez $12, $BB5_10 +; MIPS2-NEXT: move $16, $25 +; MIPS2-NEXT: # %bb.9: # %entry +; MIPS2-NEXT: sllv $1, $6, $8 +; MIPS2-NEXT: srlv $9, $17, $9 +; MIPS2-NEXT: or $16, $1, $9 +; MIPS2-NEXT: $BB5_10: # %entry +; MIPS2-NEXT: bnez $12, $BB5_12 +; MIPS2-NEXT: addiu $9, $zero, 0 +; MIPS2-NEXT: # %bb.11: # %entry +; MIPS2-NEXT: move $9, $25 +; MIPS2-NEXT: $BB5_12: # %entry +; MIPS2-NEXT: addiu $1, $zero, 63 +; MIPS2-NEXT: sltiu $25, $8, 1 +; MIPS2-NEXT: beqz $25, $BB5_22 +; MIPS2-NEXT: sltu $17, $1, $8 +; MIPS2-NEXT: # %bb.13: # %entry +; MIPS2-NEXT: beqz $17, $BB5_23 +; MIPS2-NEXT: addiu $8, $zero, 0 +; MIPS2-NEXT: $BB5_14: # %entry +; MIPS2-NEXT: beqz $17, $BB5_24 +; MIPS2-NEXT: addiu $9, $zero, 0 +; MIPS2-NEXT: $BB5_15: # %entry +; MIPS2-NEXT: beqz $13, $BB5_25 +; MIPS2-NEXT: nop +; MIPS2-NEXT: $BB5_16: # %entry +; MIPS2-NEXT: beqz $12, $BB5_26 +; MIPS2-NEXT: addiu $6, $zero, 0 +; MIPS2-NEXT: $BB5_17: # %entry +; MIPS2-NEXT: beqz $15, $BB5_27 +; MIPS2-NEXT: nop +; MIPS2-NEXT: $BB5_18: # %entry +; MIPS2-NEXT: bnez $24, $BB5_28 +; MIPS2-NEXT: nop +; MIPS2-NEXT: $BB5_19: # %entry +; MIPS2-NEXT: bnez $25, $BB5_21 +; MIPS2-NEXT: nop +; MIPS2-NEXT: $BB5_20: # %entry +; MIPS2-NEXT: move $5, $2 +; MIPS2-NEXT: $BB5_21: # %entry +; MIPS2-NEXT: move $2, $4 +; MIPS2-NEXT: move $3, $5 +; MIPS2-NEXT: move $4, $9 +; MIPS2-NEXT: move $5, $8 +; MIPS2-NEXT: lw $16, 0($sp) # 4-byte Folded Reload +; MIPS2-NEXT: lw $17, 4($sp) # 4-byte Folded Reload +; MIPS2-NEXT: jr $ra +; MIPS2-NEXT: addiu $sp, $sp, 8 +; MIPS2-NEXT: $BB5_22: # %entry +; MIPS2-NEXT: move $4, $gp +; MIPS2-NEXT: bnez $17, $BB5_14 +; MIPS2-NEXT: addiu $8, $zero, 0 +; MIPS2-NEXT: $BB5_23: # %entry +; MIPS2-NEXT: move $8, $9 +; MIPS2-NEXT: bnez $17, $BB5_15 +; MIPS2-NEXT: addiu $9, $zero, 0 +; MIPS2-NEXT: $BB5_24: # %entry +; MIPS2-NEXT: bnez $13, $BB5_16 +; MIPS2-NEXT: move $9, $16 +; MIPS2-NEXT: $BB5_25: # %entry +; MIPS2-NEXT: not $1, $10 +; MIPS2-NEXT: sll $3, $6, 1 +; MIPS2-NEXT: srlv $6, $7, $10 +; MIPS2-NEXT: sllv $1, $3, $1 +; MIPS2-NEXT: or $3, $1, $6 +; MIPS2-NEXT: bnez $12, $BB5_17 +; MIPS2-NEXT: addiu $6, $zero, 0 +; MIPS2-NEXT: $BB5_26: # %entry +; MIPS2-NEXT: bnez $15, $BB5_18 +; MIPS2-NEXT: move $6, $11 +; MIPS2-NEXT: $BB5_27: # %entry +; MIPS2-NEXT: beqz $24, $BB5_19 +; MIPS2-NEXT: move $2, $14 +; MIPS2-NEXT: $BB5_28: +; MIPS2-NEXT: bnez $25, $BB5_21 +; MIPS2-NEXT: or $2, $6, $3 +; MIPS2-NEXT: # %bb.29: +; MIPS2-NEXT: b $BB5_20 +; MIPS2-NEXT: nop +; +; MIPS32-LABEL: shl_i128: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: lw $8, 28($sp) +; MIPS32-NEXT: addiu $1, $zero, 64 +; MIPS32-NEXT: subu $1, $1, $8 +; MIPS32-NEXT: srlv $9, $6, $1 +; MIPS32-NEXT: andi $10, $1, 32 +; MIPS32-NEXT: move $2, $9 +; MIPS32-NEXT: movn $2, $zero, $10 +; MIPS32-NEXT: sllv $3, $4, $8 +; MIPS32-NEXT: not $11, $8 +; MIPS32-NEXT: srl $12, $5, 1 +; MIPS32-NEXT: srlv $12, $12, $11 +; MIPS32-NEXT: or $3, $3, $12 +; MIPS32-NEXT: sllv $12, $5, $8 +; MIPS32-NEXT: andi $13, $8, 32 +; MIPS32-NEXT: movn $3, $12, $13 +; MIPS32-NEXT: addiu $14, $8, -64 +; MIPS32-NEXT: or $15, $3, $2 +; MIPS32-NEXT: sllv $2, $6, $14 +; MIPS32-NEXT: srl $24, $7, 1 +; MIPS32-NEXT: not $3, $14 +; MIPS32-NEXT: srlv $3, $24, $3 +; MIPS32-NEXT: or $2, $2, $3 +; MIPS32-NEXT: sllv $3, $7, $14 +; MIPS32-NEXT: andi $14, $14, 32 +; MIPS32-NEXT: movn $2, $3, $14 +; MIPS32-NEXT: sltiu $25, $8, 64 +; MIPS32-NEXT: movn $2, $15, $25 +; MIPS32-NEXT: srlv $15, $7, $1 +; MIPS32-NEXT: not $1, $1 +; MIPS32-NEXT: sll $gp, $6, 1 +; MIPS32-NEXT: sllv $1, $gp, $1 +; MIPS32-NEXT: or $15, $1, $15 +; MIPS32-NEXT: sllv $1, $6, $8 +; MIPS32-NEXT: srlv $6, $24, $11 +; MIPS32-NEXT: or $1, $1, $6 +; MIPS32-NEXT: sllv $6, $7, $8 +; MIPS32-NEXT: movn $1, $6, $13 +; MIPS32-NEXT: movz $2, $4, $8 +; MIPS32-NEXT: movz $1, $zero, $25 +; MIPS32-NEXT: movn $15, $9, $10 +; MIPS32-NEXT: movn $12, $zero, $13 +; MIPS32-NEXT: or $4, $12, $15 +; MIPS32-NEXT: movn $3, $zero, $14 +; MIPS32-NEXT: movn $3, $4, $25 +; MIPS32-NEXT: movz $3, $5, $8 +; MIPS32-NEXT: movn $6, $zero, $13 +; MIPS32-NEXT: movz $6, $zero, $25 +; MIPS32-NEXT: move $4, $1 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: move $5, $6 +; +; MIPS32R2-LABEL: shl_i128: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: lw $8, 28($sp) +; MIPS32R2-NEXT: addiu $1, $zero, 64 +; MIPS32R2-NEXT: subu $1, $1, $8 +; MIPS32R2-NEXT: srlv $9, $6, $1 +; MIPS32R2-NEXT: andi $10, $1, 32 +; MIPS32R2-NEXT: move $2, $9 +; MIPS32R2-NEXT: movn $2, $zero, $10 +; MIPS32R2-NEXT: sllv $3, $4, $8 +; MIPS32R2-NEXT: not $11, $8 +; MIPS32R2-NEXT: srl $12, $5, 1 +; MIPS32R2-NEXT: srlv $12, $12, $11 +; MIPS32R2-NEXT: or $3, $3, $12 +; MIPS32R2-NEXT: sllv $12, $5, $8 +; MIPS32R2-NEXT: andi $13, $8, 32 +; MIPS32R2-NEXT: movn $3, $12, $13 +; MIPS32R2-NEXT: addiu $14, $8, -64 +; MIPS32R2-NEXT: or $15, $3, $2 +; MIPS32R2-NEXT: sllv $2, $6, $14 +; MIPS32R2-NEXT: srl $24, $7, 1 +; MIPS32R2-NEXT: not $3, $14 +; MIPS32R2-NEXT: srlv $3, $24, $3 +; MIPS32R2-NEXT: or $2, $2, $3 +; MIPS32R2-NEXT: sllv $3, $7, $14 +; MIPS32R2-NEXT: andi $14, $14, 32 +; MIPS32R2-NEXT: movn $2, $3, $14 +; MIPS32R2-NEXT: sltiu $25, $8, 64 +; MIPS32R2-NEXT: movn $2, $15, $25 +; MIPS32R2-NEXT: srlv $15, $7, $1 +; MIPS32R2-NEXT: not $1, $1 +; MIPS32R2-NEXT: sll $gp, $6, 1 +; MIPS32R2-NEXT: sllv $1, $gp, $1 +; MIPS32R2-NEXT: or $15, $1, $15 +; MIPS32R2-NEXT: sllv $1, $6, $8 +; MIPS32R2-NEXT: srlv $6, $24, $11 +; MIPS32R2-NEXT: or $1, $1, $6 +; MIPS32R2-NEXT: sllv $6, $7, $8 +; MIPS32R2-NEXT: movn $1, $6, $13 +; MIPS32R2-NEXT: movz $2, $4, $8 +; MIPS32R2-NEXT: movz $1, $zero, $25 +; MIPS32R2-NEXT: movn $15, $9, $10 +; MIPS32R2-NEXT: movn $12, $zero, $13 +; MIPS32R2-NEXT: or $4, $12, $15 +; MIPS32R2-NEXT: movn $3, $zero, $14 +; MIPS32R2-NEXT: movn $3, $4, $25 +; MIPS32R2-NEXT: movz $3, $5, $8 +; MIPS32R2-NEXT: movn $6, $zero, $13 +; MIPS32R2-NEXT: movz $6, $zero, $25 +; MIPS32R2-NEXT: move $4, $1 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: move $5, $6 +; +; MIPS32R6-LABEL: shl_i128: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: lw $3, 28($sp) +; MIPS32R6-NEXT: sllv $1, $4, $3 +; MIPS32R6-NEXT: not $2, $3 +; MIPS32R6-NEXT: srl $8, $5, 1 +; MIPS32R6-NEXT: srlv $8, $8, $2 +; MIPS32R6-NEXT: or $1, $1, $8 +; MIPS32R6-NEXT: sllv $8, $5, $3 +; MIPS32R6-NEXT: andi $9, $3, 32 +; MIPS32R6-NEXT: seleqz $1, $1, $9 +; MIPS32R6-NEXT: selnez $10, $8, $9 +; MIPS32R6-NEXT: addiu $11, $zero, 64 +; MIPS32R6-NEXT: subu $11, $11, $3 +; MIPS32R6-NEXT: srlv $12, $6, $11 +; MIPS32R6-NEXT: andi $13, $11, 32 +; MIPS32R6-NEXT: seleqz $14, $12, $13 +; MIPS32R6-NEXT: or $1, $10, $1 +; MIPS32R6-NEXT: selnez $10, $12, $13 +; MIPS32R6-NEXT: srlv $12, $7, $11 +; MIPS32R6-NEXT: not $11, $11 +; MIPS32R6-NEXT: sll $15, $6, 1 +; MIPS32R6-NEXT: sllv $11, $15, $11 +; MIPS32R6-NEXT: or $11, $11, $12 +; MIPS32R6-NEXT: seleqz $11, $11, $13 +; MIPS32R6-NEXT: addiu $12, $3, -64 +; MIPS32R6-NEXT: or $10, $10, $11 +; MIPS32R6-NEXT: or $1, $1, $14 +; MIPS32R6-NEXT: sllv $11, $6, $12 +; MIPS32R6-NEXT: srl $13, $7, 1 +; MIPS32R6-NEXT: not $14, $12 +; MIPS32R6-NEXT: srlv $14, $13, $14 +; MIPS32R6-NEXT: or $11, $11, $14 +; MIPS32R6-NEXT: andi $14, $12, 32 +; MIPS32R6-NEXT: seleqz $11, $11, $14 +; MIPS32R6-NEXT: sllv $12, $7, $12 +; MIPS32R6-NEXT: selnez $15, $12, $14 +; MIPS32R6-NEXT: sltiu $24, $3, 64 +; MIPS32R6-NEXT: selnez $1, $1, $24 +; MIPS32R6-NEXT: or $11, $15, $11 +; MIPS32R6-NEXT: sllv $6, $6, $3 +; MIPS32R6-NEXT: srlv $2, $13, $2 +; MIPS32R6-NEXT: seleqz $8, $8, $9 +; MIPS32R6-NEXT: or $8, $8, $10 +; MIPS32R6-NEXT: or $6, $6, $2 +; MIPS32R6-NEXT: seleqz $2, $11, $24 +; MIPS32R6-NEXT: seleqz $10, $zero, $24 +; MIPS32R6-NEXT: sllv $7, $7, $3 +; MIPS32R6-NEXT: seleqz $11, $7, $9 +; MIPS32R6-NEXT: selnez $11, $11, $24 +; MIPS32R6-NEXT: seleqz $4, $4, $3 +; MIPS32R6-NEXT: or $1, $1, $2 +; MIPS32R6-NEXT: selnez $1, $1, $3 +; MIPS32R6-NEXT: or $2, $4, $1 +; MIPS32R6-NEXT: or $1, $10, $11 +; MIPS32R6-NEXT: seleqz $4, $6, $9 +; MIPS32R6-NEXT: selnez $6, $7, $9 +; MIPS32R6-NEXT: seleqz $5, $5, $3 +; MIPS32R6-NEXT: selnez $7, $8, $24 +; MIPS32R6-NEXT: seleqz $8, $12, $14 +; MIPS32R6-NEXT: seleqz $8, $8, $24 +; MIPS32R6-NEXT: or $7, $7, $8 +; MIPS32R6-NEXT: selnez $3, $7, $3 +; MIPS32R6-NEXT: or $3, $5, $3 +; MIPS32R6-NEXT: or $4, $6, $4 +; MIPS32R6-NEXT: selnez $4, $4, $24 +; MIPS32R6-NEXT: or $4, $10, $4 +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: move $5, $1 +; +; MIPS3-LABEL: shl_i128: +; MIPS3: # %bb.0: # %entry +; MIPS3-NEXT: sll $3, $7, 0 +; MIPS3-NEXT: dsllv $6, $5, $7 +; MIPS3-NEXT: andi $8, $3, 64 +; MIPS3-NEXT: beqz $8, .LBB5_3 +; MIPS3-NEXT: move $2, $6 +; MIPS3-NEXT: # %bb.1: # %entry +; MIPS3-NEXT: beqz $8, .LBB5_4 +; MIPS3-NEXT: daddiu $3, $zero, 0 +; MIPS3-NEXT: .LBB5_2: # %entry +; MIPS3-NEXT: jr $ra +; MIPS3-NEXT: nop +; MIPS3-NEXT: .LBB5_3: # %entry +; MIPS3-NEXT: dsllv $1, $4, $7 +; MIPS3-NEXT: dsrl $2, $5, 1 +; MIPS3-NEXT: not $3, $3 +; MIPS3-NEXT: dsrlv $2, $2, $3 +; MIPS3-NEXT: or $2, $1, $2 +; MIPS3-NEXT: bnez $8, .LBB5_2 +; MIPS3-NEXT: daddiu $3, $zero, 0 +; MIPS3-NEXT: .LBB5_4: # %entry +; MIPS3-NEXT: jr $ra +; MIPS3-NEXT: move $3, $6 +; +; MIPS4-LABEL: shl_i128: +; MIPS4: # %bb.0: # %entry +; MIPS4-NEXT: dsllv $1, $4, $7 +; MIPS4-NEXT: dsrl $2, $5, 1 +; MIPS4-NEXT: sll $4, $7, 0 +; MIPS4-NEXT: not $3, $4 +; MIPS4-NEXT: dsrlv $2, $2, $3 +; MIPS4-NEXT: or $2, $1, $2 +; MIPS4-NEXT: dsllv $3, $5, $7 +; MIPS4-NEXT: andi $1, $4, 64 +; MIPS4-NEXT: movn $2, $3, $1 +; MIPS4-NEXT: jr $ra +; MIPS4-NEXT: movn $3, $zero, $1 +; +; MIPS64-LABEL: shl_i128: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: dsllv $1, $4, $7 +; MIPS64-NEXT: dsrl $2, $5, 1 +; MIPS64-NEXT: sll $4, $7, 0 +; MIPS64-NEXT: not $3, $4 +; MIPS64-NEXT: dsrlv $2, $2, $3 +; MIPS64-NEXT: or $2, $1, $2 +; MIPS64-NEXT: dsllv $3, $5, $7 +; MIPS64-NEXT: andi $1, $4, 64 +; MIPS64-NEXT: movn $2, $3, $1 +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: movn $3, $zero, $1 +; +; MIPS64R2-LABEL: shl_i128: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: dsllv $1, $4, $7 +; MIPS64R2-NEXT: dsrl $2, $5, 1 +; MIPS64R2-NEXT: sll $4, $7, 0 +; MIPS64R2-NEXT: not $3, $4 +; MIPS64R2-NEXT: dsrlv $2, $2, $3 +; MIPS64R2-NEXT: or $2, $1, $2 +; MIPS64R2-NEXT: dsllv $3, $5, $7 +; MIPS64R2-NEXT: andi $1, $4, 64 +; MIPS64R2-NEXT: movn $2, $3, $1 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: movn $3, $zero, $1 +; +; MIPS64R6-LABEL: shl_i128: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: dsllv $1, $4, $7 +; MIPS64R6-NEXT: dsrl $2, $5, 1 +; MIPS64R6-NEXT: sll $3, $7, 0 +; MIPS64R6-NEXT: not $4, $3 +; MIPS64R6-NEXT: dsrlv $2, $2, $4 +; MIPS64R6-NEXT: or $1, $1, $2 +; MIPS64R6-NEXT: andi $2, $3, 64 +; MIPS64R6-NEXT: sll $3, $2, 0 +; MIPS64R6-NEXT: seleqz $1, $1, $3 +; MIPS64R6-NEXT: dsllv $4, $5, $7 +; MIPS64R6-NEXT: selnez $2, $4, $3 +; MIPS64R6-NEXT: or $2, $2, $1 +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: seleqz $3, $4, $3 +; +; MMR3-LABEL: shl_i128: +; MMR3: # %bb.0: # %entry +; MMR3-NEXT: addiusp -48 +; MMR3-NEXT: .cfi_def_cfa_offset 48 +; MMR3-NEXT: sw $17, 44($sp) # 4-byte Folded Spill +; MMR3-NEXT: sw $16, 40($sp) # 4-byte Folded Spill +; MMR3-NEXT: .cfi_offset 17, -4 +; MMR3-NEXT: .cfi_offset 16, -8 +; MMR3-NEXT: sw $7, 8($sp) # 4-byte Folded Spill +; MMR3-NEXT: sw $6, 36($sp) # 4-byte Folded Spill +; MMR3-NEXT: move $17, $6 +; MMR3-NEXT: sw $5, 32($sp) # 4-byte Folded Spill +; MMR3-NEXT: move $1, $4 +; MMR3-NEXT: lw $16, 76($sp) +; MMR3-NEXT: sllv $2, $1, $16 +; MMR3-NEXT: not16 $4, $16 +; MMR3-NEXT: sw $4, 24($sp) # 4-byte Folded Spill +; MMR3-NEXT: srl16 $3, $5, 1 +; MMR3-NEXT: srlv $4, $3, $4 +; MMR3-NEXT: li16 $3, 64 +; MMR3-NEXT: or16 $4, $2 +; MMR3-NEXT: sllv $6, $5, $16 +; MMR3-NEXT: sw $6, 20($sp) # 4-byte Folded Spill +; MMR3-NEXT: subu16 $7, $3, $16 +; MMR3-NEXT: srlv $9, $17, $7 +; MMR3-NEXT: andi16 $2, $7, 32 +; MMR3-NEXT: sw $2, 28($sp) # 4-byte Folded Spill +; MMR3-NEXT: andi16 $3, $16, 32 +; MMR3-NEXT: sw $3, 12($sp) # 4-byte Folded Spill +; MMR3-NEXT: move $5, $9 +; MMR3-NEXT: li16 $17, 0 +; MMR3-NEXT: movn $5, $17, $2 +; MMR3-NEXT: movn $4, $6, $3 +; MMR3-NEXT: addiu $2, $16, -64 +; MMR3-NEXT: lw $3, 36($sp) # 4-byte Folded Reload +; MMR3-NEXT: sllv $3, $3, $2 +; MMR3-NEXT: sw $3, 16($sp) # 4-byte Folded Spill +; MMR3-NEXT: lw $17, 8($sp) # 4-byte Folded Reload +; MMR3-NEXT: srl16 $6, $17, 1 +; MMR3-NEXT: sw $6, 4($sp) # 4-byte Folded Spill +; MMR3-NEXT: not16 $3, $2 +; MMR3-NEXT: srlv $3, $6, $3 +; MMR3-NEXT: or16 $4, $5 +; MMR3-NEXT: lw $5, 16($sp) # 4-byte Folded Reload +; MMR3-NEXT: or16 $3, $5 +; MMR3-NEXT: sllv $8, $17, $2 +; MMR3-NEXT: andi16 $2, $2, 32 +; MMR3-NEXT: sw $2, 16($sp) # 4-byte Folded Spill +; MMR3-NEXT: movn $3, $8, $2 +; MMR3-NEXT: srlv $2, $17, $7 +; MMR3-NEXT: not16 $5, $7 +; MMR3-NEXT: lw $7, 36($sp) # 4-byte Folded Reload +; MMR3-NEXT: sll16 $6, $7, 1 +; MMR3-NEXT: sllv $5, $6, $5 +; MMR3-NEXT: sltiu $10, $16, 64 +; MMR3-NEXT: movn $3, $4, $10 +; MMR3-NEXT: or16 $5, $2 +; MMR3-NEXT: sllv $2, $7, $16 +; MMR3-NEXT: lw $4, 24($sp) # 4-byte Folded Reload +; MMR3-NEXT: lw $6, 4($sp) # 4-byte Folded Reload +; MMR3-NEXT: srlv $4, $6, $4 +; MMR3-NEXT: or16 $4, $2 +; MMR3-NEXT: sllv $6, $17, $16 +; MMR3-NEXT: lw $2, 12($sp) # 4-byte Folded Reload +; MMR3-NEXT: movn $4, $6, $2 +; MMR3-NEXT: sltiu $11, $16, 64 +; MMR3-NEXT: movz $3, $1, $16 +; MMR3-NEXT: li16 $7, 0 +; MMR3-NEXT: movz $4, $7, $11 +; MMR3-NEXT: lw $17, 28($sp) # 4-byte Folded Reload +; MMR3-NEXT: movn $5, $9, $17 +; MMR3-NEXT: lw $7, 20($sp) # 4-byte Folded Reload +; MMR3-NEXT: li16 $17, 0 +; MMR3-NEXT: movn $7, $17, $2 +; MMR3-NEXT: or16 $7, $5 +; MMR3-NEXT: lw $5, 16($sp) # 4-byte Folded Reload +; MMR3-NEXT: movn $8, $17, $5 +; MMR3-NEXT: li16 $17, 0 +; MMR3-NEXT: movn $8, $7, $10 +; MMR3-NEXT: lw $5, 32($sp) # 4-byte Folded Reload +; MMR3-NEXT: movz $8, $5, $16 +; MMR3-NEXT: movn $6, $17, $2 +; MMR3-NEXT: li16 $5, 0 +; MMR3-NEXT: movz $6, $5, $11 +; MMR3-NEXT: move $2, $3 +; MMR3-NEXT: move $3, $8 +; MMR3-NEXT: move $5, $6 +; MMR3-NEXT: lw $16, 40($sp) # 4-byte Folded Reload +; MMR3-NEXT: lw $17, 44($sp) # 4-byte Folded Reload +; MMR3-NEXT: addiusp 48 +; MMR3-NEXT: jrc $ra +; +; MMR6-LABEL: shl_i128: +; MMR6: # %bb.0: # %entry +; MMR6-NEXT: addiu $sp, $sp, -32 +; MMR6-NEXT: .cfi_def_cfa_offset 32 +; MMR6-NEXT: sw $17, 28($sp) # 4-byte Folded Spill +; MMR6-NEXT: sw $16, 24($sp) # 4-byte Folded Spill +; MMR6-NEXT: .cfi_offset 17, -4 +; MMR6-NEXT: .cfi_offset 16, -8 +; MMR6-NEXT: sw $6, 4($sp) # 4-byte Folded Spill +; MMR6-NEXT: move $1, $4 +; MMR6-NEXT: lw $3, 60($sp) +; MMR6-NEXT: sllv $2, $1, $3 +; MMR6-NEXT: not16 $4, $3 +; MMR6-NEXT: sw $4, 16($sp) # 4-byte Folded Spill +; MMR6-NEXT: sw $5, 20($sp) # 4-byte Folded Spill +; MMR6-NEXT: srl16 $16, $5, 1 +; MMR6-NEXT: srlv $17, $16, $4 +; MMR6-NEXT: or16 $17, $2 +; MMR6-NEXT: sllv $8, $5, $3 +; MMR6-NEXT: andi16 $16, $3, 32 +; MMR6-NEXT: seleqz $4, $17, $16 +; MMR6-NEXT: selnez $9, $8, $16 +; MMR6-NEXT: li16 $17, 64 +; MMR6-NEXT: subu16 $17, $17, $3 +; MMR6-NEXT: srlv $10, $6, $17 +; MMR6-NEXT: andi16 $2, $17, 32 +; MMR6-NEXT: seleqz $5, $10, $2 +; MMR6-NEXT: sw $5, 8($sp) # 4-byte Folded Spill +; MMR6-NEXT: or $4, $9, $4 +; MMR6-NEXT: selnez $9, $10, $2 +; MMR6-NEXT: srlv $5, $7, $17 +; MMR6-NEXT: sw $5, 12($sp) # 4-byte Folded Spill +; MMR6-NEXT: not16 $17, $17 +; MMR6-NEXT: sll16 $5, $6, 1 +; MMR6-NEXT: sllv $5, $5, $17 +; MMR6-NEXT: lw $17, 12($sp) # 4-byte Folded Reload +; MMR6-NEXT: or16 $5, $17 +; MMR6-NEXT: seleqz $2, $5, $2 +; MMR6-NEXT: addiu $5, $3, -64 +; MMR6-NEXT: or $2, $9, $2 +; MMR6-NEXT: sw $2, 12($sp) # 4-byte Folded Spill +; MMR6-NEXT: lw $2, 8($sp) # 4-byte Folded Reload +; MMR6-NEXT: or16 $4, $2 +; MMR6-NEXT: sllv $2, $6, $5 +; MMR6-NEXT: sw $2, 8($sp) # 4-byte Folded Spill +; MMR6-NEXT: srl16 $6, $7, 1 +; MMR6-NEXT: not16 $17, $5 +; MMR6-NEXT: srlv $2, $6, $17 +; MMR6-NEXT: lw $17, 8($sp) # 4-byte Folded Reload +; MMR6-NEXT: or16 $2, $17 +; MMR6-NEXT: andi16 $17, $5, 32 +; MMR6-NEXT: seleqz $2, $2, $17 +; MMR6-NEXT: sllv $12, $7, $5 +; MMR6-NEXT: selnez $9, $12, $17 +; MMR6-NEXT: sltiu $10, $3, 64 +; MMR6-NEXT: selnez $11, $4, $10 +; MMR6-NEXT: or $9, $9, $2 +; MMR6-NEXT: lw $2, 4($sp) # 4-byte Folded Reload +; MMR6-NEXT: sllv $5, $2, $3 +; MMR6-NEXT: lw $4, 16($sp) # 4-byte Folded Reload +; MMR6-NEXT: srlv $6, $6, $4 +; MMR6-NEXT: seleqz $4, $8, $16 +; MMR6-NEXT: lw $2, 12($sp) # 4-byte Folded Reload +; MMR6-NEXT: or16 $4, $2 +; MMR6-NEXT: or16 $6, $5 +; MMR6-NEXT: seleqz $2, $9, $10 +; MMR6-NEXT: li16 $5, 0 +; MMR6-NEXT: seleqz $5, $5, $10 +; MMR6-NEXT: sllv $7, $7, $3 +; MMR6-NEXT: seleqz $8, $7, $16 +; MMR6-NEXT: selnez $8, $8, $10 +; MMR6-NEXT: seleqz $1, $1, $3 +; MMR6-NEXT: or $2, $11, $2 +; MMR6-NEXT: selnez $2, $2, $3 +; MMR6-NEXT: or $2, $1, $2 +; MMR6-NEXT: or $1, $5, $8 +; MMR6-NEXT: seleqz $6, $6, $16 +; MMR6-NEXT: selnez $7, $7, $16 +; MMR6-NEXT: lw $16, 20($sp) # 4-byte Folded Reload +; MMR6-NEXT: seleqz $8, $16, $3 +; MMR6-NEXT: selnez $4, $4, $10 +; MMR6-NEXT: seleqz $9, $12, $17 +; MMR6-NEXT: seleqz $9, $9, $10 +; MMR6-NEXT: or $4, $4, $9 +; MMR6-NEXT: selnez $3, $4, $3 +; MMR6-NEXT: or $3, $8, $3 +; MMR6-NEXT: or $4, $7, $6 +; MMR6-NEXT: selnez $4, $4, $10 +; MMR6-NEXT: or $4, $5, $4 +; MMR6-NEXT: move $5, $1 +; MMR6-NEXT: lw $16, 24($sp) # 4-byte Folded Reload +; MMR6-NEXT: lw $17, 28($sp) # 4-byte Folded Reload +; MMR6-NEXT: addiu $sp, $sp, 32 +; MMR6-NEXT: jrc $ra entry: -; ALL-LABEL: shl_i128: - - ; o32 shouldn't use TImode helpers. - ; GP32-NOT: lw $25, %call16(__ashlti3)($gp) - ; MM-NOT: lw $25, %call16(__ashlti3)($2) - - ; M3: sll $[[T0:[0-9]+]], $7, 0 - ; M3: dsllv $[[T1:[0-9]+]], $5, $7 - ; M3: andi $[[T2:[0-9]+]], $[[T0]], 64 - ; M3: beqz $[[T3:[0-9]+]], [[BB0:\.LBB[0-9_]+]] - ; M3: move $2, $[[T1]] - ; M3: beqz $[[T3]], [[BB1:\.LBB[0-9_]+]] - ; M3: daddiu $3, $zero, 0 - ; M3: [[EXIT:\.LBB[0-9_]+]]: - ; M3: jr $ra - ; M3: nop - ; M3: [[BB0]]: - ; M3: dsllv $[[T4:[0-9]+]], $4, $7 - ; M3: dsrl $[[T5:[0-9]+]], $5, 1 - ; M3: not $[[T6:[0-9]+]], $[[T0]] - ; M3: dsrlv $[[T7:[0-9]+]], $[[T5]], $[[T6]] - ; M3: or $2, $[[T4]], $[[T7]] - ; M3: bnez $[[T3]], [[EXIT]] - ; M3: daddiu $3, $zero, 0 - ; M3: [[BB1]]: - ; M3: jr $ra - ; M3: move $3, $[[T1]] - - ; GP64-NOT-R6: dsllv $[[T0:[0-9]+]], $4, $7 - ; GP64-NOT-R6: dsrl $[[T1:[0-9]+]], $5, 1 - ; GP64-NOT-R6: sll $[[T2:[0-9]+]], $7, 0 - ; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T2]] - ; GP64-NOT-R6: dsrlv $[[T4:[0-9]+]], $[[T1]], $[[T3]] - ; GP64-NOT-R6: or $2, $[[T0]], $[[T4]] - ; GP64-NOT-R6: dsllv $3, $5, $7 - ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T2]], 64 - ; GP64-NOT-R6: movn $2, $3, $[[T5]] - ; GP64-NOT-R6: jr $ra - ; GP64-NOT-R6: movn $3, $zero, $1 - ; 64R6: dsllv $[[T0:[0-9]+]], $4, $7 - ; 64R6: dsrl $[[T1:[0-9]+]], $5, 1 - ; 64R6: sll $[[T2:[0-9]+]], $7, 0 - ; 64R6: not $[[T3:[0-9]+]], $[[T2]] - ; 64R6: dsrlv $[[T4:[0-9]+]], $[[T1]], $[[T3]] - ; 64R6: or $[[T5:[0-9]+]], $[[T0]], $[[T4]] - ; 64R6: andi $[[T6:[0-9]+]], $[[T2]], 64 - ; 64R6: sll $[[T7:[0-9]+]], $[[T6]], 0 - ; 64R6: seleqz $[[T8:[0-9]+]], $[[T5]], $[[T7]] - ; 64R6: dsllv $[[T9:[0-9]+]], $5, $7 - ; 64R6: selnez $[[T10:[0-9]+]], $[[T9]], $[[T7]] - ; 64R6: or $2, $[[T10]], $[[T8]] - ; 64R6: jr $ra - ; 64R6: seleqz $3, $[[T9]], $[[T7]] +; o32 shouldn't use TImode helpers. +; GP32-NOT: lw $25, %call16(__ashlti3)($gp) +; MM-NOT: lw $25, %call16(__ashlti3)($2) %r = shl i128 %a, %b ret i128 %r diff --git a/test/CodeGen/Mips/llvm-ir/xor.ll b/test/CodeGen/Mips/llvm-ir/xor.ll index 8fcf11feace..1fb51876608 100644 --- a/test/CodeGen/Mips/llvm-ir/xor.ll +++ b/test/CodeGen/Mips/llvm-ir/xor.ll @@ -1,215 +1,664 @@ -; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefixes=ALL,GP32 -; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s -check-prefixes=ALL,GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32 -; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64 -; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64 -; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64 -; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \ -; RUN: -check-prefixes=ALL,MM,MM32 -; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ -; RUN: -check-prefixes=ALL,MM,MM32 +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips2 | FileCheck %s -check-prefix=MIPS +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32 | FileCheck %s -check-prefix=MIPS +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r2 | FileCheck %s \ +; RUN: -check-prefix=MIPS32R2 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 | FileCheck %s \ +; RUN: -check-prefix=MIPS32R2 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r5 | FileCheck %s \ +; RUN: -check-prefix=MIPS32R2 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 | FileCheck %s \ +; RUN: -check-prefix=MIPS32R6 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips3 | FileCheck %s \ +; RUN: -check-prefix=MIPS64 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips4 | FileCheck %s \ +; RUN: -check-prefix=MIPS64 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64 | FileCheck %s \ +; RUN: -check-prefix=MIPS64 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r2 | FileCheck %s \ +; RUN: -check-prefix=MIPS64R2 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r3 | FileCheck %s \ +; RUN: -check-prefix=MIPS64R2 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r5 | FileCheck %s \ +; RUN: -check-prefix=MIPS64R2 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r6 | FileCheck %s \ +; RUN: -check-prefix=MIPS64R6 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefix=MM32R3 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefix=MM32R6 define signext i1 @xor_i1(i1 signext %a, i1 signext %b) { +; MIPS-LABEL: xor_i1: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: xor $2, $4, $5 +; +; MIPS32R2-LABEL: xor_i1: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: xor $2, $4, $5 +; +; MIPS32R6-LABEL: xor_i1: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: xor $2, $4, $5 +; +; MIPS64-LABEL: xor_i1: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: xor $1, $4, $5 +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: sll $2, $1, 0 +; +; MIPS64R2-LABEL: xor_i1: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: xor $1, $4, $5 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: sll $2, $1, 0 +; +; MIPS64R6-LABEL: xor_i1: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: xor $1, $4, $5 +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: sll $2, $1, 0 +; +; MM32R3-LABEL: xor_i1: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: xor16 $4, $5 +; MM32R3-NEXT: move $2, $4 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: xor_i1: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: xor16 $4, $5 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: xor_i1: - - ; GP32: xor $2, $4, $5 - - ; GP64: xor $1, $4, $5 - - ; MM32: xor16 $[[T0:[0-9]+]], $5 - ; MM32: move $2, $[[T0]] - %r = xor i1 %a, %b ret i1 %r } define signext i8 @xor_i8(i8 signext %a, i8 signext %b) { +; MIPS-LABEL: xor_i8: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: xor $2, $4, $5 +; +; MIPS32R2-LABEL: xor_i8: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: xor $2, $4, $5 +; +; MIPS32R6-LABEL: xor_i8: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: xor $2, $4, $5 +; +; MIPS64-LABEL: xor_i8: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: xor $1, $4, $5 +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: sll $2, $1, 0 +; +; MIPS64R2-LABEL: xor_i8: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: xor $1, $4, $5 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: sll $2, $1, 0 +; +; MIPS64R6-LABEL: xor_i8: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: xor $1, $4, $5 +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: sll $2, $1, 0 +; +; MM32R3-LABEL: xor_i8: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: xor16 $4, $5 +; MM32R3-NEXT: move $2, $4 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: xor_i8: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: xor16 $4, $5 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: xor_i8: - - ; GP32: xor $2, $4, $5 - - ; GP64: xor $1, $4, $5 - - ; MM32: xor16 $[[T0:[0-9]+]], $5 - ; MM32: move $2, $[[T0]] - %r = xor i8 %a, %b ret i8 %r } define signext i16 @xor_i16(i16 signext %a, i16 signext %b) { +; MIPS-LABEL: xor_i16: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: xor $2, $4, $5 +; +; MIPS32R2-LABEL: xor_i16: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: xor $2, $4, $5 +; +; MIPS32R6-LABEL: xor_i16: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: xor $2, $4, $5 +; +; MIPS64-LABEL: xor_i16: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: xor $1, $4, $5 +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: sll $2, $1, 0 +; +; MIPS64R2-LABEL: xor_i16: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: xor $1, $4, $5 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: sll $2, $1, 0 +; +; MIPS64R6-LABEL: xor_i16: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: xor $1, $4, $5 +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: sll $2, $1, 0 +; +; MM32R3-LABEL: xor_i16: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: xor16 $4, $5 +; MM32R3-NEXT: move $2, $4 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: xor_i16: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: xor16 $4, $5 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: xor_i16: - - ; GP32: xor $2, $4, $5 - - ; GP64: xor $1, $4, $5 - - ; MM32: xor16 $[[T0:[0-9]+]], $5 - ; MM32: move $2, $[[T0]] - %r = xor i16 %a, %b ret i16 %r } define signext i32 @xor_i32(i32 signext %a, i32 signext %b) { +; MIPS-LABEL: xor_i32: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: xor $2, $4, $5 +; +; MIPS32R2-LABEL: xor_i32: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: xor $2, $4, $5 +; +; MIPS32R6-LABEL: xor_i32: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: xor $2, $4, $5 +; +; MIPS64-LABEL: xor_i32: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: xor $1, $4, $5 +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: sll $2, $1, 0 +; +; MIPS64R2-LABEL: xor_i32: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: xor $1, $4, $5 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: sll $2, $1, 0 +; +; MIPS64R6-LABEL: xor_i32: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: xor $1, $4, $5 +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: sll $2, $1, 0 +; +; MM32R3-LABEL: xor_i32: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: xor16 $4, $5 +; MM32R3-NEXT: move $2, $4 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: xor_i32: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: xor16 $4, $5 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: xor_i32: - - ; GP32: xor $2, $4, $5 - - ; GP64: xor $[[T0:[0-9]+]], $4, $5 - ; GP64: sll $2, $[[T0]], 0 - - ; MM32: xor16 $[[T0:[0-9]+]], $5 - ; MM32: move $2, $[[T0]] - %r = xor i32 %a, %b ret i32 %r } define signext i64 @xor_i64(i64 signext %a, i64 signext %b) { +; MIPS-LABEL: xor_i64: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: xor $2, $4, $6 +; MIPS-NEXT: jr $ra +; MIPS-NEXT: xor $3, $5, $7 +; +; MIPS32R2-LABEL: xor_i64: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: xor $2, $4, $6 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: xor $3, $5, $7 +; +; MIPS32R6-LABEL: xor_i64: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: xor $2, $4, $6 +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: xor $3, $5, $7 +; +; MIPS64-LABEL: xor_i64: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: xor $2, $4, $5 +; +; MIPS64R2-LABEL: xor_i64: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: xor $2, $4, $5 +; +; MIPS64R6-LABEL: xor_i64: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: xor $2, $4, $5 +; +; MM32R3-LABEL: xor_i64: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: xor16 $4, $6 +; MM32R3-NEXT: xor16 $5, $7 +; MM32R3-NEXT: move $2, $4 +; MM32R3-NEXT: move $3, $5 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: xor_i64: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: xor16 $4, $6 +; MM32R6-NEXT: xor16 $5, $7 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: move $3, $5 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: xor_i64: - - ; GP32: xor $2, $4, $6 - ; GP32: xor $3, $5, $7 - - ; GP64: xor $2, $4, $5 - - ; MM32: xor16 $[[T0:[0-9]+]], $6 - ; MM32: xor16 $[[T1:[0-9]+]], $7 - ; MM32: move $2, $[[T0]] - ; MM32: move $3, $[[T1]] - %r = xor i64 %a, %b ret i64 %r } define signext i128 @xor_i128(i128 signext %a, i128 signext %b) { +; MIPS-LABEL: xor_i128: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: lw $1, 20($sp) +; MIPS-NEXT: lw $2, 16($sp) +; MIPS-NEXT: xor $2, $4, $2 +; MIPS-NEXT: xor $3, $5, $1 +; MIPS-NEXT: lw $1, 24($sp) +; MIPS-NEXT: xor $4, $6, $1 +; MIPS-NEXT: lw $1, 28($sp) +; MIPS-NEXT: jr $ra +; MIPS-NEXT: xor $5, $7, $1 +; +; MIPS32R2-LABEL: xor_i128: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: lw $1, 20($sp) +; MIPS32R2-NEXT: lw $2, 16($sp) +; MIPS32R2-NEXT: xor $2, $4, $2 +; MIPS32R2-NEXT: xor $3, $5, $1 +; MIPS32R2-NEXT: lw $1, 24($sp) +; MIPS32R2-NEXT: xor $4, $6, $1 +; MIPS32R2-NEXT: lw $1, 28($sp) +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: xor $5, $7, $1 +; +; MIPS32R6-LABEL: xor_i128: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: lw $1, 20($sp) +; MIPS32R6-NEXT: lw $2, 16($sp) +; MIPS32R6-NEXT: xor $2, $4, $2 +; MIPS32R6-NEXT: xor $3, $5, $1 +; MIPS32R6-NEXT: lw $1, 24($sp) +; MIPS32R6-NEXT: xor $4, $6, $1 +; MIPS32R6-NEXT: lw $1, 28($sp) +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: xor $5, $7, $1 +; +; MIPS64-LABEL: xor_i128: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: xor $2, $4, $6 +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: xor $3, $5, $7 +; +; MIPS64R2-LABEL: xor_i128: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: xor $2, $4, $6 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: xor $3, $5, $7 +; +; MIPS64R6-LABEL: xor_i128: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: xor $2, $4, $6 +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: xor $3, $5, $7 +; +; MM32R3-LABEL: xor_i128: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: lw $3, 20($sp) +; MM32R3-NEXT: lw $2, 16($sp) +; MM32R3-NEXT: xor16 $2, $4 +; MM32R3-NEXT: xor16 $3, $5 +; MM32R3-NEXT: lw $4, 24($sp) +; MM32R3-NEXT: xor16 $4, $6 +; MM32R3-NEXT: lw $5, 28($sp) +; MM32R3-NEXT: xor16 $5, $7 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: xor_i128: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: lw $3, 20($sp) +; MM32R6-NEXT: lw $2, 16($sp) +; MM32R6-NEXT: xor16 $2, $4 +; MM32R6-NEXT: xor16 $3, $5 +; MM32R6-NEXT: lw $4, 24($sp) +; MM32R6-NEXT: xor16 $4, $6 +; MM32R6-NEXT: lw $5, 28($sp) +; MM32R6-NEXT: xor16 $5, $7 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: xor_i128: - - ; GP32: lw $[[T1:[0-9]+]], 20($sp) - ; GP32: lw $[[T2:[0-9]+]], 16($sp) - ; GP32: xor $2, $4, $[[T2]] - ; GP32: xor $3, $5, $[[T1]] - ; GP32: lw $[[T0:[0-9]+]], 24($sp) - ; GP32: xor $4, $6, $[[T0]] - ; GP32: lw $[[T3:[0-9]+]], 28($sp) - ; GP32: xor $5, $7, $[[T3]] - - ; GP64: xor $2, $4, $6 - ; GP64: xor $3, $5, $7 - - ; MM32: lw $[[T1:[0-9]+]], 20($sp) - ; MM32: lw $[[T2:[0-9]+]], 16($sp) - ; MM32: xor16 $[[T2]], $4 - ; MM32: xor16 $[[T1]], $5 - ; MM32: lw $[[T0:[0-9]+]], 24($sp) - ; MM32: xor16 $[[T0]], $6 - ; MM32: lw $[[T3:[0-9]+]], 28($sp) - ; MM32: xor16 $[[T3]], $7 - %r = xor i128 %a, %b ret i128 %r } define signext i1 @xor_i1_4(i1 signext %b) { +; MIPS-LABEL: xor_i1_4: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: move $2, $4 +; +; MIPS32R2-LABEL: xor_i1_4: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: move $2, $4 +; +; MIPS32R6-LABEL: xor_i1_4: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: move $2, $4 +; +; MIPS64-LABEL: xor_i1_4: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: move $2, $4 +; +; MIPS64R2-LABEL: xor_i1_4: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: move $2, $4 +; +; MIPS64R6-LABEL: xor_i1_4: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: move $2, $4 +; +; MM32R3-LABEL: xor_i1_4: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: move $2, $4 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: xor_i1_4: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: xor_i1_4: - - ; ALL: move $2, $4 - %r = xor i1 4, %b ret i1 %r } define signext i8 @xor_i8_4(i8 signext %b) { +; MIPS-LABEL: xor_i8_4: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: xori $2, $4, 4 +; +; MIPS32R2-LABEL: xor_i8_4: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: xori $2, $4, 4 +; +; MIPS32R6-LABEL: xor_i8_4: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: xori $2, $4, 4 +; +; MIPS64-LABEL: xor_i8_4: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: xori $2, $4, 4 +; +; MIPS64R2-LABEL: xor_i8_4: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: xori $2, $4, 4 +; +; MIPS64R6-LABEL: xor_i8_4: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: xori $2, $4, 4 +; +; MM32R3-LABEL: xor_i8_4: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: jr $ra +; MM32R3-NEXT: xori $2, $4, 4 +; +; MM32R6-LABEL: xor_i8_4: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: xori $2, $4, 4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: xor_i8_4: - - ; ALL: xori $2, $4, 4 - %r = xor i8 4, %b ret i8 %r } define signext i16 @xor_i16_4(i16 signext %b) { +; MIPS-LABEL: xor_i16_4: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: xori $2, $4, 4 +; +; MIPS32R2-LABEL: xor_i16_4: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: xori $2, $4, 4 +; +; MIPS32R6-LABEL: xor_i16_4: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: xori $2, $4, 4 +; +; MIPS64-LABEL: xor_i16_4: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: xori $2, $4, 4 +; +; MIPS64R2-LABEL: xor_i16_4: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: xori $2, $4, 4 +; +; MIPS64R6-LABEL: xor_i16_4: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: xori $2, $4, 4 +; +; MM32R3-LABEL: xor_i16_4: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: jr $ra +; MM32R3-NEXT: xori $2, $4, 4 +; +; MM32R6-LABEL: xor_i16_4: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: xori $2, $4, 4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: xor_i16_4: - - ; ALL: xori $2, $4, 4 - %r = xor i16 4, %b ret i16 %r } define signext i32 @xor_i32_4(i32 signext %b) { +; MIPS-LABEL: xor_i32_4: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: xori $2, $4, 4 +; +; MIPS32R2-LABEL: xor_i32_4: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: xori $2, $4, 4 +; +; MIPS32R6-LABEL: xor_i32_4: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: xori $2, $4, 4 +; +; MIPS64-LABEL: xor_i32_4: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: xori $2, $4, 4 +; +; MIPS64R2-LABEL: xor_i32_4: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: xori $2, $4, 4 +; +; MIPS64R6-LABEL: xor_i32_4: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: xori $2, $4, 4 +; +; MM32R3-LABEL: xor_i32_4: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: jr $ra +; MM32R3-NEXT: xori $2, $4, 4 +; +; MM32R6-LABEL: xor_i32_4: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: xori $2, $4, 4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: xor_i32_4: - - ; ALL: xori $2, $4, 4 - %r = xor i32 4, %b ret i32 %r } define signext i64 @xor_i64_4(i64 signext %b) { +; MIPS-LABEL: xor_i64_4: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: xori $3, $5, 4 +; MIPS-NEXT: jr $ra +; MIPS-NEXT: move $2, $4 +; +; MIPS32R2-LABEL: xor_i64_4: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: xori $3, $5, 4 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: move $2, $4 +; +; MIPS32R6-LABEL: xor_i64_4: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: xori $3, $5, 4 +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: move $2, $4 +; +; MIPS64-LABEL: xor_i64_4: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: xori $2, $4, 4 +; +; MIPS64R2-LABEL: xor_i64_4: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: xori $2, $4, 4 +; +; MIPS64R6-LABEL: xor_i64_4: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: xori $2, $4, 4 +; +; MM32R3-LABEL: xor_i64_4: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: xori $3, $5, 4 +; MM32R3-NEXT: move $2, $4 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: xor_i64_4: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: xori $3, $5, 4 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: xor_i64_4: - - ; GP32: xori $3, $5, 4 - ; GP32: move $2, $4 - - ; GP64: xori $2, $4, 4 - - ; MM32: xori $3, $5, 4 - ; MM32: move $2, $4 - %r = xor i64 4, %b ret i64 %r } define signext i128 @xor_i128_4(i128 signext %b) { +; MIPS-LABEL: xor_i128_4: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: xori $1, $7, 4 +; MIPS-NEXT: move $2, $4 +; MIPS-NEXT: move $3, $5 +; MIPS-NEXT: move $4, $6 +; MIPS-NEXT: jr $ra +; MIPS-NEXT: move $5, $1 +; +; MIPS32R2-LABEL: xor_i128_4: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: xori $1, $7, 4 +; MIPS32R2-NEXT: move $2, $4 +; MIPS32R2-NEXT: move $3, $5 +; MIPS32R2-NEXT: move $4, $6 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: move $5, $1 +; +; MIPS32R6-LABEL: xor_i128_4: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: xori $1, $7, 4 +; MIPS32R6-NEXT: move $2, $4 +; MIPS32R6-NEXT: move $3, $5 +; MIPS32R6-NEXT: move $4, $6 +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: move $5, $1 +; +; MIPS64-LABEL: xor_i128_4: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: xori $3, $5, 4 +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: move $2, $4 +; +; MIPS64R2-LABEL: xor_i128_4: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: xori $3, $5, 4 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: move $2, $4 +; +; MIPS64R6-LABEL: xor_i128_4: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: xori $3, $5, 4 +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: move $2, $4 +; +; MM32R3-LABEL: xor_i128_4: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: xori $1, $7, 4 +; MM32R3-NEXT: move $2, $4 +; MM32R3-NEXT: move $3, $5 +; MM32R3-NEXT: move $4, $6 +; MM32R3-NEXT: move $5, $1 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: xor_i128_4: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: xori $1, $7, 4 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: move $3, $5 +; MM32R6-NEXT: move $4, $6 +; MM32R6-NEXT: move $5, $1 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: xor_i128_4: - - ; GP32: xori $[[T0:[0-9]+]], $7, 4 - ; GP32: move $2, $4 - ; GP32: move $3, $5 - ; GP32: move $4, $6 - ; GP32: move $5, $[[T0]] - - ; GP64: xori $3, $5, 4 - ; GP64: move $2, $4 - - ; MM32: xori $[[T0:[0-9]+]], $7, 4 - ; MM32: move $2, $4 - ; MM32: move $3, $5 - ; MM32: move $4, $6 - ; MM32: move $5, $[[T0]] - %r = xor i128 4, %b ret i128 %r } |