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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2013-09-27 10:08:31 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2013-09-27 10:08:31 +0000 |
| commit | f1ef27e6e308435035ffec112a6474ed5e009484 (patch) | |
| tree | e95a12e18af12ddcc5e485c2bce80ccbd3decd89 /test/CodeGen/Mips/msa/arithmetic.ll | |
| parent | d2a31a124f3bebbdfc4d886afe33a116893aa689 (diff) | |
[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191498 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Mips/msa/arithmetic.ll')
| -rw-r--r-- | test/CodeGen/Mips/msa/arithmetic.ll | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/test/CodeGen/Mips/msa/arithmetic.ll b/test/CodeGen/Mips/msa/arithmetic.ll index 7dc758e35df..dc655e184ab 100644 --- a/test/CodeGen/Mips/msa/arithmetic.ll +++ b/test/CodeGen/Mips/msa/arithmetic.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s +; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s define void @add_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind { ; CHECK: add_v16i8: |