diff options
| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2013-09-24 12:18:31 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2013-09-24 12:18:31 +0000 |
| commit | 89d13c1b380218d381be035eb5e4d83dcbc391cc (patch) | |
| tree | 14ae72a2db43161220cf3eaba2cc1f1124a731b6 /test/CodeGen/Mips/msa/arithmetic.ll | |
| parent | 38a10ff063971c2f7f7384cceba3253bca32e27a (diff) | |
[mips][msa] Added support for matching max, maxi, min, mini from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191291 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Mips/msa/arithmetic.ll')
| -rw-r--r-- | test/CodeGen/Mips/msa/arithmetic.ll | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/test/CodeGen/Mips/msa/arithmetic.ll b/test/CodeGen/Mips/msa/arithmetic.ll index d695f1204fa..7dc758e35df 100644 --- a/test/CodeGen/Mips/msa/arithmetic.ll +++ b/test/CodeGen/Mips/msa/arithmetic.ll @@ -69,7 +69,8 @@ define void @add_v16i8_i(<16 x i8>* %c, <16 x i8>* %a) nounwind { %1 = load <16 x i8>* %a ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5) - %2 = add <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> + %2 = add <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, + i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> ; CHECK-DAG: addvi.b [[R3:\$w[0-9]+]], [[R1]], 1 store <16 x i8> %2, <16 x i8>* %c ; CHECK-DAG: st.b [[R3]], 0($4) @@ -83,7 +84,8 @@ define void @add_v8i16_i(<8 x i16>* %c, <8 x i16>* %a) nounwind { %1 = load <8 x i16>* %a ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5) - %2 = add <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> + %2 = add <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, + i16 1, i16 1, i16 1, i16 1> ; CHECK-DAG: addvi.h [[R3:\$w[0-9]+]], [[R1]], 1 store <8 x i16> %2, <8 x i16>* %c ; CHECK-DAG: st.h [[R3]], 0($4) @@ -189,7 +191,8 @@ define void @sub_v16i8_i(<16 x i8>* %c, <16 x i8>* %a) nounwind { %1 = load <16 x i8>* %a ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5) - %2 = sub <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> + %2 = sub <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, + i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> ; CHECK-DAG: subvi.b [[R3:\$w[0-9]+]], [[R1]], 1 store <16 x i8> %2, <16 x i8>* %c ; CHECK-DAG: st.b [[R3]], 0($4) @@ -203,7 +206,8 @@ define void @sub_v8i16_i(<8 x i16>* %c, <8 x i16>* %a) nounwind { %1 = load <8 x i16>* %a ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5) - %2 = sub <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> + %2 = sub <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, + i16 1, i16 1, i16 1, i16 1> ; CHECK-DAG: subvi.h [[R3:\$w[0-9]+]], [[R1]], 1 store <8 x i16> %2, <8 x i16>* %c ; CHECK-DAG: st.h [[R3]], 0($4) |