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| author | Zlatko Buljan <Zlatko.Buljan@imgtec.com> | 2016-07-11 07:41:56 +0000 |
|---|---|---|
| committer | Zlatko Buljan <Zlatko.Buljan@imgtec.com> | 2016-07-11 07:41:56 +0000 |
| commit | 279cd1ed0bc42d2ccbb1d4ef8ecdd1c41b5e7a5e (patch) | |
| tree | b62b398ad85fce85bc3f46a147b1568334617561 /test/CodeGen/Mips/micromips-lwc1-swc1.ll | |
| parent | 02c0f025fea67d2b75f61a51a7343f9825c55597 (diff) | |
[mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and SWC2 instructions and add CodeGen support
Differential Revision: http://reviews.llvm.org/D18824
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275050 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Mips/micromips-lwc1-swc1.ll')
| -rw-r--r-- | test/CodeGen/Mips/micromips-lwc1-swc1.ll | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/test/CodeGen/Mips/micromips-lwc1-swc1.ll b/test/CodeGen/Mips/micromips-lwc1-swc1.ll new file mode 100644 index 00000000000..a1a10a5de25 --- /dev/null +++ b/test/CodeGen/Mips/micromips-lwc1-swc1.ll @@ -0,0 +1,50 @@ +; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips \ +; RUN: -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=ALL,MM32 +; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips \ +; RUN: -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=ALL,MM32 +; RUN: llc -march=mips -mcpu=mips64r6 -mattr=+micromips -target-abi n64 \ +; RUN: -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=ALL,MM64 + +@gf0 = external global float + +define float @test_lwc1() { +entry: +; CHECK-LABEL: test_lwc1 +; MM32: lui $[[R0:[0-9]+]], %hi(_gp_disp) +; MM32: addiu $[[R1:[0-9]+]], $[[R0]], %lo(_gp_disp) +; MM32: addu $[[R2:[0-9]+]], $[[R1]], $25 +; MM32: lw $[[R3:[0-9]+]], %got(gf0)($[[R2]]) +; MM32: lwc1 $f0, 0($[[R3]]) + +; MM64: lui $[[R0:[0-9]+]], %hi(%neg(%gp_rel(test_lwc1))) +; MM64: daddu $[[R1:[0-9]+]], $[[R0]], $25 +; MM64: daddiu $[[R2:[0-9]+]], $[[R1]], %lo(%neg(%gp_rel(test_lwc1))) +; MM64: ld $[[R3:[0-9]+]], %got_disp(gf0)($[[R2]]) +; MM64: lwc1 $f0, 0($[[R3]]) + + %0 = load float, float* @gf0, align 4 + ret float %0 +} + +define void @test_swc1(float %a) { +entry: +; CHECK-LABEL: test_swc1 +; MM32: lui $[[R0:[0-9]+]], %hi(_gp_disp) +; MM32: addiu $[[R1:[0-9]+]], $[[R0]], %lo(_gp_disp) +; MM32: addu $[[R2:[0-9]+]], $[[R1]], $25 +; MM32: lw $[[R3:[0-9]+]], %got(gf0)($[[R2]]) +; MM32: swc1 $f12, 0($[[R3]]) + +; MM64: lui $[[R0:[0-9]+]], %hi(%neg(%gp_rel(test_swc1))) +; MM64: daddu $[[R1:[0-9]+]], $[[R0]], $25 +; MM64: daddiu $[[R2:[0-9]+]], $[[R1]], %lo(%neg(%gp_rel(test_swc1))) +; MM64: ld $[[R3:[0-9]+]], %got_disp(gf0)($[[R2]]) +; MM64: swc1 $f12, 0($[[R3]]) + + store float %a, float* @gf0, align 4 + ret void +} + |