[mips] Pick the right variant of DINS upfront and enable target instruction verification

This patch complements D16810 "[mips] Make isel select the correct DEXT variant
up front.". Now ISel picks the right variant of DINS, so now there is no need
to replace DINS with the appropriate variant during
MipsMCCodeEmitter::encodeInstruction().

This patch also enables target specific instruction verification for ins, dins,
dinsm, dinsu, ext, dext, dextm, dextu. These instructions have constraints that
are checked when generating MipsISD::Ins and MipsISD::Ext nodes, but these
constraints are not checked during instruction selection. Adding machine
verification should catch outstanding cases.

Finally, correct a bug that instruction verification uncovered, where the
position operand of a DINSU generated during lowering was being silently
and accidently corrected to the correct value.

Reviewers: slthakur

Differential Revision: https://reviews.llvm.org/D34809


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313254 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 54 insertions, 0 deletions

diff --git a/test/CodeGen/Mips/instverify/ins-pos-size.mir b/test/CodeGen/Mips/instverify/ins-pos-size.mir
new file mode 100644
index 00000000000..95872364e07
--- /dev/null
+++ b/test/CodeGen/Mips/instverify/ins-pos-size.mir
@@ -0,0 +1,54 @@
+# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
+# RUN:         -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
+
+# CHECK: Position + Size is out of range!
+
+# Check that the machine verifier checks the pos + size  is in range 0..32
+---
+name:            f
+alignment:       2
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr32, preferred-register: '' }
+  - { id: 1, class: gpr32, preferred-register: '' }
+  - { id: 2, class: gpr32, preferred-register: '' }
+  - { id: 3, class: gpr32, preferred-register: '' }
+liveins:
+  - { reg: '%a0', virtual-reg: '%0' }
+  - { reg: '%a1', virtual-reg: '%1' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    1
+  adjustsStack:    false
+  hasCalls:        false
+  stackProtector:  ''
+  maxCallFrameSize: 4294967295
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:
+stack:
+constants:
+body:             |
+  bb.0.entry:
+    liveins: %a0, %a1
+
+    %1 = COPY %a1
+    %0 = COPY %a0
+    %2 = ANDi %1, 15
+    %3 = INS killed %2, 17, 17, %0
+    %v0 = COPY %3
+    RetRA implicit %v0
+
+...