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| author | Toma Tabacu <toma.tabacu@imgtec.com> | 2014-12-17 10:56:16 +0000 |
|---|---|---|
| committer | Toma Tabacu <toma.tabacu@imgtec.com> | 2014-12-17 10:56:16 +0000 |
| commit | 3fea427a639363f550423322c2ace5da7f1f15a0 (patch) | |
| tree | ee966c51d10c7a4eddaea81230be3b182941e8bf /test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll | |
| parent | 4bfc4f2e8ca185f850998e90fb11c76ff1a1c98e (diff) | |
[mips] Set GCC-compatible MIPS asssembler options before inline asm blocks.
Summary:
When generating MIPS assembly, LLVM always overrides the default assembler options by emitting the '.set noreorder', '.set nomacro' and '.set noat' directives,
while GCC uses the default options if an assembly-level function contains inline assembly code.
This becomes a problem when the code generated by LLVM is interleaved with inline assembly which assumes GCC-like assembler options (from Linux, for example).
This patch fixes these conflicts by setting the appropriate assembler options at the beginning of an inline asm block and popping them at the end.
Reviewers: dsanders
Reviewed By: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D6637
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224425 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll')
| -rw-r--r-- | test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll b/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll index a67ddce222a..41991d07a4f 100644 --- a/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll +++ b/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll @@ -32,10 +32,10 @@ entry: ; Now l with 1024: make sure register lo is picked. We do this by checking the instruction ; after the inline expression for a mflo to pull the value out of lo. -; CHECK: #APP -; CHECK-NEXT: mtlo ${{[0-9]+}} +; CHECK: #APP +; CHECK: mtlo ${{[0-9]+}} ; CHECK-NEXT: madd ${{[0-9]+}},${{[0-9]+}} -; CHECK-NEXT: #NO_APP +; CHECK: #NO_APP ; CHECK-NEXT: mflo ${{[0-9]+}} %bosco = alloca i32, align 4 call i32 asm sideeffect "\09mtlo $3 \0A\09\09madd $1,$2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounwind |