summaryrefslogtreecommitdiff
path: root/test/CodeGen/MSP430
diff options
context:
space:
mode:
authorNirav Dave <niravd@google.com>2017-07-05 01:21:23 +0000
committerNirav Dave <niravd@google.com>2017-07-05 01:21:23 +0000
commit3f4f926b6a830a8555747288e7d2de0a983ef395 (patch)
tree1dad349cdbf6c37f191a9e3cdbf5ed522e23d336 /test/CodeGen/MSP430
parente75c6758b9cc13dba37025e347242ce81395432e (diff)
Rewrite areNonVolatileConsecutiveLoads to use BaseIndexOffset
Relanding after rewriting undef.ll test to avoid host-dependant endianness. As discussed in D34087, rewrite areNonVolatileConsecutiveLoads using generic checks. Also, propagate missing local handling from there to BaseIndexOffset checks. Tests of note: * test/CodeGen/X86/build-vector* - Improved. * test/CodeGen/BPF/undef.ll - Improved store alignment allows an additional store merge * test/CodeGen/X86/clear_upper_vector_element_bits.ll - This is a case we already do not handle well. Here, the DAG is improved, but scheduling causes a code size degradation. Reviewers: RKSimon, craig.topper, spatel, andreadb, filcab Subscribers: nemanjai, llvm-commits Differential Revision: https://reviews.llvm.org/D34472 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307114 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/MSP430')
-rw-r--r--test/CodeGen/MSP430/Inst16mm.ll4
1 files changed, 2 insertions, 2 deletions
diff --git a/test/CodeGen/MSP430/Inst16mm.ll b/test/CodeGen/MSP430/Inst16mm.ll
index 951002d60a0..14a799b9171 100644
--- a/test/CodeGen/MSP430/Inst16mm.ll
+++ b/test/CodeGen/MSP430/Inst16mm.ll
@@ -64,6 +64,6 @@ entry:
%0 = load i16, i16* %retval ; <i16> [#uses=1]
ret i16 %0
; CHECK-LABEL: mov2:
-; CHECK: mov.w 0(r1), 4(r1)
-; CHECK: mov.w 2(r1), 6(r1)
+; CHECK-DAG: mov.w 2(r1), 6(r1)
+; CHECK-DAG: mov.w 0(r1), 4(r1)
}