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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-07-02 23:21:48 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-07-02 23:21:48 +0000 |
| commit | ff0022d12c12b546287eb0f3cb0b82ac31a15ed3 (patch) | |
| tree | 30763c799a47e766cced53aab78029d5b1fb954c /test/CodeGen/MIR | |
| parent | 0e6595164d3920a968de274d3b0590a710fad3b2 (diff) | |
AMDGPU: Add operand target flags serialization
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306995 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/MIR')
| -rw-r--r-- | test/CodeGen/MIR/AMDGPU/target-flags.mir | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/test/CodeGen/MIR/AMDGPU/target-flags.mir b/test/CodeGen/MIR/AMDGPU/target-flags.mir new file mode 100644 index 00000000000..7d288dd1b04 --- /dev/null +++ b/test/CodeGen/MIR/AMDGPU/target-flags.mir @@ -0,0 +1,29 @@ +# RUN: llc -march=amdgcn -run-pass none -o - %s | FileCheck %s +--- | + define amdgpu_kernel void @flags() { + ret void + } + + declare void @foo() +... +--- + +# CHECK: SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @foo + 4, target-flags(amdgpu-rel32-hi) @foo + 4, implicit-def dead %scc +# CHECK: %1 = S_MOV_B64 target-flags(amdgpu-gotprel) @foo + +name: flags +liveins: + - { reg: '%sgpr0_sgpr1' } +frameInfo: + maxAlignment: 8 +registers: + - { id: 0, class: sreg_64, preferred-register: '' } + - { id: 1, class: sreg_64, preferred-register: '' } +body: | + bb.0: + liveins: %sgpr0_sgpr1 + %0 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @foo + 4, target-flags(amdgpu-rel32-hi) @foo + 4, implicit-def dead %scc + %1 = S_MOV_B64 target-flags(amdgpu-gotprel) @foo + + S_ENDPGM +... |