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| author | Diana Picus <diana.picus@linaro.org> | 2017-08-02 11:09:30 +0000 |
|---|---|---|
| committer | Diana Picus <diana.picus@linaro.org> | 2017-08-02 11:09:30 +0000 |
| commit | bb326e2526455f10c7c464c99c0ab3427096b6ab (patch) | |
| tree | 0877d0e9f8e3f4c25ea238d951ee4ce011734b5b /test/CodeGen/MIR | |
| parent | e36182d580b46409793c84ab1754f8d396a60880 (diff) | |
[MIR] Print target-specific constant pools
This should enable us to test the generation of target-specific constant
pools, e.g. for ARM:
constants:
- id: 0
value: 'g(GOT_PREL)-(LPC0+8-.)'
alignment: 4
isTargetSpecific: true
I intend to use this to test PIC support in GlobalISel for ARM.
This is difficult to test outside of that context, since the existing
MIR tests usually rely on parser support as well, and that seems a bit
trickier to add. We could try to add a unit test, but the setup for that
seems rather convoluted and overkill.
We do test however that the parser reports a nice error when
encountering a target-specific constant pool.
Differential Revision: https://reviews.llvm.org/D36092
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309806 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/MIR')
| -rw-r--r-- | test/CodeGen/MIR/ARM/target-constant-pools-error.mir | 27 | ||||
| -rw-r--r-- | test/CodeGen/MIR/X86/constant-pool.mir | 6 |
2 files changed, 33 insertions, 0 deletions
diff --git a/test/CodeGen/MIR/ARM/target-constant-pools-error.mir b/test/CodeGen/MIR/ARM/target-constant-pools-error.mir new file mode 100644 index 00000000000..4fc7ea1f3cd --- /dev/null +++ b/test/CodeGen/MIR/ARM/target-constant-pools-error.mir @@ -0,0 +1,27 @@ +# RUN: not llc -mtriple arm-unknown -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +--- | + target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" + + @g = private global i32 4 + define void @target_constant_pool() { ret void } +... +--- +name: target_constant_pool +tracksRegLiveness: true +registers: + - { id: 0, class: gpr, preferred-register: '' } + - { id: 1, class: gpr, preferred-register: '' } +constants: + - id: 0 + # CHECK: [[@LINE+1]]:22: Can't parse target-specific constant pool entries yet + value: 'g-(LPC0+8)' + alignment: 4 + isTargetSpecific: true +body: | + bb.0.entry: + %0 = LDRi12 %const.0, 0, 14, _ :: (load 4 from constant-pool) + %1 = PICLDR killed %0, 0, 14, _ :: (dereferenceable load 4 from @g) + %r0 = COPY %1 + BX_RET 14, _, implicit %r0 + +... diff --git a/test/CodeGen/MIR/X86/constant-pool.mir b/test/CodeGen/MIR/X86/constant-pool.mir index 3312e6f67bd..60e12d3ddcd 100644 --- a/test/CodeGen/MIR/X86/constant-pool.mir +++ b/test/CodeGen/MIR/X86/constant-pool.mir @@ -46,9 +46,11 @@ # CHECK-NEXT: - id: 0 # CHECK-NEXT: value: 'double 3.250000e+00' # CHECK-NEXT: alignment: 8 +# CHECK-NEXT: isTargetSpecific: false # CHECK-NEXT: - id: 1 # CHECK-NEXT: value: 'float 6.250000e+00' # CHECK-NEXT: alignment: 4 +# CHECK-NEXT: isTargetSpecific: false name: test constants: - id: 0 @@ -74,9 +76,11 @@ body: | # CHECK-NEXT: - id: 0 # CHECK-NEXT: value: 'double 3.250000e+00' # CHECK-NEXT: alignment: 8 +# CHECK-NEXT: isTargetSpecific: false # CHECK-NEXT: - id: 1 # CHECK-NEXT: value: 'float 6.250000e+00' # CHECK-NEXT: alignment: 4 +# CHECK-NEXT: isTargetSpecific: false name: test2 constants: - id: 0 @@ -98,9 +102,11 @@ body: | # CHECK-NEXT: - id: 0 # CHECK-NEXT: value: 'double 3.250000e+00' # CHECK-NEXT: alignment: 128 +# CHECK-NEXT: isTargetSpecific: false # CHECK-NEXT: - id: 1 # CHECK-NEXT: value: 'float 6.250000e+00' # CHECK-NEXT: alignment: 1 +# CHECK-NEXT: isTargetSpecific: false name: test3 constants: - id: 0 |