Canonicalize a large number of mir tests using update_mir_test_checks

This converts a large and somewhat arbitrary set of tests to use
update_mir_test_checks. I ran the script on all of the tests I expect
to need to modify for an upcoming mir syntax change and kept the ones
that obviously didn't change the tests in ways that might make it
harder to understand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316137 91177308-0d34-0410-b5e6-96231b3b80d8

7 files changed, 49 insertions, 26 deletions

diff --git a/test/CodeGen/MIR/AArch64/atomic-memoperands.mir b/test/CodeGen/MIR/AArch64/atomic-memoperands.mir
index 1c81f580bee..0b182a7ecc4 100644
--- a/test/CodeGen/MIR/AArch64/atomic-memoperands.mir
+++ b/test/CodeGen/MIR/AArch64/atomic-memoperands.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass none -o - %s | FileCheck %s
 
 --- |
@@ -8,17 +9,19 @@
 
 ...
 ---
-# CHECK-LABEL: name: atomic_memoperands
-# CHECK: %1(s64) = G_LOAD %0(p0) :: (load unordered 8)
-# CHECK: %2(s32) = G_LOAD %0(p0) :: (load monotonic 4)
-# CHECK: %3(s16) = G_LOAD %0(p0) :: (load acquire 2)
-# CHECK: G_STORE %3(s16), %0(p0) :: (store release 2)
-# CHECK: G_STORE %2(s32), %0(p0) :: (store acq_rel 4)
-# CHECK: G_STORE %1(s64), %0(p0) :: (store syncscope("singlethread") seq_cst 8)
 name:            atomic_memoperands
 body: |
   bb.0:
 
+    ; CHECK-LABEL: name: atomic_memoperands
+    ; CHECK: [[COPY:%[0-9]+]](p0) = COPY %x0
+    ; CHECK: [[LOAD:%[0-9]+]](s64) = G_LOAD [[COPY]](p0) :: (load unordered 8)
+    ; CHECK: [[LOAD1:%[0-9]+]](s32) = G_LOAD [[COPY]](p0) :: (load monotonic 4)
+    ; CHECK: [[LOAD2:%[0-9]+]](s16) = G_LOAD [[COPY]](p0) :: (load acquire 2)
+    ; CHECK: G_STORE [[LOAD2]](s16), [[COPY]](p0) :: (store release 2)
+    ; CHECK: G_STORE [[LOAD1]](s32), [[COPY]](p0) :: (store acq_rel 4)
+    ; CHECK: G_STORE [[LOAD]](s64), [[COPY]](p0) :: (store syncscope("singlethread") seq_cst 8)
+    ; CHECK: RET_ReallyLR
     %0:_(p0) = COPY %x0
     %1:_(s64) = G_LOAD %0(p0) :: (load unordered 8)
     %2:_(s32) = G_LOAD %0(p0) :: (load monotonic 4)
diff --git a/test/CodeGen/MIR/AArch64/target-memoperands.mir b/test/CodeGen/MIR/AArch64/target-memoperands.mir
index c71302d97e2..0df4443d6a0 100644
--- a/test/CodeGen/MIR/AArch64/target-memoperands.mir
+++ b/test/CodeGen/MIR/AArch64/target-memoperands.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass none -o - %s | FileCheck %s
 
 --- |
@@ -8,15 +9,17 @@
 
 ...
 ---
-# CHECK-LABEL: name: target_memoperands
-# CHECK: %1(s64) = G_LOAD %0(p0) :: ("aarch64-suppress-pair" load 8)
-# CHECK: %2(s32) = G_LOAD %0(p0) :: ("aarch64-strided-access" load 4)
-# CHECK: G_STORE %1(s64), %0(p0) :: ("aarch64-suppress-pair" store 8)
-# CHECK: G_STORE %2(s32), %0(p0) :: ("aarch64-strided-access" store 4)
 name:            target_memoperands
 body: |
   bb.0:
 
+    ; CHECK-LABEL: name: target_memoperands
+    ; CHECK: [[COPY:%[0-9]+]](p0) = COPY %x0
+    ; CHECK: [[LOAD:%[0-9]+]](s64) = G_LOAD [[COPY]](p0) :: ("aarch64-suppress-pair" load 8)
+    ; CHECK: [[LOAD1:%[0-9]+]](s32) = G_LOAD [[COPY]](p0) :: ("aarch64-strided-access" load 4)
+    ; CHECK: G_STORE [[LOAD]](s64), [[COPY]](p0) :: ("aarch64-suppress-pair" store 8)
+    ; CHECK: G_STORE [[LOAD1]](s32), [[COPY]](p0) :: ("aarch64-strided-access" store 4)
+    ; CHECK: RET_ReallyLR
     %0:_(p0) = COPY %x0
     %1:_(s64) = G_LOAD %0(p0) :: ("aarch64-suppress-pair" load 8)
     %2:_(s32) = G_LOAD %0(p0) :: ("aarch64-strided-access" load 4)
diff --git a/test/CodeGen/MIR/AMDGPU/intrinsics.mir b/test/CodeGen/MIR/AMDGPU/intrinsics.mir
index cb6e6190990..cbe78716ae2 100644
--- a/test/CodeGen/MIR/AMDGPU/intrinsics.mir
+++ b/test/CodeGen/MIR/AMDGPU/intrinsics.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn -run-pass none -o - %s | FileCheck %s
 
 --- |
@@ -9,11 +10,12 @@
 ...
 ---
 # Completely invalid code, but it checks that intrinsics round-trip properly.
-# CHECK: %0(s64) = COPY intrinsic(@llvm.amdgcn.sbfe)
 name:            use_intrin
 registers:
   - { id: 0, class: _ }
 body: |
   bb.0:
+    ; CHECK-LABEL: name: use_intrin
+    ; CHECK: [[COPY:%[0-9]+]](s64) = COPY intrinsic(@llvm.amdgcn.sbfe)
     %0(s64) = COPY intrinsic(@llvm.amdgcn.sbfe.i32)
 ...
diff --git a/test/CodeGen/MIR/AMDGPU/target-flags.mir b/test/CodeGen/MIR/AMDGPU/target-flags.mir
index 7d288dd1b04..dff119d573d 100644
--- a/test/CodeGen/MIR/AMDGPU/target-flags.mir
+++ b/test/CodeGen/MIR/AMDGPU/target-flags.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -march=amdgcn -run-pass none -o - %s | FileCheck %s
 --- |
   define amdgpu_kernel void @flags() {
@@ -8,8 +9,6 @@
 ...
 ---
 
-# CHECK: SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @foo + 4, target-flags(amdgpu-rel32-hi) @foo + 4, implicit-def dead %scc
-# CHECK: %1 = S_MOV_B64 target-flags(amdgpu-gotprel) @foo
 
 name: flags
 liveins:
@@ -22,6 +21,10 @@ registers:
 body: |
   bb.0:
     liveins: %sgpr0_sgpr1
+    ; CHECK-LABEL: name: flags
+    ; CHECK: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]] = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @foo + 4, target-flags(amdgpu-rel32-hi) @foo + 4, implicit-def dead %scc
+    ; CHECK: [[S_MOV_B64_:%[0-9]+]] = S_MOV_B64 target-flags(amdgpu-gotprel) @foo
+    ; CHECK: S_ENDPGM
     %0 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @foo + 4, target-flags(amdgpu-rel32-hi) @foo + 4, implicit-def dead %scc
   %1 = S_MOV_B64 target-flags(amdgpu-gotprel) @foo
 
diff --git a/test/CodeGen/MIR/X86/stack-object-operands.mir b/test/CodeGen/MIR/X86/stack-object-operands.mir
index 1c5208ee30e..163d50395a3 100644
--- a/test/CodeGen/MIR/X86/stack-object-operands.mir
+++ b/test/CodeGen/MIR/X86/stack-object-operands.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -march=x86 -run-pass none -o - %s | FileCheck %s
 # This test ensures that the MIR parser parses stack object machine operands
 # correctly.
@@ -29,12 +30,14 @@ stack:
   - { id: 0, name: b, size: 4, alignment: 4 }
   - { id: 1, size: 4, alignment: 4 }
 body: |
-  ; CHECK: bb.0.entry:
-  ; CHECK-NEXT: %0 = MOV32rm %fixed-stack.0, 1, _, 0, _
-  ; CHECK-NEXT: MOV32mr %stack.0.b, 1, _, 0, _, %0
-  ; CHECK-NEXT: MOV32mi %stack.1, 1, _, 0, _, 2
-  ; CHECK-NEXT: %1 = MOV32rm %stack.0.b, 1, _, 0, _
   bb.0.entry:
+    ; CHECK-LABEL: name: test
+    ; CHECK: [[MOV32rm:%[0-9]+]] = MOV32rm %fixed-stack.0, 1, _, 0, _
+    ; CHECK: MOV32mr %stack.0.b, 1, _, 0, _, [[MOV32rm]]
+    ; CHECK: MOV32mi %stack.1, 1, _, 0, _, 2
+    ; CHECK: [[MOV32rm1:%[0-9]+]] = MOV32rm %stack.0.b, 1, _, 0, _
+    ; CHECK: %eax = COPY [[MOV32rm1]]
+    ; CHECK: RETL %eax
     %0 = MOV32rm %fixed-stack.0, 1, _, 0, _
     MOV32mr %stack.0.b, 1, _, 0, _, %0
     MOV32mi %stack.1, 1, _, 0, _, 2
diff --git a/test/CodeGen/MIR/X86/subregister-index-operands.mir b/test/CodeGen/MIR/X86/subregister-index-operands.mir
index e6c7c6e2e4c..c4f8ee143a0 100644
--- a/test/CodeGen/MIR/X86/subregister-index-operands.mir
+++ b/test/CodeGen/MIR/X86/subregister-index-operands.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
 # This test ensures that the MIR parser parses and prints subregisters index
 # operands correctly.
@@ -11,10 +12,6 @@
 
 ...
 ---
-# CHECK-LABEL: name: t
-# CHECK: %0 = INSERT_SUBREG %edi, %al, {{[0-9]+}}
-# CHECK: %1 = EXTRACT_SUBREG %eax, {{[0-9]+}}
-# CHECK: %ax = REG_SEQUENCE %1, {{[0-9]+}}, %1, {{[0-9]+}}
 name:            t
 tracksRegLiveness: true
 registers:
@@ -23,6 +20,12 @@ registers:
 body: |
   bb.0.entry:
     liveins: %edi, %eax
+    ; CHECK-LABEL: name: t
+    ; CHECK: liveins: %edi, %eax
+    ; CHECK: [[INSERT_SUBREG:%[0-9]+]] = INSERT_SUBREG %edi, %al, 1
+    ; CHECK: [[EXTRACT_SUBREG:%[0-9]+]] = EXTRACT_SUBREG %eax, 2
+    ; CHECK: %ax = REG_SEQUENCE [[EXTRACT_SUBREG]], 1, [[EXTRACT_SUBREG]], 2
+    ; CHECK: RETQ %ax
     %0 = INSERT_SUBREG %edi, %al, %subreg.sub_8bit
     %1 = EXTRACT_SUBREG %eax, %subreg.sub_8bit_hi
     %ax = REG_SEQUENCE %1, %subreg.sub_8bit, %1, %subreg.sub_8bit_hi
diff --git a/test/CodeGen/MIR/X86/subregister-operands.mir b/test/CodeGen/MIR/X86/subregister-operands.mir
index 6dd44aec07a..282e0cc7e42 100644
--- a/test/CodeGen/MIR/X86/subregister-operands.mir
+++ b/test/CodeGen/MIR/X86/subregister-operands.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
 # This test ensures that the MIR parser parses subregisters in register operands
 # correctly.
@@ -20,8 +21,13 @@ registers:
 body: |
   bb.0.entry:
     liveins: %edi
-    ; CHECK:      %0 = COPY %edi
-    ; CHECK-NEXT: %1 = COPY %0.sub_8bit
+    ; CHECK-LABEL: name: t
+    ; CHECK: liveins: %edi
+    ; CHECK: [[COPY:%[0-9]+]] = COPY %edi
+    ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_8bit
+    ; CHECK: [[AND8ri:%[0-9]+]] = AND8ri [[COPY1]], 1, implicit-def %eflags
+    ; CHECK: %al = COPY [[AND8ri]]
+    ; CHECK: RETQ %al
     %0 = COPY %edi
     %1 = COPY %0.sub_8bit
     %2 = AND8ri %1, 1, implicit-def %eflags