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| author | Daniel Sanders <daniel_l_sanders@apple.com> | 2017-11-28 18:57:02 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel_l_sanders@apple.com> | 2017-11-28 18:57:02 +0000 |
| commit | 7b3df669cba47d600dadce935db402687ad9cd28 (patch) | |
| tree | 6aee7885c517c63fd62a479f998207956d1c1cfc /test/CodeGen/MIR | |
| parent | 82ef781f4e418114e9521ea02661a526472e06bc (diff) | |
[mir] Print/Parse both MOLoad and MOStore when they occur together.
Summary:
They're not always mutually exclusive. read-modify-write atomics are both
at the same time. One example of this is the SWP instructions on AArch64.
Another example is GlobalISel's G_ATOMICRMW_* generic instructions which
will be added in a later patch.
Reviewers: arphaman, aemerson
Reviewed By: aemerson
Subscribers: aemerson, javed.absar, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D40157
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319202 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/MIR')
| -rw-r--r-- | test/CodeGen/MIR/AArch64/swp.mir | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/test/CodeGen/MIR/AArch64/swp.mir b/test/CodeGen/MIR/AArch64/swp.mir new file mode 100644 index 00000000000..4a31ab43535 --- /dev/null +++ b/test/CodeGen/MIR/AArch64/swp.mir @@ -0,0 +1,33 @@ +# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass none -o - %s | FileCheck %s + +--- | + define i32 @swp(i32* %addr) #0 { + entry: + %0 = atomicrmw xchg i32* %addr, i32 1 monotonic + ret i32 %0 + } + + attributes #0 = { "target-features"="+lse" } +... +--- +name: swp +alignment: 2 +tracksRegLiveness: true +registers: + - { id: 0, class: gpr64common } + - { id: 1, class: gpr32 } + - { id: 2, class: gpr32 } +liveins: + - { reg: '%x0', virtual-reg: '%0' } +body: | + bb.0.entry: + liveins: %x0 + + ; CHECK-LABEL: swp + ; CHECK: {{[0-9]+}}:gpr32 = SWPW killed %1, %0 :: (volatile load store monotonic 4 on %ir.addr) + %0:gpr64common = COPY %x0 + %1:gpr32 = MOVi32imm 1 + %2:gpr32 = SWPW killed %1, %0 :: (volatile load store monotonic 4 on %ir.addr) + %w0 = COPY %2 + RET_ReallyLR implicit %w0 +... |