MIR Serialization: Change MIR syntax - use custom syntax for MBBs.

This commit modifies the way the machine basic blocks are serialized - now the
machine basic blocks are serialized using a custom syntax instead of relying on
YAML primitives. Instead of using YAML mappings to represent the individual
machine basic blocks in a machine function's body, the new syntax uses a single
YAML block scalar which contains all of the machine basic blocks and
instructions for that function.

This is an example of a function's body that uses the old syntax:

    body:
      - id: 0
        name: entry
        instructions:
          - '%eax = MOV32r0 implicit-def %eflags'
          - 'RETQ %eax'
    ...

The same body is now written like this:

    body: |
      bb.0.entry:
        %eax = MOV32r0 implicit-def %eflags
        RETQ %eax
    ...

This syntax change is motivated by the fact that the bundled machine
instructions didn't map that well to the old syntax which was using a single
YAML sequence to store all of the machine instructions in a block. The bundled
machine instructions internally use flags like BundledPred and BundledSucc to
determine the bundles, and serializing them as MI flags using the old syntax
would have had a negative impact on the readability and the ease of editing
for MIR files. The new syntax allows me to serialize the bundled machine
instructions using a block construct without relying on the internal flags,
for example:

   BUNDLE implicit-def dead %itstate, implicit-def %s1 ... {
      t2IT 1, 24, implicit-def %itstate
      %s1 = VMOVS killed %s0, 1, killed %cpsr, implicit killed %itstate
   }

This commit also converts the MIR testcases to the new syntax. I developed
a script that can convert from the old syntax to the new one. I will post the
script on the llvm-commits mailing list in the thread for this commit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@244982 91177308-0d34-0410-b5e6-96231b3b80d8

144 files changed, 2111 insertions, 2281 deletions

diff --git a/test/CodeGen/MIR/AArch64/cfi-def-cfa.mir b/test/CodeGen/MIR/AArch64/cfi-def-cfa.mir
index 6deff62ec9c..cf7572ecad3 100644
--- a/test/CodeGen/MIR/AArch64/cfi-def-cfa.mir
+++ b/test/CodeGen/MIR/AArch64/cfi-def-cfa.mir
@@ -15,18 +15,17 @@
 ...
 ---
 name:            trivial_fp_func
-body:
-  - id:          0
-    name:        entry
-    liveins:     [ '%lr', '%fp', '%lr', '%fp' ]
-    instructions:
-      - '%sp = frame-setup STPXpre killed %fp, killed %lr, %sp, -2'
-      - '%fp = frame-setup ADDXri %sp, 0, 0'
-      # CHECK: CFI_INSTRUCTION .cfi_def_cfa %w29, 16
-      - 'frame-setup CFI_INSTRUCTION .cfi_def_cfa %w29, 16'
-      - 'frame-setup CFI_INSTRUCTION .cfi_offset %w30, -8'
-      - 'frame-setup CFI_INSTRUCTION .cfi_offset %w29, -16'
-      - 'BL @foo, csr_aarch64_aapcs, implicit-def dead %lr, implicit %sp, implicit-def %sp'
-      - '%sp, %fp, %lr = LDPXpost %sp, 2'
-      - RET_ReallyLR
+body: |
+  bb.0.entry:
+    liveins: %lr, %fp, %lr, %fp
+
+    %sp = frame-setup STPXpre killed %fp, killed %lr, %sp, -2
+    %fp = frame-setup ADDXri %sp, 0, 0
+    ; CHECK: CFI_INSTRUCTION .cfi_def_cfa %w29, 16
+    frame-setup CFI_INSTRUCTION .cfi_def_cfa %w29, 16
+    frame-setup CFI_INSTRUCTION .cfi_offset %w30, -8
+    frame-setup CFI_INSTRUCTION .cfi_offset %w29, -16
+    BL @foo, csr_aarch64_aapcs, implicit-def dead %lr, implicit %sp, implicit-def %sp
+    %sp, %fp, %lr = LDPXpost %sp, 2
+    RET_ReallyLR
 ...
diff --git a/test/CodeGen/MIR/AArch64/multiple-lhs-operands.mir b/test/CodeGen/MIR/AArch64/multiple-lhs-operands.mir
index d47c8ba47f6..e23a352dff2 100644
--- a/test/CodeGen/MIR/AArch64/multiple-lhs-operands.mir
+++ b/test/CodeGen/MIR/AArch64/multiple-lhs-operands.mir
@@ -15,15 +15,14 @@
 ...
 ---
 name:            trivial_fp_func
-body:
-  - id:          0
-    name:        entry
-    liveins:     [ '%lr', '%fp', '%lr', '%fp' ]
-    instructions:
-      - '%sp = frame-setup STPXpre killed %fp, killed %lr, %sp, -2'
-      - '%fp = frame-setup ADDXri %sp, 0, 0'
-      - 'BL @foo, csr_aarch64_aapcs, implicit-def dead %lr, implicit %sp, implicit-def %sp'
-# CHECK: %sp, %fp, %lr = LDPXpost %sp, 2
-      - '%sp, %fp, %lr = LDPXpost %sp, 2'
-      - RET_ReallyLR
+body: |
+  bb.0.entry:
+    liveins: %lr, %fp, %lr, %fp
+
+    %sp = frame-setup STPXpre killed %fp, killed %lr, %sp, -2
+    %fp = frame-setup ADDXri %sp, 0, 0
+    BL @foo, csr_aarch64_aapcs, implicit-def dead %lr, implicit %sp, implicit-def %sp
+  ; CHECK: %sp, %fp, %lr = LDPXpost %sp, 2
+    %sp, %fp, %lr = LDPXpost %sp, 2
+    RET_ReallyLR
 ...
diff --git a/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir b/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir
index 9df6ba5f5d6..34793880a60 100644
--- a/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir
+++ b/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir
@@ -38,28 +38,27 @@ liveins:
   - { reg: '%sgpr0_sgpr1' }
 frameInfo:
   maxAlignment:  8
-body:
-  - id:          0
-    name:        entry
-    liveins:     [ '%sgpr0_sgpr1' ]
-    instructions:
-      - '%sgpr2_sgpr3 = S_GETPC_B64'
-# CHECK: [[@LINE+1]]:50: expected the name of the target index
-      - '%sgpr2 = S_ADD_U32 %sgpr2, target-index(0), implicit-def %scc, implicit-def %scc'
-      - '%sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc'
-      - '%sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc'
-      - '%sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11'
-      - '%sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc'
-      - '%sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc'
-      - '%sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc'
-      - '%sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc'
-      - '%sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc'
-      - '%sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc'
-      - '%sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0'
-      - '%sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9'
-      - '%sgpr7 = S_MOV_B32 61440'
-      - '%sgpr6 = S_MOV_B32 -1'
-      - '%vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec'
-      - 'BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec'
-      - S_ENDPGM
+body: |
+  bb.0.entry:
+    liveins: %sgpr0_sgpr1
+
+    %sgpr2_sgpr3 = S_GETPC_B64
+  ; CHECK: [[@LINE+1]]:45: expected the name of the target index
+    %sgpr2 = S_ADD_U32 %sgpr2, target-index(0), implicit-def %scc, implicit-def %scc
+    %sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc
+    %sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc
+    %sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11
+    %sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc
+    %sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc
+    %sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc
+    %sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc
+    %sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc
+    %sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc
+    %sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0
+    %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9
+    %sgpr7 = S_MOV_B32 61440
+    %sgpr6 = S_MOV_B32 -1
+    %vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec
+    BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec
+    S_ENDPGM
 ...
diff --git a/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir b/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir
index aeea9b2e3a5..e20cf376414 100644
--- a/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir
+++ b/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir
@@ -38,28 +38,27 @@ liveins:
   - { reg: '%sgpr0_sgpr1' }
 frameInfo:
   maxAlignment:  8
-body:
-  - id:          0
-    name:        entry
-    liveins:     [ '%sgpr0_sgpr1' ]
-    instructions:
-      - '%sgpr2_sgpr3 = S_GETPC_B64'
-# CHECK: [[@LINE+1]]:50: use of undefined target index 'constdata-start'
-      - '%sgpr2 = S_ADD_U32 %sgpr2, target-index(constdata-start), implicit-def %scc, implicit-def %scc'
-      - '%sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc'
-      - '%sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc'
-      - '%sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11'
-      - '%sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc'
-      - '%sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc'
-      - '%sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc'
-      - '%sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc'
-      - '%sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc'
-      - '%sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc'
-      - '%sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0'
-      - '%sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9'
-      - '%sgpr7 = S_MOV_B32 61440'
-      - '%sgpr6 = S_MOV_B32 -1'
-      - '%vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec'
-      - 'BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec'
-      - S_ENDPGM
+body: |
+  bb.0.entry:
+    liveins: %sgpr0_sgpr1
+
+    %sgpr2_sgpr3 = S_GETPC_B64
+  ; CHECK: [[@LINE+1]]:45: use of undefined target index 'constdata-start'
+    %sgpr2 = S_ADD_U32 %sgpr2, target-index(constdata-start), implicit-def %scc, implicit-def %scc
+    %sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc
+    %sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc
+    %sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11
+    %sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc
+    %sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc
+    %sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc
+    %sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc
+    %sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc
+    %sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc
+    %sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0
+    %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9
+    %sgpr7 = S_MOV_B32 61440
+    %sgpr6 = S_MOV_B32 -1
+    %vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec
+    BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec
+    S_ENDPGM
 ...
diff --git a/test/CodeGen/MIR/AMDGPU/target-index-operands.mir b/test/CodeGen/MIR/AMDGPU/target-index-operands.mir
index aedfae6e375..839fd3212c6 100644
--- a/test/CodeGen/MIR/AMDGPU/target-index-operands.mir
+++ b/test/CodeGen/MIR/AMDGPU/target-index-operands.mir
@@ -47,30 +47,29 @@ liveins:
   - { reg: '%sgpr0_sgpr1' }
 frameInfo:
   maxAlignment:  8
-body:
-  - id:          0
-    name:        entry
-    liveins:     [ '%sgpr0_sgpr1' ]
-    instructions:
-      - '%sgpr2_sgpr3 = S_GETPC_B64'
-# CHECK: %sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start), implicit-def %scc, implicit-def %scc
-      - '%sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start), implicit-def %scc, implicit-def %scc'
-      - '%sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc'
-      - '%sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc'
-      - '%sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11'
-      - '%sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc'
-      - '%sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc'
-      - '%sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc'
-      - '%sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc'
-      - '%sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc'
-      - '%sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc'
-      - '%sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0'
-      - '%sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9'
-      - '%sgpr7 = S_MOV_B32 61440'
-      - '%sgpr6 = S_MOV_B32 -1'
-      - '%vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec'
-      - 'BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec'
-      - S_ENDPGM
+body: |
+  bb.0.entry:
+    liveins: %sgpr0_sgpr1
+
+    %sgpr2_sgpr3 = S_GETPC_B64
+  ; CHECK: %sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start), implicit-def %scc, implicit-def %scc
+    %sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start), implicit-def %scc, implicit-def %scc
+    %sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc
+    %sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc
+    %sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11
+    %sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc
+    %sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc
+    %sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc
+    %sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc
+    %sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc
+    %sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc
+    %sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0
+    %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9
+    %sgpr7 = S_MOV_B32 61440
+    %sgpr6 = S_MOV_B32 -1
+    %vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec
+    BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec
+    S_ENDPGM
 ...
 ---
 name:            float2
@@ -79,28 +78,27 @@ liveins:
   - { reg: '%sgpr0_sgpr1' }
 frameInfo:
   maxAlignment:  8
-body:
-  - id:          0
-    name:        entry
-    liveins:     [ '%sgpr0_sgpr1' ]
-    instructions:
-      - '%sgpr2_sgpr3 = S_GETPC_B64'
-# CHECK: %sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start) + 1, implicit-def %scc, implicit-def %scc
-      - '%sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start) + 1, implicit-def %scc, implicit-def %scc'
-      - '%sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc'
-      - '%sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc'
-      - '%sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11'
-      - '%sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc'
-      - '%sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc'
-      - '%sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc'
-      - '%sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc'
-      - '%sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc'
-      - '%sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc'
-      - '%sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0'
-      - '%sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9'
-      - '%sgpr7 = S_MOV_B32 61440'
-      - '%sgpr6 = S_MOV_B32 -1'
-      - '%vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec'
-      - 'BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec'
-      - S_ENDPGM
+body: |
+  bb.0.entry:
+    liveins: %sgpr0_sgpr1
+
+    %sgpr2_sgpr3 = S_GETPC_B64
+  ; CHECK: %sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start) + 1, implicit-def %scc, implicit-def %scc
+    %sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start) + 1, implicit-def %scc, implicit-def %scc
+    %sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc
+    %sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc
+    %sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11
+    %sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc
+    %sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc
+    %sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc
+    %sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc
+    %sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc
+    %sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc
+    %sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0
+    %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9
+    %sgpr7 = S_MOV_B32 61440
+    %sgpr6 = S_MOV_B32 -1
+    %vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec
+    BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec
+    S_ENDPGM
 ...
diff --git a/test/CodeGen/MIR/Generic/basic-blocks.mir b/test/CodeGen/MIR/Generic/basic-blocks.mir
index 17313047576..22f8d28290d 100644
--- a/test/CodeGen/MIR/Generic/basic-blocks.mir
+++ b/test/CodeGen/MIR/Generic/basic-blocks.mir
@@ -13,37 +13,37 @@
     ret i32 0
   }
 
+  define i32 @test() {
+  start:
+    ret i32 0
+  }
+
 ...
 ---
-# CHECK: name: foo
+# CHECK-LABEL: name: foo
 # CHECK: body:
-# CHECK-NEXT: - id: 0
-# CHECK-NEXT:   name: entry
-# CHECK-NEXT:   alignment: 0
-# CHECK-NEXT:   isLandingPad: false
-# CHECK-NEXT:   addressTaken: false
+# CHECK-NEXT: bb.0.entry:
 name:            foo
-body:
- - id:           0
-   name:         entry
+body: |
+  bb.0.entry:
 ...
 ---
-# CHECK: name: bar
+# CHECK-LABEL: name: bar
 # CHECK: body:
-# CHECK-NEXT: - id: 0
-# CHECK-NEXT:   name: start
-# CHECK-NEXT:   alignment: 4
-# CHECK-NEXT:   isLandingPad: false
-# CHECK-NEXT:   addressTaken: false
-# CHECK-NEXT: - id: 1
-# CHECK-NEXT:   alignment: 0
-# CHECK-NEXT:   isLandingPad: false
-# CHECK-NEXT:   addressTaken: true
+# CHECK-NEXT: bb.0.start (align 4):
+# CHECK:      bb.1 (address-taken):
 name:            bar
-body:
- - id:           0
-   name:         start
-   alignment:    4
- - id:           1
-   addressTaken: true
+body: |
+  bb.0.start (align 4):
+  bb.1 (address-taken):
+...
+---
+# CHECK-LABEL: name: test
+# CHECK: body:
+# CHECK-NEXT: bb.0.start (address-taken, align 4):
+# CHECK:      bb.1 (address-taken, align 4):
+name:            test
+body: |
+  bb.0.start (align 4, address-taken):
+  bb.1 (address-taken, align 4):
 ...
diff --git a/test/CodeGen/MIR/Generic/machine-basic-block-expected-ir-block.mir b/test/CodeGen/MIR/Generic/expected-colon-after-basic-block.mir
index 2f3d40af792..892258666d1 100644
--- a/test/CodeGen/MIR/Generic/machine-basic-block-expected-ir-block.mir
+++ b/test/CodeGen/MIR/Generic/expected-colon-after-basic-block.mir
@@ -3,14 +3,14 @@
 --- |
 
   define i32 @foo() {
+  entry:
     ret i32 0
   }
 
 ...
 ---
 name:            foo
-body:
- - id:           0
-# CHECK: [[@LINE+1]]:19: expected an IR block reference
-   ir-block:     '0'
+body: |
+  ; CHECK: [[@LINE+1]]:13: expected ':'
+  bb.0.entry
 ...
diff --git a/test/CodeGen/MIR/Generic/expected-eof-after-successor-mbb.mir b/test/CodeGen/MIR/Generic/expected-eof-after-successor-mbb.mir
deleted file mode 100644
index 25ae5119297..00000000000
--- a/test/CodeGen/MIR/Generic/expected-eof-after-successor-mbb.mir
+++ /dev/null
@@ -1,29 +0,0 @@
-# RUN: not llc -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s
-
---- |
-
-  define i32 @foo(i32 %a) {
-  entry:
-    %0 = icmp sle i32 %a, 10
-    br i1 %0, label %less, label %exit
-
-  less:
-    ret i32 0
-
-  exit:
-    ret i32 %a
-  }
-
-...
----
-name:            foo
-body:
-  - id:          0
-    name:        entry
-    # CHECK: [[@LINE+1]]:46: expected end of string after the machine basic block reference
-    successors:  [ '%bb.1.less', '%bb.2.exit 2' ]
-  - id:          1
-    name:        less
-  - id:          2
-    name:        exit
-...
diff --git a/test/CodeGen/MIR/Generic/expected-mbb-reference-for-successor-mbb.mir b/test/CodeGen/MIR/Generic/expected-mbb-reference-for-successor-mbb.mir
index ce9192901d7..a5e04f86c6d 100644
--- a/test/CodeGen/MIR/Generic/expected-mbb-reference-for-successor-mbb.mir
+++ b/test/CodeGen/MIR/Generic/expected-mbb-reference-for-successor-mbb.mir
@@ -17,13 +17,12 @@
 ...
 ---
 name:            foo
-body:
-  - id:          0
-    name:        entry
-    # CHECK: [[@LINE+1]]:35: expected a machine basic block reference
-    successors:  [ '%bb.1.less', '2' ]
-  - id:          1
-    name:        less
-  - id:          2
-    name:        exit
+body: |
+  bb.0.entry:
+    ; CHECK: [[@LINE+1]]:29: expected a machine basic block reference
+    successors: %bb.1.less, 2
+
+  bb.1.less:
+
+  bb.2.exit:
 ...
diff --git a/test/CodeGen/MIR/Generic/frame-info.mir b/test/CodeGen/MIR/Generic/frame-info.mir
index c5468f94f33..6e4e3955cb1 100644
--- a/test/CodeGen/MIR/Generic/frame-info.mir
+++ b/test/CodeGen/MIR/Generic/frame-info.mir
@@ -44,9 +44,8 @@ tracksRegLiveness: true
 # CHECK: body
 frameInfo:
   maxAlignment:    4
-body:
-  - id:          0
-    name:        entry
+body: |
+  bb.0.entry:
 ...
 ---
 name:            test2
@@ -84,8 +83,7 @@ frameInfo:
   hasOpaqueSPAdjustment: true
   hasVAStart:      true
   hasMustTailInVarArgFunc: true
-body:
-  - id:          0
-    name:        entry
+body: |
+  bb.0.entry:
 ...
 
diff --git a/test/CodeGen/MIR/Generic/invalid-jump-table-kind.mir b/test/CodeGen/MIR/Generic/invalid-jump-table-kind.mir
index 4876f795386..576de4bd9dc 100644
--- a/test/CodeGen/MIR/Generic/invalid-jump-table-kind.mir
+++ b/test/CodeGen/MIR/Generic/invalid-jump-table-kind.mir
@@ -36,19 +36,18 @@ jumpTable:
   entries:
     - id:        0
       blocks:    [ '%bb.3.lbl1', '%bb.4.lbl2', '%bb.5.lbl3', '%bb.6.lbl4' ]
-body:
-  - id:          0
-    name:        entry
-  - id:          1
-    name:        entry
-  - id:          2
-    name:        def
-  - id:          3
-    name:        lbl1
-  - id:          4
-    name:        lbl2
-  - id:          5
-    name:        lbl3
-  - id:          6
-    name:        lbl4
+body: |
+  bb.0.entry:
+
+  bb.1.entry:
+
+  bb.2.def:
+
+  bb.3.lbl1:
+
+  bb.4.lbl2:
+
+  bb.5.lbl3:
+
+  bb.6.lbl4:
 ...
diff --git a/test/CodeGen/MIR/Generic/llvmIR.mir b/test/CodeGen/MIR/Generic/llvmIR.mir
index 3c084ad7d39..c7a220afa50 100644
--- a/test/CodeGen/MIR/Generic/llvmIR.mir
+++ b/test/CodeGen/MIR/Generic/llvmIR.mir
@@ -32,6 +32,6 @@
 ...
 ---
 name: foo
-body:
-  - id: 0
+body: |
+  bb.0:
 ...
diff --git a/test/CodeGen/MIR/Generic/llvmIRMissing.mir b/test/CodeGen/MIR/Generic/llvmIRMissing.mir
index 80cea5a6fda..afa96010f29 100644
--- a/test/CodeGen/MIR/Generic/llvmIRMissing.mir
+++ b/test/CodeGen/MIR/Generic/llvmIRMissing.mir
@@ -4,6 +4,6 @@
 ---
 # CHECK: name: foo
 name: foo
-body:
-  - id: 0
+body: |
+  bb.0:
 ...
diff --git a/test/CodeGen/MIR/Generic/machine-basic-block-ir-block-reference.mir b/test/CodeGen/MIR/Generic/machine-basic-block-ir-block-reference.mir
index ccbab534388..d6ecd5dc851 100644
--- a/test/CodeGen/MIR/Generic/machine-basic-block-ir-block-reference.mir
+++ b/test/CodeGen/MIR/Generic/machine-basic-block-ir-block-reference.mir
@@ -11,9 +11,7 @@
 ...
 ---
 name:            foo
-body:
-# CHECK: id: 0
-# CHECK: ir-block: '%ir-block.0'
- - id:           0
-   ir-block:     '%ir-block.0'
+body: |
+  ; CHECK: bb.0 (%ir-block.0):
+  bb.0 (%ir-block.0):
 ...
diff --git a/test/CodeGen/MIR/Generic/machine-basic-block-redefinition-error.mir b/test/CodeGen/MIR/Generic/machine-basic-block-redefinition-error.mir
index deac3b0b69b..41747535c35 100644
--- a/test/CodeGen/MIR/Generic/machine-basic-block-redefinition-error.mir
+++ b/test/CodeGen/MIR/Generic/machine-basic-block-redefinition-error.mir
@@ -10,8 +10,9 @@
 ...
 ---
 name:            foo
-body:
-  # CHECK: redefinition of machine basic block with id #0
-  - id:       0
-  - id:       0
+body: |
+  ; CHECK: [[@LINE+3]]:3: redefinition of machine basic block with id #0
+  bb.0:
+
+  bb.0:
 ...
diff --git a/test/CodeGen/MIR/Generic/machine-basic-block-undefined-ir-block.mir b/test/CodeGen/MIR/Generic/machine-basic-block-undefined-ir-block.mir
index 76d561e61fa..df559f852ec 100644
--- a/test/CodeGen/MIR/Generic/machine-basic-block-undefined-ir-block.mir
+++ b/test/CodeGen/MIR/Generic/machine-basic-block-undefined-ir-block.mir
@@ -9,8 +9,7 @@
 ...
 ---
 name:            foo
-body:
- - id:           0
-# CHECK: [[@LINE+1]]:19: use of undefined IR block '%ir-block.10'
-   ir-block:     '%ir-block.10'
+body: |
+  ; CHECK: [[@LINE+1]]:9: use of undefined IR block '%ir-block.10'
+  bb.0 (%ir-block.10):
 ...
diff --git a/test/CodeGen/MIR/Generic/machine-basic-block-unknown-name.mir b/test/CodeGen/MIR/Generic/machine-basic-block-unknown-name.mir
index df8eee9d270..876947b868b 100644
--- a/test/CodeGen/MIR/Generic/machine-basic-block-unknown-name.mir
+++ b/test/CodeGen/MIR/Generic/machine-basic-block-unknown-name.mir
@@ -12,8 +12,7 @@
 ...
 ---
 name:            foo
-body:
-  # CHECK: [[@LINE+2]]:18: basic block 'entrie' is not defined in the function 'foo'
-  - id:          0
-    name:        entrie
+body: |
+  ; CHECK: [[@LINE+1]]:3: basic block 'entrie' is not defined in the function 'foo'
+  bb.0.entrie:
 ...
diff --git a/test/CodeGen/MIR/Generic/machine-function-missing-function.mir b/test/CodeGen/MIR/Generic/machine-function-missing-function.mir
index 424c34aae84..6800f872432 100644
--- a/test/CodeGen/MIR/Generic/machine-function-missing-function.mir
+++ b/test/CodeGen/MIR/Generic/machine-function-missing-function.mir
@@ -12,12 +12,12 @@
 ...
 ---
 name:            foo
-body:
-  - id: 0
+body: |
+  bb.0:
 ...
 ---
 # CHECK: function 'faa' isn't defined in the provided LLVM IR
 name:            faa
-body:
-  - id: 0
+body: |
+  bb.0:
 ...
diff --git a/test/CodeGen/MIR/Generic/machine-function-missing-name.mir b/test/CodeGen/MIR/Generic/machine-function-missing-name.mir
index a868a65d35f..f65b77880e9 100644
--- a/test/CodeGen/MIR/Generic/machine-function-missing-name.mir
+++ b/test/CodeGen/MIR/Generic/machine-function-missing-name.mir
@@ -16,11 +16,11 @@
 ---
 # CHECK: [[@LINE+1]]:1: missing required key 'name'
 nme:             foo
-body:
-  - id: 0
+body: |
+  bb.0:
 ...
 ---
 name:            bar
-body:
-  - id: 0
+body: |
+  bb.0:
 ...
diff --git a/test/CodeGen/MIR/Generic/machine-function.mir b/test/CodeGen/MIR/Generic/machine-function.mir
index afd10ab02c2..1c4ca3d07d2 100644
--- a/test/CodeGen/MIR/Generic/machine-function.mir
+++ b/test/CodeGen/MIR/Generic/machine-function.mir
@@ -27,8 +27,8 @@
 # CHECK-NEXT: hasInlineAsm: false
 # CHECK: ...
 name:            foo
-body:
-  - id: 0
+body: |
+  bb.0:
 ...
 ---
 # CHECK: name: bar
@@ -37,8 +37,8 @@ body:
 # CHECK-NEXT: hasInlineAsm: false
 # CHECK: ...
 name:            bar
-body:
-  - id: 0
+body: |
+  bb.0:
 ...
 ---
 # CHECK: name: func
@@ -48,8 +48,8 @@ body:
 # CHECK: ...
 name:            func
 alignment:       8
-body:
-  - id: 0
+body: |
+  bb.0:
 ...
 ---
 # CHECK: name: func2
@@ -61,6 +61,6 @@ name:            func2
 alignment:       16
 exposesReturnsTwice: true
 hasInlineAsm:    true
-body:
-  - id: 0
+body: |
+  bb.0:
 ...
diff --git a/test/CodeGen/MIR/Generic/register-info.mir b/test/CodeGen/MIR/Generic/register-info.mir
index 9585faa9622..229cf0f9130 100644
--- a/test/CodeGen/MIR/Generic/register-info.mir
+++ b/test/CodeGen/MIR/Generic/register-info.mir
@@ -22,8 +22,8 @@
 # CHECK-NEXT: tracksSubRegLiveness: false
 # CHECK: ...
 name:            foo
-body:
-  - id: 0
+body: |
+  bb.0:
 ...
 ---
 # CHECK: name: bar
@@ -35,6 +35,6 @@ name: bar
 isSSA: false
 tracksRegLiveness: true
 tracksSubRegLiveness: true
-body:
-  - id: 0
+body: |
+  bb.0:
 ...
diff --git a/test/CodeGen/MIR/NVPTX/expected-floating-point-literal.mir b/test/CodeGen/MIR/NVPTX/expected-floating-point-literal.mir
index 1a746ce802b..28fb2a2cf5c 100644
--- a/test/CodeGen/MIR/NVPTX/expected-floating-point-literal.mir
+++ b/test/CodeGen/MIR/NVPTX/expected-floating-point-literal.mir
@@ -14,13 +14,11 @@ name:            test
 registers:
   - { id: 0, class: float32regs }
   - { id: 1, class: float32regs }
-body:
-  - id:              0
-    name:            entry
-    instructions:
-      - '%0 = LD_f32_avar 0, 4, 1, 2, 32, $test_param_0'
-# CHECK: [[@LINE+1]]:38: expected a floating point literal
-      - '%1 = FADD_rnf32ri %0, float 3'
-      - 'StoreRetvalF32 %1, 0'
-      - Return
+body: |
+  bb.0.entry:
+    %0 = LD_f32_avar 0, 4, 1, 2, 32, $test_param_0
+  ; CHECK: [[@LINE+1]]:33: expected a floating point literal
+    %1 = FADD_rnf32ri %0, float 3
+    StoreRetvalF32 %1, 0
+    Return
 ...
diff --git a/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir b/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir
index 3b2ae0f99ee..18866d58a94 100644
--- a/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir
+++ b/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir
@@ -38,22 +38,20 @@ registers:
   - { id: 5, class: float32regs }
   - { id: 6, class: float32regs }
   - { id: 7, class: float32regs }
-body:
-  - id:              0
-    name:            entry
-    instructions:
-      - '%0 = LD_f32_avar 0, 4, 1, 2, 32, $test_param_0'
-      - '%1 = CVT_f64_f32 %0, 0'
-      - '%2 = LD_i32_avar 0, 4, 1, 0, 32, $test_param_1'
-# CHECK: %3 = FADD_rnf64ri %1, double 3.250000e+00
-      - '%3 = FADD_rnf64ri %1, double 3.250000e+00'
-      - '%4 = CVT_f32_f64 %3, 5'
-      - '%5 = CVT_f32_s32 %2, 5'
-# CHECK: %6 = FADD_rnf32ri %5, float 6.250000e+00
-      - '%6 = FADD_rnf32ri %5, float 6.250000e+00'
-      - '%7 = FMUL_rnf32rr %6, %4'
-      - 'StoreRetvalF32 %7, 0'
-      - Return
+body: |
+  bb.0.entry:
+    %0 = LD_f32_avar 0, 4, 1, 2, 32, $test_param_0
+    %1 = CVT_f64_f32 %0, 0
+    %2 = LD_i32_avar 0, 4, 1, 0, 32, $test_param_1
+  ; CHECK: %3 = FADD_rnf64ri %1, double 3.250000e+00
+    %3 = FADD_rnf64ri %1, double 3.250000e+00
+    %4 = CVT_f32_f64 %3, 5
+    %5 = CVT_f32_s32 %2, 5
+  ; CHECK: %6 = FADD_rnf32ri %5, float 6.250000e+00
+    %6 = FADD_rnf32ri %5, float 6.250000e+00
+    %7 = FMUL_rnf32rr %6, %4
+    StoreRetvalF32 %7, 0
+    Return
 ...
 ---
 name:            test2
@@ -66,20 +64,18 @@ registers:
   - { id: 5, class: float32regs }
   - { id: 6, class: float32regs }
   - { id: 7, class: float32regs }
-body:
-  - id:              0
-    name:            entry
-    instructions:
-      - '%0 = LD_f32_avar 0, 4, 1, 2, 32, $test2_param_0'
-      - '%1 = CVT_f64_f32 %0, 0'
-      - '%2 = LD_i32_avar 0, 4, 1, 0, 32, $test2_param_1'
-# CHECK: %3 = FADD_rnf64ri %1, double 0x7FF8000000000000
-      - '%3 = FADD_rnf64ri %1, double 0x7FF8000000000000'
-      - '%4 = CVT_f32_f64 %3, 5'
-      - '%5 = CVT_f32_s32 %2, 5'
-# CHECK: %6 = FADD_rnf32ri %5, float 0x7FF8000000000000
-      - '%6 = FADD_rnf32ri %5, float 0x7FF8000000000000'
-      - '%7 = FMUL_rnf32rr %6, %4'
-      - 'StoreRetvalF32 %7, 0'
-      - Return
+body: |
+  bb.0.entry:
+    %0 = LD_f32_avar 0, 4, 1, 2, 32, $test2_param_0
+    %1 = CVT_f64_f32 %0, 0
+    %2 = LD_i32_avar 0, 4, 1, 0, 32, $test2_param_1
+  ; CHECK: %3 = FADD_rnf64ri %1, double 0x7FF8000000000000
+    %3 = FADD_rnf64ri %1, double 0x7FF8000000000000
+    %4 = CVT_f32_f64 %3, 5
+    %5 = CVT_f32_s32 %2, 5
+  ; CHECK: %6 = FADD_rnf32ri %5, float 0x7FF8000000000000
+    %6 = FADD_rnf32ri %5, float 0x7FF8000000000000
+    %7 = FMUL_rnf32rr %6, %4
+    StoreRetvalF32 %7, 0
+    Return
 ...
diff --git a/test/CodeGen/MIR/NVPTX/floating-point-invalid-type-error.mir b/test/CodeGen/MIR/NVPTX/floating-point-invalid-type-error.mir
index 810fa15bedd..e4080f80ee5 100644
--- a/test/CodeGen/MIR/NVPTX/floating-point-invalid-type-error.mir
+++ b/test/CodeGen/MIR/NVPTX/floating-point-invalid-type-error.mir
@@ -14,13 +14,11 @@ name:            test
 registers:
   - { id: 0, class: float32regs }
   - { id: 1, class: float32regs }
-body:
-  - id:              0
-    name:            entry
-    instructions:
-      - '%0 = LD_f32_avar 0, 4, 1, 2, 32, $test_param_0'
-# CHECK: [[@LINE+1]]:38: floating point constant does not have type 'float'
-      - '%1 = FADD_rnf32ri %0, float 0xH3C00'
-      - 'StoreRetvalF32 %1, 0'
-      - Return
+body: |
+  bb.0.entry:
+    %0 = LD_f32_avar 0, 4, 1, 2, 32, $test_param_0
+  ; CHECK: [[@LINE+1]]:33: floating point constant does not have type 'float'
+    %1 = FADD_rnf32ri %0, float 0xH3C00
+    StoreRetvalF32 %1, 0
+    Return
 ...
diff --git a/test/CodeGen/MIR/X86/basic-block-liveins.mir b/test/CodeGen/MIR/X86/basic-block-liveins.mir
index d749a052442..00732975495 100644
--- a/test/CodeGen/MIR/X86/basic-block-liveins.mir
+++ b/test/CodeGen/MIR/X86/basic-block-liveins.mir
@@ -9,17 +9,54 @@
     ret i32 %c
   }
 
+  define i32 @test2(i32 %a, i32 %b) {
+  body:
+    %c = add i32 %a, %b
+    ret i32 %c
+  }
+
+  define i32 @test3() {
+  body:
+    ret i32 0
+  }
+
 ...
 ---
 name:            test
-body:
-  # CHECK: name: body
-  # CHECK: liveins: [ '%edi', '%esi' ]
-  # CHECK-NEXT: instructions:
-  - id:          0
-    name:        body
-    liveins:     [ '%edi', '%esi' ]
-    instructions:
-      - '%eax = LEA64_32r killed %rdi, 1, killed %rsi, 0, _'
-      - 'RETQ %eax'
+body: |
+  ; CHECK-LABEL: bb.0.body:
+  ; CHECK-NEXT:    liveins: %edi, %esi
+  bb.0.body:
+    liveins: %edi, %esi
+
+    %eax = LEA64_32r killed %rdi, 1, killed %rsi, 0, _
+    RETQ %eax
+...
+---
+name:            test2
+body: |
+  ; CHECK-LABEL: name: test2
+  ; Verify that we can have multiple lists of liveins that will be merged into
+  ; one.
+  ; CHECK:       bb.0.body:
+  ; CHECK-NEXT:    liveins: %edi, %esi
+  bb.0.body:
+    liveins: %edi
+    liveins: %esi
+
+    %eax = LEA64_32r killed %rdi, 1, killed %rsi, 0, _
+    RETQ %eax
+...
+---
+name:            test3
+body: |
+  ; Verify that we can have an empty list of liveins.
+  ; CHECK-LABEL: name: test3
+  ; CHECK:       bb.0.body:
+  ; CHECK-NEXT:    %eax = MOV32r0 implicit-def dead %eflags
+  bb.0.body:
+    liveins:
+
+    %eax = MOV32r0 implicit-def dead %eflags
+    RETQ killed %eax
 ...
diff --git a/test/CodeGen/MIR/X86/basic-block-not-at-start-of-line-error.mir b/test/CodeGen/MIR/X86/basic-block-not-at-start-of-line-error.mir
new file mode 100644
index 00000000000..b4b7dddea56
--- /dev/null
+++ b/test/CodeGen/MIR/X86/basic-block-not-at-start-of-line-error.mir
@@ -0,0 +1,41 @@
+# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s
+
+--- |
+
+  define i32 @foo(i32 %a) {
+  entry:
+    %0 = icmp sle i32 %a, 10
+    br i1 %0, label %less, label %exit
+
+  less:                                             ; preds = %entry
+    ret i32 0
+
+  exit:                                             ; preds = %entry
+    ret i32 %a
+  }
+
+...
+---
+name:            foo
+tracksRegLiveness: true
+liveins:
+  - { reg: '%edi' }
+body: |
+  bb.0.entry:
+    successors: %bb.1.less, %bb.2.exit
+    liveins: %edi 44
+
+    CMP32ri8 %edi, 10, implicit-def %eflags
+    JG_1 %bb.2.exit, implicit killed %eflags
+
+  ; CHECK: [[@LINE+1]]:8: basic block definition should be located at the start of the line
+  less bb.1:
+    %eax = MOV32r0 implicit-def dead %eflags
+    RETQ killed %eax
+
+  bb.2.exit:
+    liveins: %edi
+
+    %eax = COPY killed %edi
+    RETQ killed %eax
+...
diff --git a/test/CodeGen/MIR/X86/block-address-operands.mir b/test/CodeGen/MIR/X86/block-address-operands.mir
index 67e298e4932..3c2d2aefff2 100644
--- a/test/CodeGen/MIR/X86/block-address-operands.mir
+++ b/test/CodeGen/MIR/X86/block-address-operands.mir
@@ -54,84 +54,68 @@
 ...
 ---
 name:            test
-body:
-  - id:              0
-    name:            entry
-    successors:      [ '%bb.1.block' ]
-    instructions:
-    # CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block), _
-      - '%rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block), _'
-      - 'MOV64mr %rip, 1, _, @addr, _, killed %rax'
-      - 'JMP64m %rip, 1, _, @addr, _'
-  - id:              1
-    name:            block
-    addressTaken:    true
-    instructions:
-      - RETQ
+body: |
+  bb.0.entry:
+    successors: %bb.1.block
+  ; CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block), _
+    %rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block), _
+    MOV64mr %rip, 1, _, @addr, _, killed %rax
+    JMP64m %rip, 1, _, @addr, _
+
+  bb.1.block (address-taken):
+    RETQ
 ...
 ---
 name:            test2
 tracksRegLiveness: true
-body:
-  - id:              0
-    name:            entry
-    successors:      [ '%bb.1' ]
-    instructions:
-    # CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test2, %ir-block."quoted block"), _
-      - '%rax = LEA64r %rip, 1, _, blockaddress(@test2, %ir-block."quoted block"), _'
-      - 'MOV64mr %rip, 1, _, @addr, _, killed %rax'
-      - 'JMP64m %rip, 1, _, @addr, _'
-  - id:              1
-    addressTaken:    true
-    instructions:
-      - RETQ
+body: |
+  bb.0.entry:
+    successors: %bb.1
+  ; CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test2, %ir-block."quoted block"), _
+    %rax = LEA64r %rip, 1, _, blockaddress(@test2, %ir-block."quoted block"), _
+    MOV64mr %rip, 1, _, @addr, _, killed %rax
+    JMP64m %rip, 1, _, @addr, _
+
+  bb.1 (address-taken):
+    RETQ
 ...
 ---
 name:            slot_in_other_function
 tracksRegLiveness: true
-body:
-  - id:              0
-    name:            entry
-    liveins:         [ '%rdi' ]
-    instructions:
-# CHECK: name: slot_in_other_function
-# CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _
-      - '%rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _'
-      - 'MOV64mr killed %rdi, 1, _, 0, _, killed %rax'
-      - RETQ
+body: |
+  bb.0.entry:
+    liveins: %rdi
+  ; CHECK-LABEL: name: slot_in_other_function
+  ; CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _
+    %rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _
+    MOV64mr killed %rdi, 1, _, 0, _, killed %rax
+    RETQ
 ...
 ---
 name:            test3
 tracksRegLiveness: true
-body:
-  - id:              0
-    name:            entry
-    successors:      [ '%bb.1' ]
-    instructions:
-# CHECK: name: test3
-# CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _
-      - '%rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _'
-      - 'MOV64mr %rip, 1, _, @addr, _, killed %rax'
-      - 'JMP64m %rip, 1, _, @addr, _'
-  - id:              1
-    addressTaken:    true
-    instructions:
-      - RETQ
+body: |
+  bb.0.entry:
+    successors: %bb.1
+  ; CHECK-LABEL: name: test3
+  ; CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _
+    %rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _
+    MOV64mr %rip, 1, _, @addr, _, killed %rax
+    JMP64m %rip, 1, _, @addr, _
+
+  bb.1 (address-taken):
+    RETQ
 ...
 ---
 name:            test4
-body:
-  - id:              0
-    name:            entry
-    successors:      [ '%bb.1.block' ]
-    instructions:
-    # CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block) + 2, _
-      - '%rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block) + 2, _'
-      - 'MOV64mr %rip, 1, _, @addr, _, killed %rax'
-      - 'JMP64m %rip, 1, _, @addr, _'
-  - id:              1
-    name:            block
-    addressTaken:    true
-    instructions:
-      - RETQ
+body: |
+  bb.0.entry:
+    successors: %bb.1.block
+  ; CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block) + 2, _
+    %rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block) + 2, _
+    MOV64mr %rip, 1, _, @addr, _, killed %rax
+    JMP64m %rip, 1, _, @addr, _
+
+  bb.1.block (address-taken):
+    RETQ
 ...
diff --git a/test/CodeGen/MIR/X86/callee-saved-info.mir b/test/CodeGen/MIR/X86/callee-saved-info.mir
index 4ec5b50c364..17c7739951d 100644
--- a/test/CodeGen/MIR/X86/callee-saved-info.mir
+++ b/test/CodeGen/MIR/X86/callee-saved-info.mir
@@ -34,13 +34,12 @@
 ---
 name:            compute
 tracksRegLiveness: true
-body:
-  - id:          0
-    name:        body
-    liveins:     [ '%edi' ]
-    instructions:
-      - '%eax = COPY killed %edi'
-      - 'RETQ killed %eax'
+body: |
+  bb.0.body:
+    liveins: %edi
+
+    %eax = COPY killed %edi
+    RETQ killed %eax
 ...
 ---
 name:            func
@@ -60,39 +59,37 @@ fixedStack:
 stack:
   - { id: 0, name: b, offset: -20, size: 4, alignment: 4 }
   - { id: 1, offset: -24, size: 4, alignment: 4, callee-saved-register: '%edi' }
-body:
-  - id:          0
-    name:        entry
-    successors:  [ '%bb.1.check' ]
-    liveins:     [ '%edi', '%rbx' ]
-    instructions:
-      - 'frame-setup PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp'
-      - '%rsp = frame-setup SUB64ri8 %rsp, 16, implicit-def dead %eflags'
-      - '%ebx = COPY %edi'
-      - 'MOV32mr %rsp, 1, _, 12, _, %ebx'
-  - id:          1
-    name:        check
-    successors:  [ '%bb.2.loop', '%bb.3.exit' ]
-    liveins:     [ '%ebx' ]
-    instructions:
-      - 'CMP32ri8 %ebx, 10, implicit-def %eflags'
-      - 'JG_1 %bb.3.exit, implicit killed %eflags'
-      - 'JMP_1 %bb.2.loop'
-  - id:          2
-    name:        loop
-    successors:  [ '%bb.1.check' ]
-    liveins:     [ '%ebx' ]
-    instructions:
-      - '%edi = MOV32rm %rsp, 1, _, 12, _'
-      - 'CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax'
-      - '%eax = DEC32r killed %eax, implicit-def dead %eflags'
-      - 'MOV32mr %rsp, 1, _, 12, _, killed %eax'
-      - 'JMP_1 %bb.1.check'
-  - id:          3
-    name:        exit
-    instructions:
-      - '%eax = MOV32r0 implicit-def dead %eflags'
-      - '%rsp = ADD64ri8 %rsp, 16, implicit-def dead %eflags'
-      - '%rbx = POP64r implicit-def %rsp, implicit %rsp'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    successors: %bb.1.check
+    liveins: %edi, %rbx
+
+    frame-setup PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp
+    %rsp = frame-setup SUB64ri8 %rsp, 16, implicit-def dead %eflags
+    %ebx = COPY %edi
+    MOV32mr %rsp, 1, _, 12, _, %ebx
+
+  bb.1.check:
+    successors: %bb.2.loop, %bb.3.exit
+    liveins: %ebx
+
+    CMP32ri8 %ebx, 10, implicit-def %eflags
+    JG_1 %bb.3.exit, implicit killed %eflags
+    JMP_1 %bb.2.loop
+
+  bb.2.loop:
+    successors: %bb.1.check
+    liveins: %ebx
+
+    %edi = MOV32rm %rsp, 1, _, 12, _
+    CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax
+    %eax = DEC32r killed %eax, implicit-def dead %eflags
+    MOV32mr %rsp, 1, _, 12, _, killed %eax
+    JMP_1 %bb.1.check
+
+  bb.3.exit:
+    %eax = MOV32r0 implicit-def dead %eflags
+    %rsp = ADD64ri8 %rsp, 16, implicit-def dead %eflags
+    %rbx = POP64r implicit-def %rsp, implicit %rsp
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/cfi-def-cfa-offset.mir b/test/CodeGen/MIR/X86/cfi-def-cfa-offset.mir
index 3fb5395602d..47051a53e3f 100644
--- a/test/CodeGen/MIR/X86/cfi-def-cfa-offset.mir
+++ b/test/CodeGen/MIR/X86/cfi-def-cfa-offset.mir
@@ -18,14 +18,12 @@ frameInfo:
   stackSize:       4040
 stack:
   - { id: 0, name: tmp, offset: -4176, size: 4168, alignment: 4 }
-body:
-  - id:              0
-    name:            entry
-    instructions:
-      - '%rsp = SUB64ri32 %rsp, 4040, implicit-def dead %eflags'
-     # CHECK: CFI_INSTRUCTION .cfi_def_cfa_offset 4048
-      - 'CFI_INSTRUCTION .cfi_def_cfa_offset 4048'
-      - '%rsp = ADD64ri32 %rsp, 4040, implicit-def dead %eflags'
-      - 'RETQ'
+body: |
+  bb.0.entry:
+    %rsp = SUB64ri32 %rsp, 4040, implicit-def dead %eflags
+    ; CHECK: CFI_INSTRUCTION .cfi_def_cfa_offset 4048
+    CFI_INSTRUCTION .cfi_def_cfa_offset 4048
+    %rsp = ADD64ri32 %rsp, 4040, implicit-def dead %eflags
+    RETQ
 ...
 
diff --git a/test/CodeGen/MIR/X86/cfi-def-cfa-register.mir b/test/CodeGen/MIR/X86/cfi-def-cfa-register.mir
index aad546494d7..74a33b5c343 100644
--- a/test/CodeGen/MIR/X86/cfi-def-cfa-register.mir
+++ b/test/CodeGen/MIR/X86/cfi-def-cfa-register.mir
@@ -19,15 +19,14 @@ frameInfo:
   stackSize:     8
 fixedStack:
   - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16 }
-body:
-  - id:          0
-    name:        entry
-    liveins:     [ '%rbp' ]
-    instructions:
-      - 'PUSH64r killed %rbp, implicit-def %rsp, implicit %rsp'
-      - 'CFI_INSTRUCTION .cfi_def_cfa_offset 16'
-      - 'CFI_INSTRUCTION .cfi_offset %rbp, -16'
-      - '%rbp = MOV64rr %rsp'
-      # CHECK: CFI_INSTRUCTION .cfi_def_cfa_register %rbp
-      - 'CFI_INSTRUCTION .cfi_def_cfa_register %rbp'
+body: |
+  bb.0.entry:
+    liveins: %rbp
+
+    PUSH64r killed %rbp, implicit-def %rsp, implicit %rsp
+    CFI_INSTRUCTION .cfi_def_cfa_offset 16
+    CFI_INSTRUCTION .cfi_offset %rbp, -16
+    %rbp = MOV64rr %rsp
+    ; CHECK: CFI_INSTRUCTION .cfi_def_cfa_register %rbp
+    CFI_INSTRUCTION .cfi_def_cfa_register %rbp
 ...
diff --git a/test/CodeGen/MIR/X86/cfi-offset.mir b/test/CodeGen/MIR/X86/cfi-offset.mir
index edfffda8641..fd9e605a036 100644
--- a/test/CodeGen/MIR/X86/cfi-offset.mir
+++ b/test/CodeGen/MIR/X86/cfi-offset.mir
@@ -26,23 +26,22 @@ frameInfo:
   hasCalls:        true
 fixedStack:
   - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16 }
-body:
-  - id:              0
-    name:            entry
-    liveins:         [ '%ecx', '%edi', '%edx', '%esi', '%rbx' ]
-    instructions:
-      - 'PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp'
-      - 'CFI_INSTRUCTION .cfi_def_cfa_offset 16'
-      # CHECK: CFI_INSTRUCTION .cfi_offset %rbx, -16
-      - 'CFI_INSTRUCTION .cfi_offset %rbx, -16'
-      - '%ebx = COPY %edi, implicit-def %rbx'
-      - '%ebx = ADD32rr %ebx, killed %esi, implicit-def dead %eflags'
-      - '%ebx = ADD32rr %ebx, killed %edx, implicit-def dead %eflags'
-      - '%ebx = ADD32rr %ebx, killed %ecx, implicit-def dead %eflags'
-      - '%edi = COPY %ebx'
-      - 'CALL64pcrel32 @foo, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp'
-      - '%eax = LEA64_32r killed %rbx, 1, %rbx, 0, _'
-      - '%rbx = POP64r implicit-def %rsp, implicit %rsp'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    liveins: %ecx, %edi, %edx, %esi, %rbx
+
+    PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp
+    CFI_INSTRUCTION .cfi_def_cfa_offset 16
+    ; CHECK: CFI_INSTRUCTION .cfi_offset %rbx, -16
+    CFI_INSTRUCTION .cfi_offset %rbx, -16
+    %ebx = COPY %edi, implicit-def %rbx
+    %ebx = ADD32rr %ebx, killed %esi, implicit-def dead %eflags
+    %ebx = ADD32rr %ebx, killed %edx, implicit-def dead %eflags
+    %ebx = ADD32rr %ebx, killed %ecx, implicit-def dead %eflags
+    %edi = COPY %ebx
+    CALL64pcrel32 @foo, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp
+    %eax = LEA64_32r killed %rbx, 1, %rbx, 0, _
+    %rbx = POP64r implicit-def %rsp, implicit %rsp
+    RETQ %eax
 ...
 
diff --git a/test/CodeGen/MIR/X86/constant-pool-item-redefinition-error.mir b/test/CodeGen/MIR/X86/constant-pool-item-redefinition-error.mir
index 0ff67302876..2ddf5736b97 100644
--- a/test/CodeGen/MIR/X86/constant-pool-item-redefinition-error.mir
+++ b/test/CodeGen/MIR/X86/constant-pool-item-redefinition-error.mir
@@ -17,11 +17,9 @@ constants:
 # CHECK: [[@LINE+1]]:18: redefinition of constant pool item '%const.0'
   - id:          0
     value:       'double 3.250000e+00'
-body:
-  - id: 0
-    name: entry
-    instructions:
-      - '%xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _'
-      - 'RETQ %xmm0'
+body: |
+  bb.0.entry:
+    %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _
+    RETQ %xmm0
 ...
 
diff --git a/test/CodeGen/MIR/X86/constant-pool.mir b/test/CodeGen/MIR/X86/constant-pool.mir
index 8e5b9b57388..213e4e28348 100644
--- a/test/CodeGen/MIR/X86/constant-pool.mir
+++ b/test/CodeGen/MIR/X86/constant-pool.mir
@@ -57,17 +57,15 @@ constants:
   - id:          1
     value:       'float 6.250000e+00'
     alignment:   4
-body:
-  - id: 0
-    name: entry
-    instructions:
-      # CHECK:      %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _
-      # CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _
-      - '%xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _'
-      - '%xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _'
-      - '%xmm1 = CVTSS2SDrr killed %xmm1'
-      - '%xmm0 = MULSDrr killed %xmm0, killed %xmm1'
-      - 'RETQ %xmm0'
+body: |
+  bb.0.entry:
+    ; CHECK:      %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _
+    ; CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _
+    %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _
+    %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _
+    %xmm1 = CVTSS2SDrr killed %xmm1
+    %xmm0 = MULSDrr killed %xmm0, killed %xmm1
+    RETQ %xmm0
 ...
 ---
 # Verify that alignment can be inferred:
@@ -85,15 +83,13 @@ constants:
     value:       'double 3.250000e+00'
   - id:          1
     value:       'float 6.250000e+00'
-body:
-  - id: 0
-    name: entry
-    instructions:
-      - '%xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _'
-      - '%xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _'
-      - '%xmm1 = CVTSS2SDrr killed %xmm1'
-      - '%xmm0 = MULSDrr killed %xmm0, killed %xmm1'
-      - 'RETQ %xmm0'
+body: |
+  bb.0.entry:
+    %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _
+    %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _
+    %xmm1 = CVTSS2SDrr killed %xmm1
+    %xmm0 = MULSDrr killed %xmm0, killed %xmm1
+    RETQ %xmm0
 ...
 ---
 # Verify that the non-standard alignments are respected:
@@ -113,17 +109,15 @@ constants:
   - id:          1
     value:       'float 6.250000e+00'
     alignment:   1
-body:
-  - id: 0
-    name: entry
-    instructions:
-      # CHECK:      %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _
-      # CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _
-      - '%xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _'
-      - '%xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _'
-      - '%xmm1 = CVTSS2SDrr killed %xmm1'
-      - '%xmm0 = MULSDrr killed %xmm0, killed %xmm1'
-      - 'RETQ %xmm0'
+body: |
+  bb.0.entry:
+    ; CHECK:      %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _
+    ; CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _
+    %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _
+    %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _
+    %xmm1 = CVTSS2SDrr killed %xmm1
+    %xmm0 = MULSDrr killed %xmm0, killed %xmm1
+    RETQ %xmm0
 ...
 ---
 # CHECK:  name:  test4
@@ -133,15 +127,13 @@ constants:
     value:       'double 3.250000e+00'
   - id:          1
     value:       'float 6.250000e+00'
-body:
-  - id: 0
-    name: entry
-    instructions:
-      # CHECK:      %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.1 - 12, _
-      # CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.0 + 8, _
-      - '%xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.1 - 12, _'
-      - '%xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.0 + 8, _'
-      - '%xmm1 = CVTSS2SDrr killed %xmm1'
-      - '%xmm0 = MULSDrr killed %xmm0, killed %xmm1'
-      - 'RETQ %xmm0'
+body: |
+  bb.0.entry:
+    ; CHECK:      %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.1 - 12, _
+    ; CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.0 + 8, _
+    %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.1 - 12, _
+    %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.0 + 8, _
+    %xmm1 = CVTSS2SDrr killed %xmm1
+    %xmm0 = MULSDrr killed %xmm0, killed %xmm1
+    RETQ %xmm0
 ...
diff --git a/test/CodeGen/MIR/X86/constant-value-error.mir b/test/CodeGen/MIR/X86/constant-value-error.mir
index d6c21107022..1e14d2282c5 100644
--- a/test/CodeGen/MIR/X86/constant-value-error.mir
+++ b/test/CodeGen/MIR/X86/constant-value-error.mir
@@ -17,11 +17,9 @@ constants:
   - id:          0
   # CHECK: [[@LINE+1]]:19: expected type
     value:       'dub 3.250000e+00'
-body:
-  - id: 0
-    name: entry
-    instructions:
-      - '%xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _'
-      - 'RETQ %xmm0'
+body: |
+  bb.0.entry:
+    %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _
+    RETQ %xmm0
 ...
 
diff --git a/test/CodeGen/MIR/X86/dead-register-flag.mir b/test/CodeGen/MIR/X86/dead-register-flag.mir
index 988b554659c..309e776de46 100644
--- a/test/CodeGen/MIR/X86/dead-register-flag.mir
+++ b/test/CodeGen/MIR/X86/dead-register-flag.mir
@@ -15,12 +15,10 @@
 ...
 ---
 name:            foo
-body:
-  # CHECK: name: body
-  - id:          0
-    name:        body
-    instructions:
-      # CHECK: - '%eax = IMUL32rri8 %edi, 11, implicit-def dead %eflags'
-      - '%eax = IMUL32rri8 %edi, 11, implicit-def dead %eflags'
-      - 'RETQ %eax'
+body: |
+  ; CHECK: bb.0.body:
+  bb.0.body:
+    ; CHECK: %eax = IMUL32rri8 %edi, 11, implicit-def dead %eflags
+    %eax = IMUL32rri8 %edi, 11, implicit-def dead %eflags
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/duplicate-memory-operand-flag.mir b/test/CodeGen/MIR/X86/duplicate-memory-operand-flag.mir
index f608195387f..7d01810c792 100644
--- a/test/CodeGen/MIR/X86/duplicate-memory-operand-flag.mir
+++ b/test/CodeGen/MIR/X86/duplicate-memory-operand-flag.mir
@@ -16,14 +16,12 @@ name:            volatile_inc
 tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
-body:
-  - id:          0
-    name:        entry
-    liveins:     [ '%rdi' ]
-    instructions:
-# CHECK: [[@LINE+1]]:55: duplicate 'volatile' memory operand flag
-      - '%eax = MOV32rm %rdi, 1, _, 0, _ :: (volatile volatile load 4 from %ir.x)'
-      - '%eax = INC32r killed %eax, implicit-def dead %eflags'
-      - 'MOV32mr killed %rdi, 1, _, 0, _, %eax :: (volatile store 4 into %ir.x)'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    liveins: %rdi
+  ; CHECK: [[@LINE+1]]:50: duplicate 'volatile' memory operand flag
+    %eax = MOV32rm %rdi, 1, _, 0, _ :: (volatile volatile load 4 from %ir.x)
+    %eax = INC32r killed %eax, implicit-def dead %eflags
+    MOV32mr killed %rdi, 1, _, 0, _, %eax :: (volatile store 4 into %ir.x)
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/duplicate-register-flag-error.mir b/test/CodeGen/MIR/X86/duplicate-register-flag-error.mir
index f9570a44ccc..d80c6ed061d 100644
--- a/test/CodeGen/MIR/X86/duplicate-register-flag-error.mir
+++ b/test/CodeGen/MIR/X86/duplicate-register-flag-error.mir
@@ -17,22 +17,19 @@
 ...
 ---
 name:            foo
-body:
-  - id:          0
-    name:        entry
-    successors:  [ '%bb.1.less', '%bb.2.exit' ]
-    instructions:
-      - 'CMP32ri8 %edi, 10, implicit-def %eflags'
-# CHECK: [[@LINE+1]]:36: duplicate 'implicit' register flag
-      - 'JG_1 %bb.2.exit, implicit implicit %eflags'
-  - id:          1
-    name:        less
-    instructions:
-      - '%eax = MOV32r0 implicit-def %eflags'
-      - 'RETQ %eax'
-  - id:          2
-    name:        exit
-    instructions:
-      - '%eax = COPY %edi'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    successors: %bb.1.less, %bb.2.exit
+
+    CMP32ri8 %edi, 10, implicit-def %eflags
+  ; CHECK: [[@LINE+1]]:31: duplicate 'implicit' register flag
+    JG_1 %bb.2.exit, implicit implicit %eflags
+
+  bb.1.less:
+    %eax = MOV32r0 implicit-def %eflags
+    RETQ %eax
+
+  bb.2.exit:
+    %eax = COPY %edi
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/early-clobber-register-flag.mir b/test/CodeGen/MIR/X86/early-clobber-register-flag.mir
index ce2e509e7c1..4dc442e4fb9 100644
--- a/test/CodeGen/MIR/X86/early-clobber-register-flag.mir
+++ b/test/CodeGen/MIR/X86/early-clobber-register-flag.mir
@@ -28,19 +28,18 @@ frameInfo:
   stackSize:     8
   adjustsStack:  true
   hasCalls:      true
-body:
-  - id:          0
-    name:        entry
-    liveins:     [ '%edi', '%esi' ]
-    instructions:
-      - 'frame-setup PUSH64r undef %rax, implicit-def %rsp, implicit %rsp'
-      - CFI_INSTRUCTION .cfi_def_cfa_offset 16
-      - '%ecx = COPY %edi'
-      - '%ecx = ADD32rr killed %ecx, killed %esi, implicit-def dead %eflags'
-# CHECK: INLINEASM $nop, 1, 12, implicit-def dead early-clobber %ax, 12, implicit-def dead early-clobber %di
-      - 'INLINEASM $nop, 1, 12, implicit-def dead early-clobber %ax, 12, implicit-def dead early-clobber %di'
-      - '%edi = COPY killed %ecx'
-      - 'CALL64pcrel32 @foo, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp'
-      - '%rax = POP64r implicit-def %rsp, implicit %rsp'
-      - RETQ
+body: |
+  bb.0.entry:
+    liveins: %edi, %esi
+
+    frame-setup PUSH64r undef %rax, implicit-def %rsp, implicit %rsp
+    CFI_INSTRUCTION .cfi_def_cfa_offset 16
+    %ecx = COPY %edi
+    %ecx = ADD32rr killed %ecx, killed %esi, implicit-def dead %eflags
+  ; CHECK: INLINEASM $nop, 1, 12, implicit-def dead early-clobber %ax, 12, implicit-def dead early-clobber %di
+    INLINEASM $nop, 1, 12, implicit-def dead early-clobber %ax, 12, implicit-def dead early-clobber %di
+    %edi = COPY killed %ecx
+    CALL64pcrel32 @foo, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp
+    %rax = POP64r implicit-def %rsp, implicit %rsp
+    RETQ
 ...
diff --git a/test/CodeGen/MIR/X86/expected-align-in-memory-operand.mir b/test/CodeGen/MIR/X86/expected-align-in-memory-operand.mir
index b11734e5d90..f2e349454c5 100644
--- a/test/CodeGen/MIR/X86/expected-align-in-memory-operand.mir
+++ b/test/CodeGen/MIR/X86/expected-align-in-memory-operand.mir
@@ -16,17 +16,15 @@ name:            memory_alignment
 tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
-body:
-  - id:          0
-    name:        entry
-    liveins:     [ '%rdi' ]
-    instructions:
-# CHECK: [[@LINE+1]]:70: expected 'align'
-      - '%xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, 32)'
-      - '%xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32)'
-      - '%xmm2 = FsFLD0SS'
-      - '%xmm1 = MOVSSrr killed %xmm1, killed %xmm2'
-      - 'MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec, align 32)'
-      - 'MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32)'
-      - RETQ
+body: |
+  bb.0.entry:
+    liveins: %rdi
+  ; CHECK: [[@LINE+1]]:65: expected 'align'
+    %xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, 32)
+    %xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32)
+    %xmm2 = FsFLD0SS
+    %xmm1 = MOVSSrr killed %xmm1, killed %xmm2
+    MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec, align 32)
+    MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32)
+    RETQ
 ...
diff --git a/test/CodeGen/MIR/X86/expected-alignment-after-align-in-memory-operand.mir b/test/CodeGen/MIR/X86/expected-alignment-after-align-in-memory-operand.mir
index 19ed8e8544e..7ce377f8c5f 100644
--- a/test/CodeGen/MIR/X86/expected-alignment-after-align-in-memory-operand.mir
+++ b/test/CodeGen/MIR/X86/expected-alignment-after-align-in-memory-operand.mir
@@ -16,17 +16,15 @@ name:            memory_alignment
 tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
-body:
-  - id:          0
-    name:        entry
-    liveins:     [ '%rdi' ]
-    instructions:
-# CHECK: [[@LINE+1]]:75: expected an integer literal after 'align'
-      - '%xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, align)'
-      - '%xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32)'
-      - '%xmm2 = FsFLD0SS'
-      - '%xmm1 = MOVSSrr killed %xmm1, killed %xmm2'
-      - 'MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec, align 32)'
-      - 'MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32)'
-      - RETQ
+body: |
+  bb.0.entry:
+    liveins: %rdi
+  ; CHECK: [[@LINE+1]]:70: expected an integer literal after 'align'
+    %xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, align)
+    %xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32)
+    %xmm2 = FsFLD0SS
+    %xmm1 = MOVSSrr killed %xmm1, killed %xmm2
+    MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec, align 32)
+    MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32)
+    RETQ
 ...
diff --git a/test/CodeGen/MIR/X86/expected-basic-block-at-start-of-body.mir b/test/CodeGen/MIR/X86/expected-basic-block-at-start-of-body.mir
new file mode 100644
index 00000000000..861baec4bcb
--- /dev/null
+++ b/test/CodeGen/MIR/X86/expected-basic-block-at-start-of-body.mir
@@ -0,0 +1,40 @@
+# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s
+
+--- |
+
+  define i32 @foo(i32 %a) {
+  entry:
+    %0 = icmp sle i32 %a, 10
+    br i1 %0, label %less, label %exit
+
+  less:                                             ; preds = %entry
+    ret i32 0
+
+  exit:                                             ; preds = %entry
+    ret i32 %a
+  }
+
+...
+---
+name:            foo
+tracksRegLiveness: true
+liveins:
+  - { reg: '%edi' }
+body: |
+  ; CHECK: [[@LINE+1]]:3: expected a basic block definition before instructions
+  successors: %bb.1.less, %bb.2.exit
+    liveins: %edi 44
+
+    CMP32ri8 %edi, 10, implicit-def %eflags
+    JG_1 %bb.2.exit, implicit killed %eflags
+
+  bb.1.less:
+    %eax = MOV32r0 implicit-def dead %eflags
+    RETQ killed %eax
+
+  bb.2.exit:
+    liveins: %edi
+
+    %eax = COPY killed %edi
+    RETQ killed %eax
+...
diff --git a/test/CodeGen/MIR/X86/expected-block-reference-in-blockaddress.mir b/test/CodeGen/MIR/X86/expected-block-reference-in-blockaddress.mir
index 2d4f5fac60b..ef7df4c8c20 100644
--- a/test/CodeGen/MIR/X86/expected-block-reference-in-blockaddress.mir
+++ b/test/CodeGen/MIR/X86/expected-block-reference-in-blockaddress.mir
@@ -17,18 +17,14 @@
 ...
 ---
 name:            test
-body:
-  - id:              0
-    name:            entry
-    successors:      [ '%bb.1.block' ]
-    instructions:
-      # CHECK: [[@LINE+1]]:56: expected an IR block reference
-      - '%rax = LEA64r %rip, 1, _, blockaddress(@test, _), _'
-      - 'MOV64mr %rip, 1, _, @addr, _, killed %rax'
-      - 'JMP64m %rip, 1, _, @addr, _'
-  - id:              1
-    name:            block
-    addressTaken:    true
-    instructions:
-      - RETQ
+body: |
+  bb.0.entry:
+    successors: %bb.1.block
+    ; CHECK: [[@LINE+1]]:51: expected an IR block reference
+    %rax = LEA64r %rip, 1, _, blockaddress(@test, _), _
+    MOV64mr %rip, 1, _, @addr, _, killed %rax
+    JMP64m %rip, 1, _, @addr, _
+
+  bb.1.block (address-taken):
+    RETQ
 ...
diff --git a/test/CodeGen/MIR/X86/expected-comma-after-cfi-register.mir b/test/CodeGen/MIR/X86/expected-comma-after-cfi-register.mir
index 8c4eac037fa..ba7b2ab64c3 100644
--- a/test/CodeGen/MIR/X86/expected-comma-after-cfi-register.mir
+++ b/test/CodeGen/MIR/X86/expected-comma-after-cfi-register.mir
@@ -24,21 +24,19 @@ frameInfo:
   hasCalls:        true
 fixedStack:
   - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16 }
-body:
-  - id:              0
-    name:            entry
-    instructions:
-      - 'PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp'
-      - 'CFI_INSTRUCTION .cfi_def_cfa_offset 16'
-      # CHECK: [[@LINE+1]]:43: expected ','
-      - 'CFI_INSTRUCTION .cfi_offset %rbx -16'
-      - '%ebx = COPY %edi, implicit-def %rbx'
-      - '%ebx = ADD32rr %ebx, killed %esi, implicit-def dead %eflags'
-      - '%ebx = ADD32rr %ebx, killed %edx, implicit-def dead %eflags'
-      - '%ebx = ADD32rr %ebx, killed %ecx, implicit-def dead %eflags'
-      - '%edi = COPY %ebx'
-      - 'CALL64pcrel32 @foo, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp'
-      - '%eax = LEA64_32r killed %rbx, 1, %rbx, 0, _'
-      - '%rbx = POP64r implicit-def %rsp, implicit %rsp'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp
+    CFI_INSTRUCTION .cfi_def_cfa_offset 16
+    ; CHECK: [[@LINE+1]]:38: expected ','
+    CFI_INSTRUCTION .cfi_offset %rbx -16
+    %ebx = COPY %edi, implicit-def %rbx
+    %ebx = ADD32rr %ebx, killed %esi, implicit-def dead %eflags
+    %ebx = ADD32rr %ebx, killed %edx, implicit-def dead %eflags
+    %ebx = ADD32rr %ebx, killed %ecx, implicit-def dead %eflags
+    %edi = COPY %ebx
+    CALL64pcrel32 @foo, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp
+    %eax = LEA64_32r killed %rbx, 1, %rbx, 0, _
+    %rbx = POP64r implicit-def %rsp, implicit %rsp
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/expected-comma-after-memory-operand.mir b/test/CodeGen/MIR/X86/expected-comma-after-memory-operand.mir
index da83340b2e2..dd569395257 100644
--- a/test/CodeGen/MIR/X86/expected-comma-after-memory-operand.mir
+++ b/test/CodeGen/MIR/X86/expected-comma-after-memory-operand.mir
@@ -16,12 +16,10 @@ name:            test
 tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
-body:
-  - id:          0
-    name:        entry2
-    liveins:     [ '%rdi' ]
-    instructions:
-# CHECK: [[@LINE+1]]:92: expected ',' before the next machine memory operand
-      - 'INC32m killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (store 4 into %ir.a) (load 4 from %ir.a)'
-      - RETQ
+body: |
+  bb.0.entry2:
+    liveins: %rdi
+  ; CHECK: [[@LINE+1]]:87: expected ',' before the next machine memory operand
+    INC32m killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (store 4 into %ir.a) (load 4 from %ir.a)
+    RETQ
 ...
diff --git a/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir b/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir
index c5f5aaca34e..d2c55bdc7b8 100644
--- a/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir
+++ b/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir
@@ -19,20 +19,16 @@
 ...
 ---
 name:            foo
-body:
- - id:              0
-   name:            entry
-   instructions:
-     - '%eax = MOV32rm %rdi, 1, _, 0, _'
-     - 'CMP32ri8 %eax, 10, implicit-def %eflags'
-# CHECK: [[@LINE+1]]:26: expected an implicit register operand 'implicit %eflags'
-     - 'JG_1 %bb.2.exit, implicit %eax'
- - id:              1
-   name:            less
-   instructions:
-     - '%eax = MOV32r0 implicit-def %eflags'
- - id:              2
-   name:            exit
-   instructions:
-     - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    %eax = MOV32rm %rdi, 1, _, 0, _
+    CMP32ri8 %eax, 10, implicit-def %eflags
+  ; CHECK: [[@LINE+1]]:22: expected an implicit register operand 'implicit %eflags'
+    JG_1 %bb.2.exit, implicit %eax
+
+  bb.1.less:
+    %eax = MOV32r0 implicit-def %eflags
+
+  bb.2.exit:
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir b/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir
index ecf3a122bf6..6a7201193a0 100644
--- a/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir
+++ b/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir
@@ -19,20 +19,16 @@
 ...
 ---
 name:            foo
-body:
- - id:              0
-   name:            entry
-   instructions:
-     - '%eax = MOV32rm %rdi, 1, _, 0, _'
-     - 'CMP32ri8 %eax, 10, implicit-def %eflags'
-# CHECK: [[@LINE+1]]:26: expected an implicit register operand 'implicit %eflags'
-     - 'JG_1 %bb.2.exit, implicit-def %eflags'
- - id:              1
-   name:            less
-   instructions:
-     - '%eax = MOV32r0 implicit-def %eflags'
- - id:              2
-   name:            exit
-   instructions:
-     - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    %eax = MOV32rm %rdi, 1, _, 0, _
+    CMP32ri8 %eax, 10, implicit-def %eflags
+  ; CHECK: [[@LINE+1]]:22: expected an implicit register operand 'implicit %eflags'
+    JG_1 %bb.2.exit, implicit-def %eflags
+
+  bb.1.less:
+    %eax = MOV32r0 implicit-def %eflags
+
+  bb.2.exit:
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/expected-from-in-memory-operand.mir b/test/CodeGen/MIR/X86/expected-from-in-memory-operand.mir
index d0f83f25716..f9e9d0b2296 100644
--- a/test/CodeGen/MIR/X86/expected-from-in-memory-operand.mir
+++ b/test/CodeGen/MIR/X86/expected-from-in-memory-operand.mir
@@ -14,13 +14,11 @@ name:            test
 tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
-body:
-  - id:          0
-    name:        entry
-    liveins:     [ '%rdi' ]
-    instructions:
-# CHECK: [[@LINE+1]]:60: expected 'from'
-      - '%eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 %ir.a)'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    liveins: %rdi
+  ; CHECK: [[@LINE+1]]:55: expected 'from'
+    %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 %ir.a)
+    RETQ %eax
 ...
 
diff --git a/test/CodeGen/MIR/X86/expected-function-reference-after-blockaddress.mir b/test/CodeGen/MIR/X86/expected-function-reference-after-blockaddress.mir
index 0b8fe36c025..de6a745fd70 100644
--- a/test/CodeGen/MIR/X86/expected-function-reference-after-blockaddress.mir
+++ b/test/CodeGen/MIR/X86/expected-function-reference-after-blockaddress.mir
@@ -17,18 +17,14 @@
 ...
 ---
 name:            test
-body:
-  - id:              0
-    name:            entry
-    successors:      [ '%bb.1.block' ]
-    instructions:
-      # CHECK: [[@LINE+1]]:49: expected an IR function reference
-      - '%rax = LEA64r %rip, 1, _, blockaddress(@addr, %ir-block.block), _'
-      - 'MOV64mr %rip, 1, _, @addr, _, killed %rax'
-      - 'JMP64m %rip, 1, _, @addr, _'
-  - id:              1
-    name:            block
-    addressTaken:    true
-    instructions:
-      - RETQ
+body: |
+  bb.0.entry:
+    successors: %bb.1.block
+    ; CHECK: [[@LINE+1]]:44: expected an IR function reference
+    %rax = LEA64r %rip, 1, _, blockaddress(@addr, %ir-block.block), _
+    MOV64mr %rip, 1, _, @addr, _, killed %rax
+    JMP64m %rip, 1, _, @addr, _
+
+  bb.1.block (address-taken):
+    RETQ
 ...
diff --git a/test/CodeGen/MIR/X86/expected-global-value-after-blockaddress.mir b/test/CodeGen/MIR/X86/expected-global-value-after-blockaddress.mir
index a42a26cb07c..f737c06c3e1 100644
--- a/test/CodeGen/MIR/X86/expected-global-value-after-blockaddress.mir
+++ b/test/CodeGen/MIR/X86/expected-global-value-after-blockaddress.mir
@@ -17,18 +17,14 @@
 ...
 ---
 name:            test
-body:
-  - id:              0
-    name:            entry
-    successors:      [ '%bb.1.block' ]
-    instructions:
-      # CHECK: [[@LINE+1]]:49: expected a global value
-      - '%rax = LEA64r %rip, 1, _, blockaddress(0, %ir-block.block), _'
-      - 'MOV64mr %rip, 1, _, @addr, _, killed %rax'
-      - 'JMP64m %rip, 1, _, @addr, _'
-  - id:              1
-    name:            block
-    addressTaken:    true
-    instructions:
-      - RETQ
+body: |
+  bb.0.entry:
+    successors: %bb.1.block
+    ; CHECK: [[@LINE+1]]:44: expected a global value
+    %rax = LEA64r %rip, 1, _, blockaddress(0, %ir-block.block), _
+    MOV64mr %rip, 1, _, @addr, _, killed %rax
+    JMP64m %rip, 1, _, @addr, _
+
+  bb.1.block (address-taken):
+    RETQ
 ...
diff --git a/test/CodeGen/MIR/X86/expected-integer-after-offset-sign.mir b/test/CodeGen/MIR/X86/expected-integer-after-offset-sign.mir
index 5e84c277286..e337292f17a 100644
--- a/test/CodeGen/MIR/X86/expected-integer-after-offset-sign.mir
+++ b/test/CodeGen/MIR/X86/expected-integer-after-offset-sign.mir
@@ -14,13 +14,11 @@
 ...
 ---
 name: inc
-body:
-  - id: 0
-    name: entry
-    instructions:
-      # CHECK: [[@LINE+1]]:42: expected an integer literal after '+'
-      - '%rax = MOV64rm %rip, 1, _, @G + , _'
-      - '%eax = MOV32rm %rax, 1, _, 0, _'
-      - '%eax = INC32r %eax, implicit-def %eflags'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    ; CHECK: [[@LINE+1]]:37: expected an integer literal after '+'
+    %rax = MOV64rm %rip, 1, _, @G + , _
+    %eax = MOV32rm %rax, 1, _, 0, _
+    %eax = INC32r %eax, implicit-def %eflags
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/expected-integer-in-successor-weight.mir b/test/CodeGen/MIR/X86/expected-integer-in-successor-weight.mir
new file mode 100644
index 00000000000..83874eb6747
--- /dev/null
+++ b/test/CodeGen/MIR/X86/expected-integer-in-successor-weight.mir
@@ -0,0 +1,38 @@
+# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s
+
+--- |
+
+  define i32 @foo(i32 %a) {
+  entry:
+    %0 = icmp sle i32 %a, 10
+    br i1 %0, label %less, label %exit
+
+  less:
+    ret i32 0
+
+  exit:
+    ret i32 %a
+  }
+
+...
+---
+name:            foo
+body: |
+  bb.0.entry:
+  ; CHECK: [[@LINE+1]]:29: expected an integer literal after '('
+    successors: %bb.1.less (_), %bb.2.exit(32)
+    liveins: %edi
+
+    CMP32ri8 %edi, 10, implicit-def %eflags
+    JG_1 %bb.2.exit, implicit killed %eflags
+
+  bb.1.less:
+    %eax = MOV32r0 implicit-def dead %eflags
+    RETQ killed %eax
+
+  bb.2.exit:
+    liveins: %edi
+
+    %eax = COPY killed %edi
+    RETQ killed %eax
+...
diff --git a/test/CodeGen/MIR/X86/expected-load-or-store-in-memory-operand.mir b/test/CodeGen/MIR/X86/expected-load-or-store-in-memory-operand.mir
index 28c2dd46497..8fcd622a18e 100644
--- a/test/CodeGen/MIR/X86/expected-load-or-store-in-memory-operand.mir
+++ b/test/CodeGen/MIR/X86/expected-load-or-store-in-memory-operand.mir
@@ -14,12 +14,10 @@ name:            test
 tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
-body:
-  - id:          0
-    name:        entry
-    liveins:     [ '%rdi' ]
-    instructions:
-# CHECK: [[@LINE+1]]:53: expected 'load' or 'store' memory operation
-      - '%eax = MOV32rm killed %rdi, 1, _, 0, _ :: (4 from %ir.a)'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    liveins: %rdi
+  ; CHECK: [[@LINE+1]]:48: expected 'load' or 'store' memory operation
+    %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (4 from %ir.a)
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/expected-machine-operand.mir b/test/CodeGen/MIR/X86/expected-machine-operand.mir
index 3725c93cd3e..3ba5126b998 100644
--- a/test/CodeGen/MIR/X86/expected-machine-operand.mir
+++ b/test/CodeGen/MIR/X86/expected-machine-operand.mir
@@ -10,12 +10,10 @@
 ...
 ---
 name:            foo
-body:
- - id:           0
-   name:         entry
-   instructions:
-     # CHECK: [[@LINE+1]]:24: expected a machine operand
-     - '%eax = XOR32rr ='
-     - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    ; CHECK: [[@LINE+1]]:20: expected a machine operand
+    %eax = XOR32rr =
+    RETQ %eax
 ...
 
diff --git a/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir b/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir
index 48d59933710..e1ee7a03f48 100644
--- a/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir
+++ b/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir
@@ -48,14 +48,12 @@ frameInfo:
   maxAlignment:  4
 stack:
   - { id: 0, name: x.addr, size: 4, alignment: 4 }
-body:
-  - id:          0
-    name:        entry
-    instructions:
-      - '%0 = COPY %edi'
-      # CHECK: [[@LINE+1]]:51: expected a metadata node after 'debug-location'
-      - 'DBG_VALUE _, 0, !12, !13, debug-location 14'
-      - 'MOV32mr %stack.x.addr, 1, _, 0, _, %0'
-      - '%eax = COPY %0'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    %0 = COPY %edi
+    ; CHECK: [[@LINE+1]]:46: expected a metadata node after 'debug-location'
+    DBG_VALUE _, 0, !12, !13, debug-location 14
+    MOV32mr %stack.x.addr, 1, _, 0, _, %0
+    %eax = COPY %0
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir b/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir
index 90e748e9f16..09db75afdc1 100644
--- a/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir
+++ b/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir
@@ -48,14 +48,12 @@ frameInfo:
   maxAlignment:  4
 stack:
   - { id: 0, name: x.addr, size: 4, alignment: 4 }
-body:
-  - id:          0
-    name:        entry
-    instructions:
-      - '%0 = COPY %edi'
-      # CHECK: [[@LINE+1]]:33: expected metadata id after '!'
-      - 'DBG_VALUE _, 0, !12, ! _'
-      - 'MOV32mr %stack.0.x.addr, 1, _, 0, _, %0'
-      - '%eax = COPY %0'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    %0 = COPY %edi
+    ; CHECK: [[@LINE+1]]:28: expected metadata id after '!'
+    DBG_VALUE _, 0, !12, ! _
+    MOV32mr %stack.0.x.addr, 1, _, 0, _, %0
+    %eax = COPY %0
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir b/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir
index 3dca9ab726b..04568f6dde5 100644
--- a/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir
+++ b/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir
@@ -17,14 +17,13 @@ registers:
   # CHECK: [[@LINE+1]]:48: expected a named register
   - { id: 1, class: gr32, preferred-register: '%0' }
   - { id: 2, class: gr32, preferred-register: '%edi' }
-body:
-  - id:              0
-    name:            body
-    liveins:         [ '%edi', '%esi' ]
-    instructions:
-      - '%1 = COPY %esi'
-      - '%2 = COPY %edi'
-      - '%2 = IMUL32rr %2, %1, implicit-def dead %eflags'
-      - '%eax = COPY %2'
-      - 'RETQ killed %eax'
+body: |
+  bb.0.body:
+    liveins: %edi, %esi
+
+    %1 = COPY %esi
+    %2 = COPY %edi
+    %2 = IMUL32rr %2, %1, implicit-def dead %eflags
+    %eax = COPY %2
+    RETQ killed %eax
 ...
diff --git a/test/CodeGen/MIR/X86/expected-named-register-in-callee-saved-register.mir b/test/CodeGen/MIR/X86/expected-named-register-in-callee-saved-register.mir
index bd9e70420b5..be57734ecf3 100644
--- a/test/CodeGen/MIR/X86/expected-named-register-in-callee-saved-register.mir
+++ b/test/CodeGen/MIR/X86/expected-named-register-in-callee-saved-register.mir
@@ -32,13 +32,12 @@
 ---
 name:            compute
 tracksRegLiveness: true
-body:
-  - id:          0
-    name:        body
-    liveins:     [ '%edi' ]
-    instructions:
-      - '%eax = COPY killed %edi'
-      - 'RETQ killed %eax'
+body: |
+  bb.0.body:
+    liveins: %edi
+
+    %eax = COPY killed %edi
+    RETQ killed %eax
 ...
 ---
 name:            func
@@ -53,39 +52,37 @@ fixedStack:
   - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: '%0' }
 stack:
   - { id: 0, name: b, offset: -20, size: 4, alignment: 4 }
-body:
-  - id:          0
-    name:        entry
-    successors:  [ '%bb.1.check' ]
-    liveins:     [ '%edi', '%rbx' ]
-    instructions:
-      - 'frame-setup PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp'
-      - '%rsp = frame-setup SUB64ri8 %rsp, 16, implicit-def dead %eflags'
-      - '%ebx = COPY %edi'
-      - 'MOV32mr %rsp, 1, _, 12, _, %ebx'
-  - id:          1
-    name:        check
-    successors:  [ '%bb.2.loop', '%bb.3.exit' ]
-    liveins:     [ '%ebx' ]
-    instructions:
-      - 'CMP32ri8 %ebx, 10, implicit-def %eflags'
-      - 'JG_1 %bb.3.exit, implicit killed %eflags'
-      - 'JMP_1 %bb.2.loop'
-  - id:          2
-    name:        loop
-    successors:  [ '%bb.1.check' ]
-    liveins:     [ '%ebx' ]
-    instructions:
-      - '%edi = MOV32rm %rsp, 1, _, 12, _'
-      - 'CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax'
-      - '%eax = DEC32r killed %eax, implicit-def dead %eflags'
-      - 'MOV32mr %rsp, 1, _, 12, _, killed %eax'
-      - 'JMP_1 %bb.1.check'
-  - id:          3
-    name:        exit
-    instructions:
-      - '%eax = MOV32r0 implicit-def dead %eflags'
-      - '%rsp = ADD64ri8 %rsp, 16, implicit-def dead %eflags'
-      - '%rbx = POP64r implicit-def %rsp, implicit %rsp'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    successors: %bb.1.check
+    liveins: %edi, %rbx
+
+    frame-setup PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp
+    %rsp = frame-setup SUB64ri8 %rsp, 16, implicit-def dead %eflags
+    %ebx = COPY %edi
+    MOV32mr %rsp, 1, _, 12, _, %ebx
+
+  bb.1.check:
+    successors: %bb.2.loop, %bb.3.exit
+    liveins: %ebx
+
+    CMP32ri8 %ebx, 10, implicit-def %eflags
+    JG_1 %bb.3.exit, implicit killed %eflags
+    JMP_1 %bb.2.loop
+
+  bb.2.loop:
+    successors: %bb.1.check
+    liveins: %ebx
+
+    %edi = MOV32rm %rsp, 1, _, 12, _
+    CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax
+    %eax = DEC32r killed %eax, implicit-def dead %eflags
+    MOV32mr %rsp, 1, _, 12, _, killed %eax
+    JMP_1 %bb.1.check
+
+  bb.3.exit:
+    %eax = MOV32r0 implicit-def dead %eflags
+    %rsp = ADD64ri8 %rsp, 16, implicit-def dead %eflags
+    %rbx = POP64r implicit-def %rsp, implicit %rsp
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir b/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir
index b14ff32694a..ae9f776ad76 100644
--- a/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir
+++ b/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir
@@ -17,12 +17,11 @@ registers:
 liveins:
   # CHECK: [[@LINE+1]]:13: expected a named register
   - { reg: '%0' }
-body:
-  - id:          0
-    name:        body
-    liveins:     [ '%edi' ]
-    instructions:
-      - '%0 = COPY %edi'
-      - '%eax = COPY %0'
-      - 'RETQ %eax'
+body: |
+  bb.0.body:
+    liveins: %edi
+
+    %0 = COPY %edi
+    %eax = COPY %0
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/expected-named-register-livein.mir b/test/CodeGen/MIR/X86/expected-named-register-livein.mir
index 1fbe881c8c7..41e6a4a6cc8 100644
--- a/test/CodeGen/MIR/X86/expected-named-register-livein.mir
+++ b/test/CodeGen/MIR/X86/expected-named-register-livein.mir
@@ -10,12 +10,11 @@
 ...
 ---
 name:            test
-body:
-  - id:          0
-    name:        body
-    # CHECK: [[@LINE+1]]:21: expected a named register
-    liveins:     [ '%0' ]
-    instructions:
-      - '%eax = COPY %edi'
-      - 'RETQ %eax'
+body: |
+  bb.0.body:
+    ; CHECK: [[@LINE+1]]:14: expected a named register
+    liveins: %0
+
+    %eax = COPY %edi
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/expected-newline-at-end-of-list.mir b/test/CodeGen/MIR/X86/expected-newline-at-end-of-list.mir
new file mode 100644
index 00000000000..1f0439d126f
--- /dev/null
+++ b/test/CodeGen/MIR/X86/expected-newline-at-end-of-list.mir
@@ -0,0 +1,41 @@
+# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s
+
+--- |
+
+  define i32 @foo(i32 %a) {
+  entry:
+    %0 = icmp sle i32 %a, 10
+    br i1 %0, label %less, label %exit
+
+  less:                                             ; preds = %entry
+    ret i32 0
+
+  exit:                                             ; preds = %entry
+    ret i32 %a
+  }
+
+...
+---
+name:            foo
+tracksRegLiveness: true
+liveins:
+  - { reg: '%edi' }
+body: |
+  bb.0.entry:
+    successors: %bb.1.less, %bb.2.exit
+  ; CHECK: [[@LINE+1]]:19: expected line break at the end of a list
+    liveins: %edi 44
+
+    CMP32ri8 %edi, 10, implicit-def %eflags
+    JG_1 %bb.2.exit, implicit killed %eflags
+
+  bb.1.less:
+    %eax = MOV32r0 implicit-def dead %eflags
+    RETQ killed %eax
+
+  bb.2.exit:
+    liveins: %edi
+
+    %eax = COPY killed %edi
+    RETQ killed %eax
+...
diff --git a/test/CodeGen/MIR/X86/expected-number-after-bb.mir b/test/CodeGen/MIR/X86/expected-number-after-bb.mir
index 5343a847fbb..a239cf176f5 100644
--- a/test/CodeGen/MIR/X86/expected-number-after-bb.mir
+++ b/test/CodeGen/MIR/X86/expected-number-after-bb.mir
@@ -18,20 +18,16 @@
 ...
 ---
 name:            foo
-body:
- - id: 0
-   name:   entry
-   instructions:
-     - '%eax = MOV32rm %rdi, 1, _, 0, _'
-     - 'CMP32ri8 %eax, 10, implicit-def %eflags'
-     # CHECK: [[@LINE+1]]:18: expected a number after '%bb.'
-     - 'JG_1 %bb.nah, implicit %eflags'
- - id: 1
-   name: yes
-   instructions:
-     - '%eax = MOV32r0 implicit-def %eflags'
- - id: 2
-   name: nah
-   instructions:
-     - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    %eax = MOV32rm %rdi, 1, _, 0, _
+    CMP32ri8 %eax, 10, implicit-def %eflags
+    ; CHECK: [[@LINE+1]]:14: expected a number after '%bb.'
+    JG_1 %bb.nah, implicit %eflags
+
+  bb.1.true:
+    %eax = MOV32r0 implicit-def %eflags
+
+  bb.2.nah:
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/expected-offset-after-cfi-operand.mir b/test/CodeGen/MIR/X86/expected-offset-after-cfi-operand.mir
index 42fb1400268..aefeed9ce05 100644
--- a/test/CodeGen/MIR/X86/expected-offset-after-cfi-operand.mir
+++ b/test/CodeGen/MIR/X86/expected-offset-after-cfi-operand.mir
@@ -16,14 +16,12 @@ frameInfo:
   stackSize:       4040
 stack:
   - { id: 0, name: tmp, offset: -4176, size: 4168, alignment: 4 }
-body:
-  - id:              0
-    name:            entry
-    instructions:
-      - '%rsp = SUB64ri32 %rsp, 4040, implicit-def dead %eflags'
-     # CHECK: [[@LINE+1]]:46: expected a cfi offset
-      - 'CFI_INSTRUCTION .cfi_def_cfa_offset _'
-      - '%rsp = ADD64ri32 %rsp, 4040, implicit-def dead %eflags'
-      - 'RETQ'
+body: |
+  bb.0.entry:
+    %rsp = SUB64ri32 %rsp, 4040, implicit-def dead %eflags
+    ; CHECK: [[@LINE+1]]:41: expected a cfi offset
+    CFI_INSTRUCTION .cfi_def_cfa_offset _
+    %rsp = ADD64ri32 %rsp, 4040, implicit-def dead %eflags
+    RETQ
 ...
 
diff --git a/test/CodeGen/MIR/X86/expected-pointer-value-in-memory-operand.mir b/test/CodeGen/MIR/X86/expected-pointer-value-in-memory-operand.mir
index e5bfa73c13c..fca078c3497 100644
--- a/test/CodeGen/MIR/X86/expected-pointer-value-in-memory-operand.mir
+++ b/test/CodeGen/MIR/X86/expected-pointer-value-in-memory-operand.mir
@@ -14,13 +14,11 @@ name:            test
 tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
-body:
-  - id:          0
-    name:        entry
-    liveins:     [ '%rdi' ]
-    instructions:
-# CHECK: [[@LINE+1]]:65: expected a pointer IR value
-      - '%eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 from %ir.b)'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    liveins: %rdi
+  ; CHECK: [[@LINE+1]]:60: expected a pointer IR value
+    %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 from %ir.b)
+    RETQ %eax
 ...
 
diff --git a/test/CodeGen/MIR/X86/expected-positive-alignment-after-align.mir b/test/CodeGen/MIR/X86/expected-positive-alignment-after-align.mir
index 442d2fa7538..31b4c5be125 100644
--- a/test/CodeGen/MIR/X86/expected-positive-alignment-after-align.mir
+++ b/test/CodeGen/MIR/X86/expected-positive-alignment-after-align.mir
@@ -16,17 +16,15 @@ name:            memory_alignment
 tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
-body:
-  - id:          0
-    name:        entry
-    liveins:     [ '%rdi' ]
-    instructions:
-# CHECK: [[@LINE+1]]:76: expected an integer literal after 'align'
-      - '%xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, align -32)'
-      - '%xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32)'
-      - '%xmm2 = FsFLD0SS'
-      - '%xmm1 = MOVSSrr killed %xmm1, killed %xmm2'
-      - 'MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec, align 32)'
-      - 'MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32)'
-      - RETQ
+body: |
+  bb.0.entry:
+    liveins: %rdi
+  ; CHECK: [[@LINE+1]]:71: expected an integer literal after 'align'
+    %xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, align -32)
+    %xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32)
+    %xmm2 = FsFLD0SS
+    %xmm1 = MOVSSrr killed %xmm1, killed %xmm2
+    MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec, align 32)
+    MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32)
+    RETQ
 ...
diff --git a/test/CodeGen/MIR/X86/expected-register-after-cfi-operand.mir b/test/CodeGen/MIR/X86/expected-register-after-cfi-operand.mir
index 7178c1d4568..3280fca6d55 100644
--- a/test/CodeGen/MIR/X86/expected-register-after-cfi-operand.mir
+++ b/test/CodeGen/MIR/X86/expected-register-after-cfi-operand.mir
@@ -24,21 +24,19 @@ frameInfo:
   hasCalls:        true
 fixedStack:
   - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16 }
-body:
-  - id:              0
-    name:            entry
-    instructions:
-      - 'PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp'
-      - 'CFI_INSTRUCTION .cfi_def_cfa_offset 16'
-      # CHECK: [[@LINE+1]]:38: expected a cfi register
-      - 'CFI_INSTRUCTION .cfi_offset %0, -16'
-      - '%ebx = COPY %edi, implicit-def %rbx'
-      - '%ebx = ADD32rr %ebx, killed %esi, implicit-def dead %eflags'
-      - '%ebx = ADD32rr %ebx, killed %edx, implicit-def dead %eflags'
-      - '%ebx = ADD32rr %ebx, killed %ecx, implicit-def dead %eflags'
-      - '%edi = COPY %ebx'
-      - 'CALL64pcrel32 @foo, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp'
-      - '%eax = LEA64_32r killed %rbx, 1, %rbx, 0, _'
-      - '%rbx = POP64r implicit-def %rsp, implicit %rsp'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp
+    CFI_INSTRUCTION .cfi_def_cfa_offset 16
+    ; CHECK: [[@LINE+1]]:33: expected a cfi register
+    CFI_INSTRUCTION .cfi_offset %0, -16
+    %ebx = COPY %edi, implicit-def %rbx
+    %ebx = ADD32rr %ebx, killed %esi, implicit-def dead %eflags
+    %ebx = ADD32rr %ebx, killed %edx, implicit-def dead %eflags
+    %ebx = ADD32rr %ebx, killed %ecx, implicit-def dead %eflags
+    %edi = COPY %ebx
+    CALL64pcrel32 @foo, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp
+    %eax = LEA64_32r killed %rbx, 1, %rbx, 0, _
+    %rbx = POP64r implicit-def %rsp, implicit %rsp
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/expected-register-after-flags.mir b/test/CodeGen/MIR/X86/expected-register-after-flags.mir
index 111f5496a37..68f1060ad87 100644
--- a/test/CodeGen/MIR/X86/expected-register-after-flags.mir
+++ b/test/CodeGen/MIR/X86/expected-register-after-flags.mir
@@ -12,11 +12,9 @@
 ...
 ---
 name:            foo
-body:
- - id:           0
-   name:         entry
-   instructions:
-     # CHECK: [[@LINE+1]]:37: expected a register after register flags
-     - '%eax = MOV32r0 implicit-def 2'
-     - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    ; CHECK: [[@LINE+1]]:33: expected a register after register flags
+    %eax = MOV32r0 implicit-def 2
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation.mir b/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation.mir
index 526558c93a3..71ff15bd9c5 100644
--- a/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation.mir
+++ b/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation.mir
@@ -14,13 +14,11 @@ name:            test
 tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
-body:
-  - id:          0
-    name:        entry
-    liveins:     [ '%rdi' ]
-    instructions:
-# CHECK: [[@LINE+1]]:58: expected the size integer literal after memory operation
-      - '%eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load from %ir.a)'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    liveins: %rdi
+  ; CHECK: [[@LINE+1]]:53: expected the size integer literal after memory operation
+    %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load from %ir.a)
+    RETQ %eax
 ...
 
diff --git a/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir b/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir
index c891a115a18..6283427c10b 100644
--- a/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir
+++ b/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir
@@ -16,14 +16,12 @@ registers:
   - { id: 0, class: gr32 }
   - { id: 1, class: gr8 }
   - { id: 2, class: gr8 }
-body:
-  - name:        entry
-    id:          0
-    instructions:
-      - '%0 = COPY %edi'
-      # CHECK: [[@LINE+1]]:25: expected a subregister index after ':'
-      - '%1 = COPY %0 : 42'
-      - '%2 = AND8ri %1, 1, implicit-def %eflags'
-      - '%al = COPY %2'
-      - 'RETQ %al'
+body: |
+  bb.0.entry:
+    %0 = COPY %edi
+    ; CHECK: [[@LINE+1]]:20: expected a subregister index after ':'
+    %1 = COPY %0 : 42
+    %2 = AND8ri %1, 1, implicit-def %eflags
+    %al = COPY %2
+    RETQ %al
 ...
diff --git a/test/CodeGen/MIR/X86/expected-target-flag-name.mir b/test/CodeGen/MIR/X86/expected-target-flag-name.mir
index a885a566b67..3d094a11e9f 100644
--- a/test/CodeGen/MIR/X86/expected-target-flag-name.mir
+++ b/test/CodeGen/MIR/X86/expected-target-flag-name.mir
@@ -14,13 +14,11 @@
 ...
 ---
 name: inc
-body:
-  - id: 0
-    name: entry
-    instructions:
-# CHECK: [[@LINE+1]]:51: expected the name of the target flag
-      - '%rax = MOV64rm %rip, 1, _, target-flags( ) @G, _'
-      - '%eax = MOV32rm killed %rax, 1, _, 0, _'
-      - '%eax = INC32r killed %eax, implicit-def dead %eflags'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+  ; CHECK: [[@LINE+1]]:46: expected the name of the target flag
+    %rax = MOV64rm %rip, 1, _, target-flags( ) @G, _
+    %eax = MOV32rm killed %rax, 1, _, 0, _
+    %eax = INC32r killed %eax, implicit-def dead %eflags
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/expected-value-in-memory-operand.mir b/test/CodeGen/MIR/X86/expected-value-in-memory-operand.mir
index 2493e948c1a..f99443f1726 100644
--- a/test/CodeGen/MIR/X86/expected-value-in-memory-operand.mir
+++ b/test/CodeGen/MIR/X86/expected-value-in-memory-operand.mir
@@ -14,13 +14,11 @@ name:            test
 tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
-body:
-  - id:          0
-    name:        entry
-    liveins:     [ '%rdi' ]
-    instructions:
-# CHECK: [[@LINE+1]]:65: expected an IR value reference
-      - '%eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 from a)'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    liveins: %rdi
+  ; CHECK: [[@LINE+1]]:60: expected an IR value reference
+    %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 from a)
+    RETQ %eax
 ...
 
diff --git a/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir b/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir
index edadf42056b..da0d1e166a1 100644
--- a/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir
+++ b/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir
@@ -17,12 +17,11 @@ registers:
 liveins:
   # CHECK: [[@LINE+1]]:34: expected a virtual register
   - { reg: '%edi', virtual-reg: '%edi' }
-body:
-  - id:          0
-    name:        body
-    liveins:     [ '%edi' ]
-    instructions:
-      - '%0 = COPY %edi'
-      - '%eax = COPY %0'
-      - 'RETQ %eax'
+body: |
+  bb.0.body:
+    liveins: %edi
+
+    %0 = COPY %edi
+    %eax = COPY %0
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/external-symbol-operands.mir b/test/CodeGen/MIR/X86/external-symbol-operands.mir
index eeb93c8f21f..7e85d946b75 100644
--- a/test/CodeGen/MIR/X86/external-symbol-operands.mir
+++ b/test/CodeGen/MIR/X86/external-symbol-operands.mir
@@ -29,38 +29,36 @@
 ---
 name:            test
 tracksRegLiveness: true
-body:
-  - id:              0
-    name:            entry
-    successors:      [ '%bb.1.entry', '%bb.2.entry' ]
-    liveins:         [ '%edi' ]
-    instructions:
-      - '%rsp = SUB64ri32 %rsp, 520, implicit-def %eflags'
-      - '%rcx = LOAD_STACK_GUARD'
-      - 'MOV64mr %rsp, 1, _, 512, _, %rcx'
-      - '%rax = MOVSX64rr32 %edi'
-      - '%eax = MOV32rm %rsp, 4, %rax, 0, _'
-      - 'CMP64rm %rcx, %rsp, 1, _, 512, _, implicit-def %eflags'
-      - 'JNE_1 %bb.2.entry, implicit %eflags'
-  - id:              1
-    name:            entry
-    liveins:         [ '%eax' ]
-    instructions:
-      - '%rsp = ADD64ri32 %rsp, 520, implicit-def %eflags'
-      - 'RETQ %eax'
-  - id:              2
-    name:            entry
-    instructions:
-      # CHECK:      CALL64pcrel32 $__stack_chk_fail,
-      # CHECK-NEXT: CALL64pcrel32 $__stack_chk_fail.09-_,
-      # CHECK-NEXT: CALL64pcrel32 $"__stack_chk_fail$",
-      # CHECK-NEXT: CALL64pcrel32 $"$Quoted \09 External symbol \11 ",
-      # CHECK-NEXT: CALL64pcrel32 $__stack_chk_fail + 2,
-      # CHECK-NEXT: CALL64pcrel32 $" check stack - 20" - 20,
-      - 'CALL64pcrel32 $__stack_chk_fail, csr_64, implicit %rsp, implicit-def %rsp'
-      - 'CALL64pcrel32 $__stack_chk_fail.09-_, csr_64, implicit %rsp, implicit-def %rsp'
-      - 'CALL64pcrel32 $__stack_chk_fail$, csr_64, implicit %rsp, implicit-def %rsp'
-      - 'CALL64pcrel32 $"$Quoted \09 External symbol \11 ", csr_64, implicit %rsp, implicit-def %rsp'
-      - 'CALL64pcrel32 $__stack_chk_fail + 2, csr_64, implicit %rsp, implicit-def %rsp'
-      - 'CALL64pcrel32 $" check stack - 20" - 20, csr_64, implicit %rsp, implicit-def %rsp'
+body: |
+  bb.0.entry:
+    successors: %bb.1.entry, %bb.2.entry
+    liveins: %edi
+
+    %rsp = SUB64ri32 %rsp, 520, implicit-def %eflags
+    %rcx = LOAD_STACK_GUARD
+    MOV64mr %rsp, 1, _, 512, _, %rcx
+    %rax = MOVSX64rr32 %edi
+    %eax = MOV32rm %rsp, 4, %rax, 0, _
+    CMP64rm %rcx, %rsp, 1, _, 512, _, implicit-def %eflags
+    JNE_1 %bb.2.entry, implicit %eflags
+
+  bb.1.entry:
+    liveins: %eax
+
+    %rsp = ADD64ri32 %rsp, 520, implicit-def %eflags
+    RETQ %eax
+
+  bb.2.entry:
+    ; CHECK:      CALL64pcrel32 $__stack_chk_fail,
+    ; CHECK-NEXT: CALL64pcrel32 $__stack_chk_fail.09-_,
+    ; CHECK-NEXT: CALL64pcrel32 $"__stack_chk_fail$",
+    ; CHECK-NEXT: CALL64pcrel32 $"$Quoted \09 External symbol \11 ",
+    ; CHECK-NEXT: CALL64pcrel32 $__stack_chk_fail + 2,
+    ; CHECK-NEXT: CALL64pcrel32 $" check stack - 20" - 20,
+    CALL64pcrel32 $__stack_chk_fail, csr_64, implicit %rsp, implicit-def %rsp
+    CALL64pcrel32 $__stack_chk_fail.09-_, csr_64, implicit %rsp, implicit-def %rsp
+    CALL64pcrel32 $__stack_chk_fail$, csr_64, implicit %rsp, implicit-def %rsp
+    CALL64pcrel32 $"$Quoted \09 External symbol \11 ", csr_64, implicit %rsp, implicit-def %rsp
+    CALL64pcrel32 $__stack_chk_fail + 2, csr_64, implicit %rsp, implicit-def %rsp
+    CALL64pcrel32 $" check stack - 20" - 20, csr_64, implicit %rsp, implicit-def %rsp
 ...
diff --git a/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir b/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir
index 8c9bce4044b..75d0f8a39c1 100644
--- a/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir
+++ b/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir
@@ -26,16 +26,14 @@ fixedStack:
   - { id: 0, offset: 0, size: 4, alignment: 16, isImmutable: true }
 stack:
   - { id: 0, name: b, offset: -8, size: 4, alignment: 4 }
-body:
-  - id:              0
-    name:            entry
-    instructions:
-      - 'frame-setup PUSH32r undef %eax, implicit-def %esp, implicit %esp'
-      - CFI_INSTRUCTION .cfi_def_cfa_offset 8
-# CHECK: name: test
-# CHECK: %eax = MOV32rm %esp, 1, _, 8, _ :: (load 4 from %fixed-stack.0, align 16)
-      - '%eax = MOV32rm %esp, 1, _, 8, _ :: (load 4 from %fixed-stack.0, align 16)'
-      - 'MOV32mr %esp, 1, _, 0, _, %eax :: (store 4 into %ir.b)'
-      - '%edx = POP32r implicit-def %esp, implicit %esp'
-      - 'RETL %eax'
+body: |
+  bb.0.entry:
+    frame-setup PUSH32r undef %eax, implicit-def %esp, implicit %esp
+    CFI_INSTRUCTION .cfi_def_cfa_offset 8
+  ; CHECK: name: test
+  ; CHECK: %eax = MOV32rm %esp, 1, _, 8, _ :: (load 4 from %fixed-stack.0, align 16)
+    %eax = MOV32rm %esp, 1, _, 8, _ :: (load 4 from %fixed-stack.0, align 16)
+    MOV32mr %esp, 1, _, 0, _, %eax :: (store 4 into %ir.b)
+    %edx = POP32r implicit-def %esp, implicit %esp
+    RETL %eax
 ...
diff --git a/test/CodeGen/MIR/X86/fixed-stack-object-redefinition-error.mir b/test/CodeGen/MIR/X86/fixed-stack-object-redefinition-error.mir
index 5f88bc428f1..c4c57a1d244 100644
--- a/test/CodeGen/MIR/X86/fixed-stack-object-redefinition-error.mir
+++ b/test/CodeGen/MIR/X86/fixed-stack-object-redefinition-error.mir
@@ -20,11 +20,9 @@ fixedStack:
   - { id: 0, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false }
 # CHECK: [[@LINE+1]]:11: redefinition of fixed stack object '%fixed-stack.0'
   - { id: 0, offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false }
-body:
-  - id:              0
-    name:            entry
-    instructions:
-      - '%eax = MOV32rm %esp, 1, _, 4, _'
-      - '%eax = ADD32rm killed %eax, %esp, 1, _, 8, _, implicit-def dead %eflags'
-      - 'RETL %eax'
+body: |
+  bb.0.entry:
+    %eax = MOV32rm %esp, 1, _, 4, _
+    %eax = ADD32rm killed %eax, %esp, 1, _, 8, _, implicit-def dead %eflags
+    RETL %eax
 ...
diff --git a/test/CodeGen/MIR/X86/fixed-stack-objects.mir b/test/CodeGen/MIR/X86/fixed-stack-objects.mir
index dcbe6f73a6d..70e5a742835 100644
--- a/test/CodeGen/MIR/X86/fixed-stack-objects.mir
+++ b/test/CodeGen/MIR/X86/fixed-stack-objects.mir
@@ -25,11 +25,9 @@ fixedStack:
   - { id: 0, offset: 0, size: 4, alignment: 4, isImmutable: true, isAliased: false }
 stack:
   - { id: 0, offset: -8, size: 4, alignment: 4 }
-body:
-  - id:          0
-    name:        entry
-    instructions:
-      - '%eax = MOV32rm %esp, 1, _, 8, _'
-      - 'MOV32mr %esp, 1, _, 0, _, %eax'
-      - 'RETL %eax'
+body: |
+  bb.0.entry:
+    %eax = MOV32rm %esp, 1, _, 8, _
+    MOV32mr %esp, 1, _, 0, _, %eax
+    RETL %eax
 ...
diff --git a/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir b/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir
index 9bf8d0d77a9..54fa8ad0b61 100644
--- a/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir
+++ b/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir
@@ -40,33 +40,34 @@ frameInfo:
   restorePoint:  '%bb.2.true'
 stack:
   - { id: 0, name: tmp, offset: 0, size: 4, alignment: 4 }
-body:
-  - id:          0
-    successors:  [ '%bb.2.true', '%bb.1' ]
-    liveins:     [ '%edi', '%esi' ]
-    instructions:
-      - '%eax = COPY %edi'
-      - 'CMP32rr %eax, killed %esi, implicit-def %eflags'
-      - 'JL_1 %bb.2.true, implicit killed %eflags'
-  - id:          1
-    successors:  [ '%bb.3.false' ]
-    liveins:     [ '%eax' ]
-    instructions:
-      - 'JMP_1 %bb.3.false'
-  - id:          2
-    name:        'true'
-    successors:  [ '%bb.3.false' ]
-    liveins:     [ '%eax' ]
-    instructions:
-      - 'MOV32mr %stack.0.tmp, 1, _, 0, _, killed %eax'
-      - 'ADJCALLSTACKDOWN64 0, 0, implicit-def %rsp, implicit-def dead %eflags, implicit %rsp'
-      - '%rsi = LEA64r %stack.0.tmp, 1, _, 0, _'
-      - '%edi = MOV32r0 implicit-def dead %eflags'
-      - 'CALL64pcrel32 @doSomething, csr_64, implicit %rsp, implicit %edi, implicit %rsi, implicit-def %rsp, implicit-def %eax'
-      - 'ADJCALLSTACKUP64 0, 0, implicit-def %rsp, implicit-def dead %eflags, implicit %rsp'
-  - id:          3
-    name:        'false'
-    liveins:     [ '%eax' ]
-    instructions:
-      - 'RETQ %eax'
+body: |
+  bb.0:
+    successors: %bb.2.true, %bb.1
+    liveins: %edi, %esi
+
+    %eax = COPY %edi
+    CMP32rr %eax, killed %esi, implicit-def %eflags
+    JL_1 %bb.2.true, implicit killed %eflags
+
+  bb.1:
+    successors: %bb.3.false
+    liveins: %eax
+
+    JMP_1 %bb.3.false
+
+  bb.2.true:
+    successors: %bb.3.false
+    liveins: %eax
+
+    MOV32mr %stack.0.tmp, 1, _, 0, _, killed %eax
+    ADJCALLSTACKDOWN64 0, 0, implicit-def %rsp, implicit-def dead %eflags, implicit %rsp
+    %rsi = LEA64r %stack.0.tmp, 1, _, 0, _
+    %edi = MOV32r0 implicit-def dead %eflags
+    CALL64pcrel32 @doSomething, csr_64, implicit %rsp, implicit %edi, implicit %rsi, implicit-def %rsp, implicit-def %eax
+    ADJCALLSTACKUP64 0, 0, implicit-def %rsp, implicit-def dead %eflags, implicit %rsp
+
+  bb.3.false:
+    liveins: %eax
+
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/frame-setup-instruction-flag.mir b/test/CodeGen/MIR/X86/frame-setup-instruction-flag.mir
index ca34fe1050d..87c1fc68046 100644
--- a/test/CodeGen/MIR/X86/frame-setup-instruction-flag.mir
+++ b/test/CodeGen/MIR/X86/frame-setup-instruction-flag.mir
@@ -18,22 +18,18 @@
 ...
 ---
 name:            compute
-body:
-  - name:        body
-    id:          0
-    instructions:
-      - '%eax = IMUL32rri8 %edi, 11, implicit-def %eflags'
-      - 'RETQ %eax'
+body: |
+  bb.0.body:
+    %eax = IMUL32rri8 %edi, 11, implicit-def %eflags
+    RETQ %eax
 ...
 ---
 name:            foo
-body:
-  - name:        entry
-    id:          0
-    instructions:
-      # CHECK: frame-setup PUSH64r %rax
-      - 'frame-setup PUSH64r %rax, implicit-def %rsp, implicit %rsp'
-      - 'CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax'
-      - '%rdx = POP64r implicit-def %rsp, implicit %rsp'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    ; CHECK: frame-setup PUSH64r %rax
+    frame-setup PUSH64r %rax, implicit-def %rsp, implicit %rsp
+    CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax
+    %rdx = POP64r implicit-def %rsp, implicit %rsp
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/function-liveins.mir b/test/CodeGen/MIR/X86/function-liveins.mir
index d3c9d3f72cd..95f8786b47a 100644
--- a/test/CodeGen/MIR/X86/function-liveins.mir
+++ b/test/CodeGen/MIR/X86/function-liveins.mir
@@ -25,14 +25,13 @@ registers:
 liveins:
   - { reg: '%edi', virtual-reg: '%0' }
   - { reg: '%esi', virtual-reg: '%1' }
-body:
-  - id:              0
-    name:            body
-    liveins:         [ '%edi', '%esi' ]
-    instructions:
-      - '%1 = COPY %esi'
-      - '%0 = COPY %edi'
-      - '%2 = ADD32rr %0, %1, implicit-def dead %eflags'
-      - '%eax = COPY %2'
-      - 'RETQ %eax'
+body: |
+  bb.0.body:
+    liveins: %edi, %esi
+
+    %1 = COPY %esi
+    %0 = COPY %edi
+    %2 = ADD32rr %0, %1, implicit-def dead %eflags
+    %eax = COPY %2
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/global-value-operands.mir b/test/CodeGen/MIR/X86/global-value-operands.mir
index f29ed358a71..394aa397aef 100644
--- a/test/CodeGen/MIR/X86/global-value-operands.mir
+++ b/test/CodeGen/MIR/X86/global-value-operands.mir
@@ -62,91 +62,79 @@
 ---
 # CHECK: name: inc
 name: inc
-body:
-  - id: 0
-    name: entry
-    instructions:
-      # CHECK: - '%rax = MOV64rm %rip, 1, _, @G, _'
-      - '%rax = MOV64rm %rip, 1, _, @G, _'
-      - '%eax = MOV32rm %rax, 1, _, 0, _'
-      - '%eax = INC32r %eax, implicit-def %eflags'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    ; CHECK: %rax = MOV64rm %rip, 1, _, @G, _
+    %rax = MOV64rm %rip, 1, _, @G, _
+    %eax = MOV32rm %rax, 1, _, 0, _
+    %eax = INC32r %eax, implicit-def %eflags
+    RETQ %eax
 ...
 ---
 # CHECK: name: inc2
 name: inc2
-body:
-  - id: 0
-    name: entry
-    instructions:
-      # CHECK: - '%rax = MOV64rm %rip, 1, _, @0, _'
-      - '%rax = MOV64rm %rip, 1, _, @0, _'
-      - '%eax = MOV32rm %rax, 1, _, 0, _'
-      - '%eax = INC32r %eax, implicit-def %eflags'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    ; CHECK: %rax = MOV64rm %rip, 1, _, @0, _
+    %rax = MOV64rm %rip, 1, _, @0, _
+    %eax = MOV32rm %rax, 1, _, 0, _
+    %eax = INC32r %eax, implicit-def %eflags
+    RETQ %eax
 ...
 ---
 name:            test
-body:
-  - id:              0
-    name:            entry
-    instructions:
-      # CHECK: , @".$0",
-      # CHECK: , @-_-,
-      # CHECK: , @_-_a,
-      # CHECK: , @"$.-B",
-      - '%rax = MOV64rm %rip, 1, _, @.$0, _'
-      - '%eax = MOV32rm killed %rax, 1, _, 0, _'
-      - '%rcx = MOV64rm %rip, 1, _, @-_-, _'
-      - 'MOV32mr killed %rcx, 1, _, 0, _, killed %eax'
-      - '%rax = MOV64rm %rip, 1, _, @_-_a, _'
-      - '%eax = MOV32rm killed %rax, 1, _, 0, _'
-      - '%rcx = MOV64rm %rip, 1, _, @$.-B, _'
-      - 'MOV32mr killed %rcx, 1, _, 0, _, %eax'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    ; CHECK: , @".$0",
+    ; CHECK: , @-_-,
+    ; CHECK: , @_-_a,
+    ; CHECK: , @"$.-B",
+    %rax = MOV64rm %rip, 1, _, @.$0, _
+    %eax = MOV32rm killed %rax, 1, _, 0, _
+    %rcx = MOV64rm %rip, 1, _, @-_-, _
+    MOV32mr killed %rcx, 1, _, 0, _, killed %eax
+    %rax = MOV64rm %rip, 1, _, @_-_a, _
+    %eax = MOV32rm killed %rax, 1, _, 0, _
+    %rcx = MOV64rm %rip, 1, _, @$.-B, _
+    MOV32mr killed %rcx, 1, _, 0, _, %eax
+    RETQ %eax
 ...
 ---
 name:            test2
-body:
-  - id:              0
-    name:            entry
-    instructions:
-      # CHECK: , @"\01Hello@$%09 \5C World,",
-      - '%rax = MOV64rm %rip, 1, _, @"\01Hello@$%09 \\ World,", _'
-      - '%eax = MOV32rm killed %rax, 1, _, 0, _'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    ; CHECK: , @"\01Hello@$%09 \5C World,",
+    %rax = MOV64rm %rip, 1, _, @"\01Hello@$%09 \\ World,", _
+    %eax = MOV32rm killed %rax, 1, _, 0, _
+    RETQ %eax
 ...
 ---
 # CHECK: name: test3
 name:            test3
-body:
-  - id:              0
-    name:            entry
-    instructions:
-      # CHECK: , @".$0",
-      # CHECK: , @-_-,
-      # CHECK: , @_-_a + 4,
-      # CHECK: , @"$.-B" - 8,
-      - '%rax = MOV64rm %rip, 1, _, @.$0 + 0, _'
-      - '%eax = MOV32rm killed %rax, 1, _, 0, _'
-      - '%rcx = MOV64rm %rip, 1, _, @-_- - 0, _'
-      - 'MOV32mr killed %rcx, 1, _, 0, _, killed %eax'
-      - '%rax = MOV64rm %rip, 1, _, @_-_a + 4, _'
-      - '%eax = MOV32rm killed %rax, 1, _, 0, _'
-      - '%rcx = MOV64rm %rip, 1, _, @$.-B - 8, _'
-      - 'MOV32mr killed %rcx, 1, _, 0, _, %eax'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    ; CHECK: , @".$0",
+    ; CHECK: , @-_-,
+    ; CHECK: , @_-_a + 4,
+    ; CHECK: , @"$.-B" - 8,
+    %rax = MOV64rm %rip, 1, _, @.$0 + 0, _
+    %eax = MOV32rm killed %rax, 1, _, 0, _
+    %rcx = MOV64rm %rip, 1, _, @-_- - 0, _
+    MOV32mr killed %rcx, 1, _, 0, _, killed %eax
+    %rax = MOV64rm %rip, 1, _, @_-_a + 4, _
+    %eax = MOV32rm killed %rax, 1, _, 0, _
+    %rcx = MOV64rm %rip, 1, _, @$.-B - 8, _
+    MOV32mr killed %rcx, 1, _, 0, _, %eax
+    RETQ %eax
 ...
 ---
 # CHECK: name: tf
 name: tf
-body:
-  - id: 0
-    name: entry
-    instructions:
-# CHECK: %rax = MOV64rm %rip, 1, _, target-flags(x86-gotpcrel) @G, _
-      - '%rax = MOV64rm %rip, 1, _, target-flags(x86-gotpcrel) @G, _'
-      - '%eax = MOV32rm %rax, 1, _, 0, _'
-      - '%eax = INC32r %eax, implicit-def %eflags'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+  ; CHECK: %rax = MOV64rm %rip, 1, _, target-flags(x86-gotpcrel) @G, _
+    %rax = MOV64rm %rip, 1, _, target-flags(x86-gotpcrel) @G, _
+    %eax = MOV32rm %rax, 1, _, 0, _
+    %eax = INC32r %eax, implicit-def %eflags
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/immediate-operands.mir b/test/CodeGen/MIR/X86/immediate-operands.mir
index 5d4956f539d..34bd0fa1490 100644
--- a/test/CodeGen/MIR/X86/immediate-operands.mir
+++ b/test/CodeGen/MIR/X86/immediate-operands.mir
@@ -17,24 +17,20 @@
 ---
 # CHECK: name: foo
 name:            foo
-body:
- - id:           0
-   name:         entry
-   instructions:
-     # CHECK:      - '%eax = MOV32ri 42'
-     # CHECK-NEXT: - 'RETQ %eax'
-     - '%eax = MOV32ri 42'
-     - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    ; CHECK:      %eax = MOV32ri 42
+    ; CHECK-NEXT: RETQ %eax
+    %eax = MOV32ri 42
+    RETQ %eax
 ...
 ---
 # CHECK: name: bar
 name:            bar
-body:
- - id:           0
-   name:         entry
-   instructions:
-     # CHECK:      - '%eax = MOV32ri -11'
-     # CHECK-NEXT: - 'RETQ %eax'
-     - '%eax = MOV32ri -11'
-     - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    ; CHECK:      %eax = MOV32ri -11
+    ; CHECK-NEXT: RETQ %eax
+    %eax = MOV32ri -11
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/implicit-register-flag.mir b/test/CodeGen/MIR/X86/implicit-register-flag.mir
index cf2c930b64b..a18a578e249 100644
--- a/test/CodeGen/MIR/X86/implicit-register-flag.mir
+++ b/test/CodeGen/MIR/X86/implicit-register-flag.mir
@@ -19,24 +19,20 @@
 ...
 ---
 name:            foo
-body:
-  - id:          0
-    name:        entry
-    successors:  [ '%bb.1.less', '%bb.2.exit' ]
-    instructions:
-      # CHECK:      - 'CMP32ri8 %edi, 10, implicit-def %eflags'
-      # CHECK-NEXT: - 'JG_1 %bb.2.exit, implicit %eflags'
-      - 'CMP32ri8 %edi, 10, implicit-def %eflags'
-      - 'JG_1 %bb.2.exit, implicit %eflags'
-  - id:          1
-    name:        less
-    instructions:
-      # CHECK: - '%eax = MOV32r0 implicit-def %eflags'
-      - '%eax = MOV32r0 implicit-def %eflags'
-      - 'RETQ %eax'
-  - id:          2
-    name:        exit
-    instructions:
-      - '%eax = COPY %edi'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    successors: %bb.1.less, %bb.2.exit
+    ; CHECK:      CMP32ri8 %edi, 10, implicit-def %eflags
+    ; CHECK-NEXT: JG_1 %bb.2.exit, implicit %eflags
+    CMP32ri8 %edi, 10, implicit-def %eflags
+    JG_1 %bb.2.exit, implicit %eflags
+
+  bb.1.less:
+    ; CHECK: %eax = MOV32r0 implicit-def %eflags
+    %eax = MOV32r0 implicit-def %eflags
+    RETQ %eax
+
+  bb.2.exit:
+    %eax = COPY %edi
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/instructions-debug-location.mir b/test/CodeGen/MIR/X86/instructions-debug-location.mir
index 57554841086..9436ad32139 100644
--- a/test/CodeGen/MIR/X86/instructions-debug-location.mir
+++ b/test/CodeGen/MIR/X86/instructions-debug-location.mir
@@ -59,19 +59,17 @@ frameInfo:
   maxAlignment:  4
 stack:
   - { id: 0, name: x.addr, size: 4, alignment: 4 }
-body:
-  - id:           0
-    name:         entry
-    liveins:      [ '%edi' ]
-    instructions:
-      # CHECK: DBG_VALUE debug-use _, 0, !12, !13, debug-location !14
-      # CHECK: %eax = COPY %0, debug-location !15
-      # CHECK: RETQ %eax, debug-location !15
-      - '%0 = COPY %edi'
-      - 'DBG_VALUE debug-use _, 0, !12, !13, debug-location !14'
-      - 'MOV32mr %stack.0.x.addr, 1, _, 0, _, %0'
-      - '%eax = COPY %0, debug-location !15'
-      - 'RETQ %eax, debug-location !15'
+body: |
+  bb.0.entry:
+    liveins: %edi
+    ; CHECK: DBG_VALUE debug-use _, 0, !12, !13, debug-location !14
+    ; CHECK: %eax = COPY %0, debug-location !15
+    ; CHECK: RETQ %eax, debug-location !15
+    %0 = COPY %edi
+    DBG_VALUE debug-use _, 0, !12, !13, debug-location !14
+    MOV32mr %stack.0.x.addr, 1, _, 0, _, %0
+    %eax = COPY %0, debug-location !15
+    RETQ %eax, debug-location !15
 ...
 ---
 name:            test_typed_immediates
@@ -83,19 +81,18 @@ frameInfo:
   maxAlignment:  4
 stack:
   - { id: 0, name: x.addr, size: 4, alignment: 4 }
-body:
-  - id:           0
-    name:         entry
-    liveins:      [ '%edi' ]
-    instructions:
-      - '%0 = COPY %edi'
-# CHECK:      DBG_VALUE _, i32 0, !12, !13
-# CHECK-NEXT: DBG_VALUE _, i64 -22, !12, !13
-# CHECK-NEXT: DBG_VALUE _, i128 123492148938512984928424384934328985928, !12, !13
-      - 'DBG_VALUE _, i32 0, !12, !13'
-      - 'DBG_VALUE _, i64 -22, !12, !13'
-      - 'DBG_VALUE _, i128 123492148938512984928424384934328985928, !12, !13'
-      - 'MOV32mr %stack.0.x.addr, 1, _, 0, _, %0'
-      - '%eax = COPY %0'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    liveins: %edi
+
+    %0 = COPY %edi
+  ; CHECK:      DBG_VALUE _, i32 0, !12, !13
+  ; CHECK-NEXT: DBG_VALUE _, i64 -22, !12, !13
+  ; CHECK-NEXT: DBG_VALUE _, i128 123492148938512984928424384934328985928, !12, !13
+    DBG_VALUE _, i32 0, !12, !13
+    DBG_VALUE _, i64 -22, !12, !13
+    DBG_VALUE _, i128 123492148938512984928424384934328985928, !12, !13
+    MOV32mr %stack.0.x.addr, 1, _, 0, _, %0
+    %eax = COPY %0
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/invalid-constant-pool-item.mir b/test/CodeGen/MIR/X86/invalid-constant-pool-item.mir
index de2ca4cca75..afd6c78546c 100644
--- a/test/CodeGen/MIR/X86/invalid-constant-pool-item.mir
+++ b/test/CodeGen/MIR/X86/invalid-constant-pool-item.mir
@@ -16,12 +16,10 @@ name:            test
 constants:
   - id:          0
     value:       'double 3.250000e+00'
-body:
-  - id: 0
-    name: entry
-    instructions:
-      # CHECK: [[@LINE+1]]:52: use of undefined constant '%const.10'
-      - '%xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.10, _'
-      - 'RETQ %xmm0'
+body: |
+  bb.0.entry:
+    ; CHECK: [[@LINE+1]]:47: use of undefined constant '%const.10'
+    %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.10, _
+    RETQ %xmm0
 ...
 
diff --git a/test/CodeGen/MIR/X86/invalid-target-flag-name.mir b/test/CodeGen/MIR/X86/invalid-target-flag-name.mir
index 1e1fc7b302d..313c5bdafed 100644
--- a/test/CodeGen/MIR/X86/invalid-target-flag-name.mir
+++ b/test/CodeGen/MIR/X86/invalid-target-flag-name.mir
@@ -14,13 +14,11 @@
 ...
 ---
 name: inc
-body:
-  - id: 0
-    name: entry
-    instructions:
-# CHECK: [[@LINE+1]]:50: use of undefined target flag 'x86-test'
-      - '%rax = MOV64rm %rip, 1, _, target-flags(x86-test) @G, _'
-      - '%eax = MOV32rm killed %rax, 1, _, 0, _'
-      - '%eax = INC32r killed %eax, implicit-def dead %eflags'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+  ; CHECK: [[@LINE+1]]:45: use of undefined target flag 'x86-test'
+    %rax = MOV64rm %rip, 1, _, target-flags(x86-test) @G, _
+    %eax = MOV32rm killed %rax, 1, _, 0, _
+    %eax = INC32r killed %eax, implicit-def dead %eflags
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/jump-table-info.mir b/test/CodeGen/MIR/X86/jump-table-info.mir
index 25cf9240526..a4e6f6a1728 100644
--- a/test/CodeGen/MIR/X86/jump-table-info.mir
+++ b/test/CodeGen/MIR/X86/jump-table-info.mir
@@ -68,48 +68,41 @@ jumpTable:
   entries:
     - id:        0
       blocks:    [ '%bb.3.lbl1', '%bb.4.lbl2', '%bb.5.lbl3', '%bb.6.lbl4' ]
-body:
-  - id:          0
-    name:        entry
-    successors:  [ '%bb.2.def', '%bb.1.entry' ]
-    instructions:
-      - '%eax = MOV32rr %edi, implicit-def %rax'
-      - 'CMP32ri8 %edi, 3, implicit-def %eflags'
-      - 'JA_1 %bb.2.def, implicit %eflags'
-  - id:          1
-    name:        entry
-    successors:  [ '%bb.3.lbl1', '%bb.4.lbl2', '%bb.5.lbl3', '%bb.6.lbl4' ]
-    instructions:
-    # CHECK: %rcx = LEA64r %rip, 1, _, %jump-table.0, _
-      - '%rcx = LEA64r %rip, 1, _, %jump-table.0, _'
-      - '%rax = MOVSX64rm32 %rcx, 4, %rax, 0, _'
-      - '%rax = ADD64rr %rax, %rcx, implicit-def %eflags'
-      - 'JMP64r %rax'
-  - id:          2
-    name:        def
-    instructions:
-      - '%eax = MOV32r0 implicit-def %eflags'
-      - 'RETQ %eax'
-  - id:          3
-    name:        lbl1
-    instructions:
-      - '%eax = MOV32ri 1'
-      - 'RETQ %eax'
-  - id:          4
-    name:        lbl2
-    instructions:
-      - '%eax = MOV32ri 2'
-      - 'RETQ %eax'
-  - id:          5
-    name:        lbl3
-    instructions:
-      - '%eax = MOV32ri 4'
-      - 'RETQ %eax'
-  - id:          6
-    name:        lbl4
-    instructions:
-      - '%eax = MOV32ri 8'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    successors: %bb.2.def, %bb.1.entry
+
+    %eax = MOV32rr %edi, implicit-def %rax
+    CMP32ri8 %edi, 3, implicit-def %eflags
+    JA_1 %bb.2.def, implicit %eflags
+
+  bb.1.entry:
+    successors: %bb.3.lbl1, %bb.4.lbl2, %bb.5.lbl3, %bb.6.lbl4
+    ; CHECK: %rcx = LEA64r %rip, 1, _, %jump-table.0, _
+    %rcx = LEA64r %rip, 1, _, %jump-table.0, _
+    %rax = MOVSX64rm32 %rcx, 4, %rax, 0, _
+    %rax = ADD64rr %rax, %rcx, implicit-def %eflags
+    JMP64r %rax
+
+  bb.2.def:
+    %eax = MOV32r0 implicit-def %eflags
+    RETQ %eax
+
+  bb.3.lbl1:
+    %eax = MOV32ri 1
+    RETQ %eax
+
+  bb.4.lbl2:
+    %eax = MOV32ri 2
+    RETQ %eax
+
+  bb.5.lbl3:
+    %eax = MOV32ri 4
+    RETQ %eax
+
+  bb.6.lbl4:
+    %eax = MOV32ri 8
+    RETQ %eax
 ...
 ---
 name:            test_jumptable2
@@ -118,47 +111,40 @@ jumpTable:
   entries:
     - id:        1
       blocks:    [ '%bb.3.lbl1', '%bb.4.lbl2', '%bb.5.lbl3', '%bb.6.lbl4' ]
-body:
-  - id:          0
-    name:        entry
-    successors:  [ '%bb.2.def', '%bb.1.entry' ]
-    instructions:
-      - '%eax = MOV32rr %edi, implicit-def %rax'
-      - 'CMP32ri8 %edi, 3, implicit-def %eflags'
-      - 'JA_1 %bb.2.def, implicit %eflags'
-  - id:          1
-    name:        entry
-    successors:  [ '%bb.3.lbl1', '%bb.4.lbl2', '%bb.5.lbl3', '%bb.6.lbl4' ]
-    instructions:
-    # Verify that the printer will use an id of 0 for this jump table:
-    # CHECK: %rcx = LEA64r %rip, 1, _, %jump-table.0, _
-      - '%rcx = LEA64r %rip, 1, _, %jump-table.1, _'
-      - '%rax = MOVSX64rm32 %rcx, 4, %rax, 0, _'
-      - '%rax = ADD64rr %rax, %rcx, implicit-def %eflags'
-      - 'JMP64r %rax'
-  - id:         2
-    name:       def
-    instructions:
-      - '%eax = MOV32r0 implicit-def %eflags'
-      - 'RETQ %eax'
-  - id:         3
-    name:       lbl1
-    instructions:
-      - '%eax = MOV32ri 1'
-      - 'RETQ %eax'
-  - id:         4
-    name:       lbl2
-    instructions:
-      - '%eax = MOV32ri 2'
-      - 'RETQ %eax'
-  - id:         5
-    name:       lbl3
-    instructions:
-      - '%eax = MOV32ri 4'
-      - 'RETQ %eax'
-  - id:         6
-    name:       lbl4
-    instructions:
-      - '%eax = MOV32ri 8'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    successors: %bb.2.def, %bb.1.entry
+
+    %eax = MOV32rr %edi, implicit-def %rax
+    CMP32ri8 %edi, 3, implicit-def %eflags
+    JA_1 %bb.2.def, implicit %eflags
+
+  bb.1.entry:
+    successors: %bb.3.lbl1, %bb.4.lbl2, %bb.5.lbl3, %bb.6.lbl4
+    ; Verify that the printer will use an id of 0 for this jump table:
+    ; CHECK: %rcx = LEA64r %rip, 1, _, %jump-table.0, _
+    %rcx = LEA64r %rip, 1, _, %jump-table.1, _
+    %rax = MOVSX64rm32 %rcx, 4, %rax, 0, _
+    %rax = ADD64rr %rax, %rcx, implicit-def %eflags
+    JMP64r %rax
+
+  bb.2.def:
+    %eax = MOV32r0 implicit-def %eflags
+    RETQ %eax
+
+  bb.3.lbl1:
+    %eax = MOV32ri 1
+    RETQ %eax
+
+  bb.4.lbl2:
+    %eax = MOV32ri 2
+    RETQ %eax
+
+  bb.5.lbl3:
+    %eax = MOV32ri 4
+    RETQ %eax
+
+  bb.6.lbl4:
+    %eax = MOV32ri 8
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/jump-table-redefinition-error.mir b/test/CodeGen/MIR/X86/jump-table-redefinition-error.mir
index c9d195adbd9..d4ab11f4078 100644
--- a/test/CodeGen/MIR/X86/jump-table-redefinition-error.mir
+++ b/test/CodeGen/MIR/X86/jump-table-redefinition-error.mir
@@ -38,45 +38,39 @@ jumpTable:
 # CHECK: [[@LINE+1]]:18: redefinition of jump table entry '%jump-table.0'
     - id:        0
       blocks:    [ '%bb.3.lbl1', '%bb.4.lbl2', '%bb.5.lbl3', '%bb.6.lbl4' ]
-body:
-  - id:          0
-    name:        entry
-    successors:  [ '%bb.2.def', '%bb.1.entry' ]
-    instructions:
-      - '%eax = MOV32rr %edi, implicit-def %rax'
-      - 'CMP32ri8 %edi, 3, implicit-def %eflags'
-      - 'JA_1 %bb.2.def, implicit %eflags'
-  - id:          1
-    name:        entry
-    successors:  [ '%bb.3.lbl1', '%bb.4.lbl2', '%bb.5.lbl3', '%bb.6.lbl4' ]
-    instructions:
-      - '%rcx = LEA64r %rip, 1, _, %jump-table.0, _'
-      - '%rax = MOVSX64rm32 %rcx, 4, %rax, 0, _'
-      - '%rax = ADD64rr %rax, %rcx, implicit-def %eflags'
-      - 'JMP64r %rax'
-  - id:          2
-    name:        def
-    instructions:
-      - '%eax = MOV32r0 implicit-def %eflags'
-      - 'RETQ %eax'
-  - id:          3
-    name:        lbl1
-    instructions:
-      - '%eax = MOV32ri 1'
-      - 'RETQ %eax'
-  - id:          4
-    name:        lbl2
-    instructions:
-      - '%eax = MOV32ri 2'
-      - 'RETQ %eax'
-  - id:          5
-    name:        lbl3
-    instructions:
-      - '%eax = MOV32ri 4'
-      - 'RETQ %eax'
-  - id:          6
-    name:        lbl4
-    instructions:
-      - '%eax = MOV32ri 8'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    successors: %bb.2.def, %bb.1.entry
+
+    %eax = MOV32rr %edi, implicit-def %rax
+    CMP32ri8 %edi, 3, implicit-def %eflags
+    JA_1 %bb.2.def, implicit %eflags
+
+  bb.1.entry:
+    successors: %bb.3.lbl1, %bb.4.lbl2, %bb.5.lbl3, %bb.6.lbl4
+
+    %rcx = LEA64r %rip, 1, _, %jump-table.0, _
+    %rax = MOVSX64rm32 %rcx, 4, %rax, 0, _
+    %rax = ADD64rr %rax, %rcx, implicit-def %eflags
+    JMP64r %rax
+
+  bb.2.def:
+    %eax = MOV32r0 implicit-def %eflags
+    RETQ %eax
+
+  bb.3.lbl1:
+    %eax = MOV32ri 1
+    RETQ %eax
+
+  bb.4.lbl2:
+    %eax = MOV32ri 2
+    RETQ %eax
+
+  bb.5.lbl3:
+    %eax = MOV32ri 4
+    RETQ %eax
+
+  bb.6.lbl4:
+    %eax = MOV32ri 8
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/killed-register-flag.mir b/test/CodeGen/MIR/X86/killed-register-flag.mir
index fd5f881b0fd..9e8f3ba3b36 100644
--- a/test/CodeGen/MIR/X86/killed-register-flag.mir
+++ b/test/CodeGen/MIR/X86/killed-register-flag.mir
@@ -19,25 +19,22 @@
 ...
 ---
 name:            foo
-body:
-  - id:          0
-    name:        entry
-    successors:  [ '%bb.1.less', '%bb.2.exit' ]
-    instructions:
-      - 'CMP32ri8 %edi, 10, implicit-def %eflags'
-      - 'JG_1 %bb.2.exit, implicit %eflags'
-  - id:          1
-    name:        less
-    instructions:
-      # CHECK:      - '%eax = MOV32r0
-      # CHECK-NEXT: - 'RETQ killed %eax
-      - '%eax = MOV32r0 implicit-def %eflags'
-      - 'RETQ killed %eax'
-  - id:          2
-    name:        exit
-    instructions:
-      # CHECK:      - '%eax = COPY killed %edi
-      # CHECK-NEXT: - 'RETQ killed %eax
-      - '%eax = COPY killed %edi'
-      - 'RETQ killed %eax'
+body: |
+  bb.0.entry:
+    successors: %bb.1.less, %bb.2.exit
+
+    CMP32ri8 %edi, 10, implicit-def %eflags
+    JG_1 %bb.2.exit, implicit %eflags
+
+  bb.1.less:
+    ; CHECK:      %eax = MOV32r0
+    ; CHECK-NEXT: RETQ killed %eax
+    %eax = MOV32r0 implicit-def %eflags
+    RETQ killed %eax
+
+  bb.2.exit:
+    ; CHECK:      %eax = COPY killed %edi
+    ; CHECK-NEXT: RETQ killed %eax
+    %eax = COPY killed %edi
+    RETQ killed %eax
 ...
diff --git a/test/CodeGen/MIR/X86/large-cfi-offset-number-error.mir b/test/CodeGen/MIR/X86/large-cfi-offset-number-error.mir
index 5f395b1ef01..93ce30abec7 100644
--- a/test/CodeGen/MIR/X86/large-cfi-offset-number-error.mir
+++ b/test/CodeGen/MIR/X86/large-cfi-offset-number-error.mir
@@ -16,14 +16,12 @@ frameInfo:
   stackSize:       4040
 stack:
   - { id: 0, name: tmp, offset: -4176, size: 4168, alignment: 4 }
-body:
-  - id:              0
-    name:            entry
-    instructions:
-      - '%rsp = SUB64ri32 %rsp, 4040, implicit-def dead %eflags'
-     # CHECK: [[@LINE+1]]:46: expected a 32 bit integer (the cfi offset is too large)
-      - 'CFI_INSTRUCTION .cfi_def_cfa_offset 123456789123456'
-      - '%rsp = ADD64ri32 %rsp, 4040, implicit-def dead %eflags'
-      - 'RETQ'
+body: |
+  bb.0.entry:
+    %rsp = SUB64ri32 %rsp, 4040, implicit-def dead %eflags
+    ; CHECK: [[@LINE+1]]:41: expected a 32 bit integer (the cfi offset is too large)
+    CFI_INSTRUCTION .cfi_def_cfa_offset 123456789123456
+    %rsp = ADD64ri32 %rsp, 4040, implicit-def dead %eflags
+    RETQ
 ...
 
diff --git a/test/CodeGen/MIR/X86/large-immediate-operand-error.mir b/test/CodeGen/MIR/X86/large-immediate-operand-error.mir
index fead666e164..f815c63e18e 100644
--- a/test/CodeGen/MIR/X86/large-immediate-operand-error.mir
+++ b/test/CodeGen/MIR/X86/large-immediate-operand-error.mir
@@ -10,11 +10,9 @@
 ...
 ---
 name:            foo
-body:
- - id:           0
-   name:         entry
-   instructions:
-# CHECK: [[@LINE+1]]:24: integer literal is too large to be an immediate operand
-     - '%eax = MOV32ri 12346127502983478823754212949184914'
-     - 'RETQ %eax'
+body: |
+  bb.0.entry:
+  ; CHECK: [[@LINE+1]]:20: integer literal is too large to be an immediate operand
+    %eax = MOV32ri 12346127502983478823754212949184914
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/large-index-number-error.mir b/test/CodeGen/MIR/X86/large-index-number-error.mir
index fdb25c907f5..272cd685b38 100644
--- a/test/CodeGen/MIR/X86/large-index-number-error.mir
+++ b/test/CodeGen/MIR/X86/large-index-number-error.mir
@@ -18,18 +18,16 @@
 ...
 ---
 name:            foo
-body:
- - id: 0
-   name: entry
-   instructions:
-     - '%eax = MOV32rm %rdi, 1, _, 0, _'
-     - 'CMP32ri8 %eax, 10, implicit-def %eflags'
-     # CHECK: [[@LINE+1]]:14: expected 32-bit integer (too large)
-     - 'JG_1 %bb.123456789123456, implicit %eflags'
- - id: 1
-   instructions:
-     - '%eax = MOV32r0 implicit-def %eflags'
- - id: 2
-   instructions:
-     - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    %eax = MOV32rm %rdi, 1, _, 0, _
+    CMP32ri8 %eax, 10, implicit-def %eflags
+    ; CHECK: [[@LINE+1]]:10: expected 32-bit integer (too large)
+    JG_1 %bb.123456789123456, implicit %eflags
+
+  bb.1:
+    %eax = MOV32r0 implicit-def %eflags
+
+  bb.2:
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/large-offset-number-error.mir b/test/CodeGen/MIR/X86/large-offset-number-error.mir
index 54d8e41064a..5463cdbce44 100644
--- a/test/CodeGen/MIR/X86/large-offset-number-error.mir
+++ b/test/CodeGen/MIR/X86/large-offset-number-error.mir
@@ -14,13 +14,11 @@
 ...
 ---
 name: inc
-body:
-  - id: 0
-    name: entry
-    instructions:
-      # CHECK: [[@LINE+1]]:42: expected 64-bit integer (too large)
-      - '%rax = MOV64rm %rip, 1, _, @G + 123456789123456789123456789, _'
-      - '%eax = MOV32rm %rax, 1, _, 0, _'
-      - '%eax = INC32r %eax implicit-def %eflags'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    ; CHECK: [[@LINE+1]]:37: expected 64-bit integer (too large)
+    %rax = MOV64rm %rip, 1, _, @G + 123456789123456789123456789, _
+    %eax = MOV32rm %rax, 1, _, 0, _
+    %eax = INC32r %eax implicit-def %eflags
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/large-size-in-memory-operand-error.mir b/test/CodeGen/MIR/X86/large-size-in-memory-operand-error.mir
index 09e17bfbd44..c570f0992a3 100644
--- a/test/CodeGen/MIR/X86/large-size-in-memory-operand-error.mir
+++ b/test/CodeGen/MIR/X86/large-size-in-memory-operand-error.mir
@@ -14,13 +14,11 @@ name:            test
 tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
-body:
-  - id:          0
-    name:        entry
-    liveins:     [ '%rdi' ]
-    instructions:
-# CHECK: [[@LINE+1]]:58: expected 64-bit integer (too large)
-      - '%eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 12345678912345678924218574857 from %ir.a)'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    liveins: %rdi
+  ; CHECK: [[@LINE+1]]:53: expected 64-bit integer (too large)
+    %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 12345678912345678924218574857 from %ir.a)
+    RETQ %eax
 ...
 
diff --git a/test/CodeGen/MIR/X86/liveout-register-mask.mir b/test/CodeGen/MIR/X86/liveout-register-mask.mir
index 5f193ab24b5..7ded7287060 100644
--- a/test/CodeGen/MIR/X86/liveout-register-mask.mir
+++ b/test/CodeGen/MIR/X86/liveout-register-mask.mir
@@ -26,18 +26,17 @@ frameInfo:
   hasCalls:      true
 fixedStack:
   - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16 }
-body:
-  - id:          0
-    name:        entry
-    liveins:     [ '%rdi', '%rsi', '%rbp' ]
-    instructions:
-      - 'frame-setup PUSH64r killed %rbp, implicit-def %rsp, implicit %rsp'
-      - CFI_INSTRUCTION .cfi_def_cfa_offset 16
-      - 'CFI_INSTRUCTION .cfi_offset %rbp, -16'
-      - '%rbp = frame-setup MOV64rr %rsp'
-      - 'CFI_INSTRUCTION .cfi_def_cfa_register %rbp'
-# CHECK: PATCHPOINT 5, 5, 0, 2, 0, %rdi, %rsi, csr_64, liveout(%esp, %rsp, %sp, %spl),
-      - 'PATCHPOINT 5, 5, 0, 2, 0, %rdi, %rsi, csr_64, liveout(%esp, %rsp, %sp, %spl), implicit-def dead early-clobber %r11, implicit-def %rsp, implicit-def dead %rax'
-      - '%rbp = POP64r implicit-def %rsp, implicit %rsp'
-      - RETQ
+body: |
+  bb.0.entry:
+    liveins: %rdi, %rsi, %rbp
+
+    frame-setup PUSH64r killed %rbp, implicit-def %rsp, implicit %rsp
+    CFI_INSTRUCTION .cfi_def_cfa_offset 16
+    CFI_INSTRUCTION .cfi_offset %rbp, -16
+    %rbp = frame-setup MOV64rr %rsp
+    CFI_INSTRUCTION .cfi_def_cfa_register %rbp
+  ; CHECK: PATCHPOINT 5, 5, 0, 2, 0, %rdi, %rsi, csr_64, liveout(%esp, %rsp, %sp, %spl),
+    PATCHPOINT 5, 5, 0, 2, 0, %rdi, %rsi, csr_64, liveout(%esp, %rsp, %sp, %spl), implicit-def dead early-clobber %r11, implicit-def %rsp, implicit-def dead %rax
+    %rbp = POP64r implicit-def %rsp, implicit %rsp
+    RETQ
 ...
diff --git a/test/CodeGen/MIR/X86/machine-basic-block-operands.mir b/test/CodeGen/MIR/X86/machine-basic-block-operands.mir
index 25cb7a1211a..0d7a9f8ef34 100644
--- a/test/CodeGen/MIR/X86/machine-basic-block-operands.mir
+++ b/test/CodeGen/MIR/X86/machine-basic-block-operands.mir
@@ -33,45 +33,41 @@
 ---
 # CHECK: name: foo
 name:            foo
-body:
- # CHECK: name: entry
- - id:              0
-   name:            entry
-   successors:      [ '%bb.1.less', '%bb.2.exit' ]
-   instructions:
-     - '%eax = MOV32rm %rdi, 1, _, 0, _'
-     # CHECK:      - 'CMP32ri8 %eax, 10
-     # CHECK-NEXT: - 'JG_1 %bb.2.exit
-     - 'CMP32ri8 %eax, 10, implicit-def %eflags'
-     - 'JG_1 %bb.2.exit, implicit %eflags'
- # CHECK: name: less
- - id:              1
-   name:            less
-   instructions:
-     - '%eax = MOV32r0 implicit-def %eflags'
- - id:              2
-   name:            exit
-   instructions:
-     - 'RETQ %eax'
+body: |
+  ; CHECK: bb.0.entry
+  bb.0.entry:
+    successors: %bb.1.less, %bb.2.exit
+
+    %eax = MOV32rm %rdi, 1, _, 0, _
+    ; CHECK:      CMP32ri8 %eax, 10
+    ; CHECK-NEXT: JG_1 %bb.2.exit
+    CMP32ri8 %eax, 10, implicit-def %eflags
+    JG_1 %bb.2.exit, implicit %eflags
+  ; CHECK: bb.1.less:
+
+  bb.1.less:
+    %eax = MOV32r0 implicit-def %eflags
+
+  bb.2.exit:
+    RETQ %eax
 ...
 ---
 # CHECK: name: bar
 name:            bar
-body:
- # CHECK: name: entry
- - id: 0
-   name: entry
-   successors:  [ '%bb.1', '%bb.3' ]
-   instructions:
-     - '%eax = MOV32rm %rdi, 1, _, 0, _'
-     # CHECK:      - 'CMP32ri8 %eax, 10
-     # CHECK-NEXT: - 'JG_1 %bb.2
-     - 'CMP32ri8 %eax, 10, implicit-def %eflags'
-     - 'JG_1 %bb.3, implicit %eflags'
- - id: 1
-   instructions:
-     - '%eax = MOV32r0 implicit-def %eflags'
- - id: 3
-   instructions:
-     - 'RETQ %eax'
+body: |
+  ; CHECK: bb.0.entry:
+  bb.0.entry:
+    successors: %bb.1, %bb.3
+
+    %eax = MOV32rm %rdi, 1, _, 0, _
+    ; CHECK:      CMP32ri8 %eax, 10
+    ; CHECK-NEXT: JG_1 %bb.2
+    CMP32ri8 %eax, 10, implicit-def %eflags
+    JG_1 %bb.3, implicit %eflags
+
+  bb.1:
+    %eax = MOV32r0 implicit-def %eflags
+
+  bb.3:
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/machine-instructions.mir b/test/CodeGen/MIR/X86/machine-instructions.mir
index c319db0892b..0e46d01e0bd 100644
--- a/test/CodeGen/MIR/X86/machine-instructions.mir
+++ b/test/CodeGen/MIR/X86/machine-instructions.mir
@@ -14,12 +14,10 @@
 ---
 # CHECK: name: inc
 name:            inc
-body:
- - id:           0
-   name:         entry
-   instructions:
-     # CHECK:      MOV32rr
-     # CHECK-NEXT: RETQ
-     - '%eax = MOV32rr %eax'
-     - ' RETQ %eax'
+body: |
+  bb.0.entry:
+    ; CHECK:      MOV32rr
+    ; CHECK-NEXT: RETQ
+    %eax = MOV32rr %eax
+     RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/machine-verifier.mir b/test/CodeGen/MIR/X86/machine-verifier.mir
index 608a90ea4de..2cde970d751 100644
--- a/test/CodeGen/MIR/X86/machine-verifier.mir
+++ b/test/CodeGen/MIR/X86/machine-verifier.mir
@@ -11,13 +11,11 @@
 ...
 ---
 name:            inc
-body:
- - id:           0
-   name:         entry
-   liveins:      [ '%edi' ]
-   instructions:
-   # CHECK: *** Bad machine code: Too few operands ***
-   # CHECK: instruction: COPY2 operands expected, but 0 given.
-     - 'COPY'
-     - 'RETQ'
+body: |
+  bb.0.entry:
+    liveins: %edi
+   ; CHECK: *** Bad machine code: Too few operands ***
+   ; CHECK: instruction: COPY2 operands expected, but 0 given.
+    COPY
+    RETQ
 ...
diff --git a/test/CodeGen/MIR/X86/memory-operands.mir b/test/CodeGen/MIR/X86/memory-operands.mir
index 1bde368f576..7b4d60b0044 100644
--- a/test/CodeGen/MIR/X86/memory-operands.mir
+++ b/test/CodeGen/MIR/X86/memory-operands.mir
@@ -117,48 +117,42 @@ name:            test
 tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
-body:
-  - id:          0
-    name:        entry
-    liveins:     [ '%rdi' ]
-    instructions:
-# CHECK:      %eax = MOV32rm %rdi, 1, _, 0, _ :: (load 4 from %ir.a)
-# CHECK-NEXT: MOV32mi killed %rdi, 1, _, 0, _, 42 :: (store 4 into %ir.a)
-      - '%eax = MOV32rm %rdi, 1, _, 0, _ :: (load 4 from %ir.a)'
-      - 'MOV32mi killed %rdi, 1, _, 0, _, 42 :: (store 4 into %ir.a)'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    liveins: %rdi
+  ; CHECK:      %eax = MOV32rm %rdi, 1, _, 0, _ :: (load 4 from %ir.a)
+  ; CHECK-NEXT: MOV32mi killed %rdi, 1, _, 0, _, 42 :: (store 4 into %ir.a)
+    %eax = MOV32rm %rdi, 1, _, 0, _ :: (load 4 from %ir.a)
+    MOV32mi killed %rdi, 1, _, 0, _, 42 :: (store 4 into %ir.a)
+    RETQ %eax
 ...
 ---
 name:            test2
 tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
-body:
-  - id:          0
-    name:        entry2
-    liveins:     [ '%rdi' ]
-    instructions:
-# CHECK: INC32m killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (store 4 into %ir."a value"), (load 4 from %ir."a value")
-      - 'INC32m killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (store 4 into %ir."a value"), (load 4 from %ir."a value")'
-      - RETQ
+body: |
+  bb.0.entry2:
+    liveins: %rdi
+  ; CHECK: INC32m killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (store 4 into %ir."a value"), (load 4 from %ir."a value")
+    INC32m killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (store 4 into %ir."a value"), (load 4 from %ir."a value")
+    RETQ
 ...
 ---
 name:            volatile_inc
 tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
-body:
-  - id:          0
-    name:        entry
-    liveins:     [ '%rdi' ]
-    instructions:
-    # CHECK: name: volatile_inc
-    # CHECK: %eax = MOV32rm %rdi, 1, _, 0, _ :: (volatile load 4 from %ir.x)
-    # CHECK: MOV32mr killed %rdi, 1, _, 0, _, %eax :: (volatile store 4 into %ir.x)
-      - '%eax = MOV32rm %rdi, 1, _, 0, _ :: (volatile load 4 from %ir.x)'
-      - '%eax = INC32r killed %eax, implicit-def dead %eflags'
-      - 'MOV32mr killed %rdi, 1, _, 0, _, %eax :: (volatile store 4 into %ir.x)'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    liveins: %rdi
+    ; CHECK: name: volatile_inc
+    ; CHECK: %eax = MOV32rm %rdi, 1, _, 0, _ :: (volatile load 4 from %ir.x)
+    ; CHECK: MOV32mr killed %rdi, 1, _, 0, _, %eax :: (volatile store 4 into %ir.x)
+    %eax = MOV32rm %rdi, 1, _, 0, _ :: (volatile load 4 from %ir.x)
+    %eax = INC32r killed %eax, implicit-def dead %eflags
+    MOV32mr killed %rdi, 1, _, 0, _, %eax :: (volatile store 4 into %ir.x)
+    RETQ %eax
 ...
 ---
 name:            non_temporal_store
@@ -166,76 +160,68 @@ tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
   - { reg: '%esi' }
-body:
-  - id:          0
-    name:        entry
-    liveins:     [ '%esi', '%rdi' ]
-    instructions:
-# CHECK: name: non_temporal_store
-# CHECK: MOVNTImr killed %rdi, 1, _, 0, _, killed %esi :: (non-temporal store 4 into %ir.a)
-      - 'MOVNTImr killed %rdi, 1, _, 0, _, killed %esi :: (non-temporal store 4 into %ir.a)'
-      - RETQ
+body: |
+  bb.0.entry:
+    liveins: %esi, %rdi
+  ; CHECK: name: non_temporal_store
+  ; CHECK: MOVNTImr killed %rdi, 1, _, 0, _, killed %esi :: (non-temporal store 4 into %ir.a)
+    MOVNTImr killed %rdi, 1, _, 0, _, killed %esi :: (non-temporal store 4 into %ir.a)
+    RETQ
 ...
 ---
 name:            invariant_load
 tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
-body:
-  - id:          0
-    name:        entry
-    liveins:     [ '%rdi' ]
-    instructions:
-# CHECK: name: invariant_load
-# CHECK: %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (invariant load 4 from %ir.x)
-      - '%eax = MOV32rm killed %rdi, 1, _, 0, _ :: (invariant load 4 from %ir.x)'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    liveins: %rdi
+  ; CHECK: name: invariant_load
+  ; CHECK: %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (invariant load 4 from %ir.x)
+    %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (invariant load 4 from %ir.x)
+    RETQ %eax
 ...
 ---
 name:            memory_offset
 tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
-body:
-  - id:          0
-    name:        entry
-    liveins:     [ '%rdi' ]
-    instructions:
-# CHECK: name: memory_offset
-# CHECK:      %xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec)
-# CHECK-NEXT: %xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16)
-# CHECK:      MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec)
-# CHECK-NEXT: MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16)
-      - '%xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec)'
-      - '%xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16)'
-      - '%xmm2 = FsFLD0SS'
-      - '%xmm1 = MOVSSrr killed %xmm1, killed %xmm2'
-      - 'MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec)'
-      - 'MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16)'
-      - RETQ
+body: |
+  bb.0.entry:
+    liveins: %rdi
+  ; CHECK: name: memory_offset
+  ; CHECK:      %xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec)
+  ; CHECK-NEXT: %xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16)
+  ; CHECK:      MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec)
+  ; CHECK-NEXT: MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16)
+    %xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec)
+    %xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16)
+    %xmm2 = FsFLD0SS
+    %xmm1 = MOVSSrr killed %xmm1, killed %xmm2
+    MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec)
+    MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16)
+    RETQ
 ...
 ---
 name:            memory_alignment
 tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
-body:
-  - id:          0
-    name:        entry
-    liveins:     [ '%rdi' ]
-    instructions:
-# CHECK: name: memory_alignment
-# CHECK:      %xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, align 32)
-# CHECK-NEXT: %xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32)
-# CHECK:      MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec, align 32)
-# CHECK-NEXT: MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32)
-      - '%xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, align 32)'
-      - '%xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32)'
-      - '%xmm2 = FsFLD0SS'
-      - '%xmm1 = MOVSSrr killed %xmm1, killed %xmm2'
-      - 'MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec, align 32)'
-      - 'MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32)'
-      - RETQ
+body: |
+  bb.0.entry:
+    liveins: %rdi
+  ; CHECK: name: memory_alignment
+  ; CHECK:      %xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, align 32)
+  ; CHECK-NEXT: %xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32)
+  ; CHECK:      MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec, align 32)
+  ; CHECK-NEXT: MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32)
+    %xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, align 32)
+    %xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32)
+    %xmm2 = FsFLD0SS
+    %xmm1 = MOVSSrr killed %xmm1, killed %xmm2
+    MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec, align 32)
+    MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32)
+    RETQ
 ...
 ---
 name:            constant_pool_psv
@@ -245,17 +231,15 @@ liveins:
 constants:
   - id:          0
     value:       'double 3.250000e+00'
-body:
-  - id:          0
-    name:        entry
-    liveins:     [ '%xmm0' ]
-    instructions:
-# CHECK: name: constant_pool_psv
-# CHECK:      %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ :: (load 8 from constant-pool)
-# CHECK-NEXT: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ :: (load 8 from constant-pool + 8)
-      - '%xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ :: (load 8 from constant-pool)'
-      - '%xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ :: (load 8 from constant-pool + 8)'
-      - 'RETQ %xmm0'
+body: |
+  bb.0.entry:
+    liveins: %xmm0
+  ; CHECK: name: constant_pool_psv
+  ; CHECK:      %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ :: (load 8 from constant-pool)
+  ; CHECK-NEXT: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ :: (load 8 from constant-pool + 8)
+    %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ :: (load 8 from constant-pool)
+    %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ :: (load 8 from constant-pool + 8)
+    RETQ %xmm0
 ...
 ---
 name:            stack_psv
@@ -268,47 +252,41 @@ frameInfo:
   maxCallFrameSize: 16
 fixedStack:
   - { id: 0, offset: 0, size: 10, alignment: 16, isImmutable: true, isAliased: false }
-body:
-  - id:          0
-    name:        entry
-    instructions:
-      - '%rsp = frame-setup SUB64ri8 %rsp, 24, implicit-def dead %eflags'
-      - CFI_INSTRUCTION .cfi_def_cfa_offset 32
-      - 'LD_F80m %rsp, 1, _, 32, _, implicit-def dead %fpsw'
-# CHECK: name: stack_psv
-# CHECK: ST_FP80m %rsp, 1, _, 0, _, implicit-def dead %fpsw :: (store 10 into stack, align 16)
-      - 'ST_FP80m %rsp, 1, _, 0, _, implicit-def dead %fpsw :: (store 10 into stack, align 16)'
-      - 'CALL64pcrel32 $cosl, csr_64, implicit %rsp, implicit-def %rsp, implicit-def %fp0'
-      - '%rsp = ADD64ri8 %rsp, 24, implicit-def dead %eflags'
-      - RETQ
+body: |
+  bb.0.entry:
+    %rsp = frame-setup SUB64ri8 %rsp, 24, implicit-def dead %eflags
+    CFI_INSTRUCTION .cfi_def_cfa_offset 32
+    LD_F80m %rsp, 1, _, 32, _, implicit-def dead %fpsw
+  ; CHECK: name: stack_psv
+  ; CHECK: ST_FP80m %rsp, 1, _, 0, _, implicit-def dead %fpsw :: (store 10 into stack, align 16)
+    ST_FP80m %rsp, 1, _, 0, _, implicit-def dead %fpsw :: (store 10 into stack, align 16)
+    CALL64pcrel32 $cosl, csr_64, implicit %rsp, implicit-def %rsp, implicit-def %fp0
+    %rsp = ADD64ri8 %rsp, 24, implicit-def dead %eflags
+    RETQ
 ...
 ---
 name:            got_psv
 tracksRegLiveness: true
-body:
-  - id:          0
-    name:        entry
-    instructions:
-# CHECK: name: got_psv
-# CHECK: %rax = MOV64rm %rip, 1, _, @G, _ :: (load 8 from got)
-      - '%rax = MOV64rm %rip, 1, _, @G, _ :: (load 8 from got)'
-      - '%eax = MOV32rm killed %rax, 1, _, 0, _'
-      - '%eax = INC32r killed %eax, implicit-def dead %eflags'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+  ; CHECK: name: got_psv
+  ; CHECK: %rax = MOV64rm %rip, 1, _, @G, _ :: (load 8 from got)
+    %rax = MOV64rm %rip, 1, _, @G, _ :: (load 8 from got)
+    %eax = MOV32rm killed %rax, 1, _, 0, _
+    %eax = INC32r killed %eax, implicit-def dead %eflags
+    RETQ %eax
 ...
 ---
 name:            global_value
 tracksRegLiveness: true
-body:
-  - id:          0
-    name:        entry
-    instructions:
-      - '%rax = MOV64rm %rip, 1, _, @G, _'
-# CHECK: name: global_value
-# CHECK: %eax = MOV32rm killed %rax, 1, _, 0, _ :: (load 4 from %ir.G)
-      - '%eax = MOV32rm killed %rax, 1, _, 0, _ :: (load 4 from %ir.G)'
-      - '%eax = INC32r killed %eax, implicit-def dead %eflags'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    %rax = MOV64rm %rip, 1, _, @G, _
+  ; CHECK: name: global_value
+  ; CHECK: %eax = MOV32rm killed %rax, 1, _, 0, _ :: (load 4 from %ir.G)
+    %eax = MOV32rm killed %rax, 1, _, 0, _ :: (load 4 from %ir.G)
+    %eax = INC32r killed %eax, implicit-def dead %eflags
+    RETQ %eax
 ...
 ---
 name:            jumptable_psv
@@ -320,49 +298,43 @@ jumpTable:
   entries:
     - id:        0
       blocks:    [ '%bb.3.lbl1', '%bb.4.lbl2', '%bb.5.lbl3', '%bb.6.lbl4' ]
-body:
-  - id:          0
-    name:        entry
-    successors:  [ '%bb.2.def', '%bb.1.entry' ]
-    liveins:     [ '%edi' ]
-    instructions:
-      - '%eax = MOV32rr %edi, implicit-def %rax'
-      - 'CMP32ri8 killed %edi, 3, implicit-def %eflags'
-      - 'JA_1 %bb.2.def, implicit killed %eflags'
-  - id:          1
-    name:        entry
-    successors:  [ '%bb.3.lbl1', '%bb.4.lbl2', '%bb.5.lbl3', '%bb.6.lbl4' ]
-    liveins:     [ '%rax' ]
-    instructions:
-      - '%rcx = LEA64r %rip, 1, _, %jump-table.0, _'
-# CHECK: name: jumptable_psv
-# CHECK: %rax = MOVSX64rm32 %rcx, 4, killed %rax, 0, _ :: (load 4 from jump-table, align 8)
-      - '%rax = MOVSX64rm32 %rcx, 4, killed %rax, 0, _ :: (load 4 from jump-table, align 8)'
-      - '%rax = ADD64rr killed %rax, killed %rcx, implicit-def dead %eflags'
-      - 'JMP64r killed %rax'
-  - id:              2
-    name:            def
-    instructions:
-      - '%eax = MOV32r0 implicit-def dead %eflags'
-      - 'RETQ %eax'
-  - id:              3
-    name:            lbl1
-    instructions:
-      - '%eax = MOV32ri 1'
-      - 'RETQ %eax'
-  - id:              4
-    name:            lbl2
-    instructions:
-      - '%eax = MOV32ri 2'
-      - 'RETQ %eax'
-  - id:              5
-    name:            lbl3
-    instructions:
-      - '%eax = MOV32ri 4'
-      - 'RETQ %eax'
-  - id:              6
-    name:            lbl4
-    instructions:
-      - '%eax = MOV32ri 8'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    successors: %bb.2.def, %bb.1.entry
+    liveins: %edi
+
+    %eax = MOV32rr %edi, implicit-def %rax
+    CMP32ri8 killed %edi, 3, implicit-def %eflags
+    JA_1 %bb.2.def, implicit killed %eflags
+
+  bb.1.entry:
+    successors: %bb.3.lbl1, %bb.4.lbl2, %bb.5.lbl3, %bb.6.lbl4
+    liveins: %rax
+
+    %rcx = LEA64r %rip, 1, _, %jump-table.0, _
+  ; CHECK: name: jumptable_psv
+  ; CHECK: %rax = MOVSX64rm32 %rcx, 4, killed %rax, 0, _ :: (load 4 from jump-table, align 8)
+    %rax = MOVSX64rm32 %rcx, 4, killed %rax, 0, _ :: (load 4 from jump-table, align 8)
+    %rax = ADD64rr killed %rax, killed %rcx, implicit-def dead %eflags
+    JMP64r killed %rax
+
+  bb.2.def:
+    %eax = MOV32r0 implicit-def dead %eflags
+    RETQ %eax
+
+  bb.3.lbl1:
+    %eax = MOV32ri 1
+    RETQ %eax
+
+  bb.4.lbl2:
+    %eax = MOV32ri 2
+    RETQ %eax
+
+  bb.5.lbl3:
+    %eax = MOV32ri 4
+    RETQ %eax
+
+  bb.6.lbl4:
+    %eax = MOV32ri 8
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/metadata-operands.mir b/test/CodeGen/MIR/X86/metadata-operands.mir
index c509b302ce9..461b2064eea 100644
--- a/test/CodeGen/MIR/X86/metadata-operands.mir
+++ b/test/CodeGen/MIR/X86/metadata-operands.mir
@@ -50,16 +50,14 @@ frameInfo:
   maxAlignment:  4
 stack:
   - { id: 0, name: x.addr, size: 4, alignment: 4 }
-body:
-  - id:          0
-    name:        entry
-    liveins:     [ '%edi' ]
-    instructions:
-      # CHECK:      %0 = COPY %edi
-      # CHECK-NEXT: DBG_VALUE _, 0, !12, !13
-      - '%0 = COPY %edi'
-      - 'DBG_VALUE _, 0, !12, ! 13'
-      - 'MOV32mr %stack.0.x.addr, 1, _, 0, _, %0'
-      - '%eax = COPY %0'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    liveins: %edi
+    ; CHECK:      %0 = COPY %edi
+    ; CHECK-NEXT: DBG_VALUE _, 0, !12, !13
+    %0 = COPY %edi
+    DBG_VALUE _, 0, !12, ! 13
+    MOV32mr %stack.0.x.addr, 1, _, 0, _, %0
+    %eax = COPY %0
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/missing-closing-quote.mir b/test/CodeGen/MIR/X86/missing-closing-quote.mir
index f188d3ad8cf..9f4b369a3df 100644
--- a/test/CodeGen/MIR/X86/missing-closing-quote.mir
+++ b/test/CodeGen/MIR/X86/missing-closing-quote.mir
@@ -13,12 +13,10 @@
 ...
 ---
 name:            test
-body:
-  - id:          0
-    name:        entry
-    instructions:
-      # CHECK: [[@LINE+1]]:53: end of machine instruction reached before the closing '"'
-      - '%rax = MOV64rm %rip, 1, _, @"quoted name, _'
-      - '%eax = MOV32rm killed %rax, 1, _, 0, _'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    ; CHECK: [[@LINE+1]]:48: end of machine instruction reached before the closing '"'
+    %rax = MOV64rm %rip, 1, _, @"quoted name, _
+    %eax = MOV32rm killed %rax, 1, _, 0, _
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/missing-comma.mir b/test/CodeGen/MIR/X86/missing-comma.mir
index 54c67ac6c91..092995e59c7 100644
--- a/test/CodeGen/MIR/X86/missing-comma.mir
+++ b/test/CodeGen/MIR/X86/missing-comma.mir
@@ -10,12 +10,10 @@
 ...
 ---
 name:            foo
-body:
- - id:           0
-   name:         entry
-   instructions:
-     # CHECK: [[@LINE+1]]:29: expected ',' before the next machine operand
-     - '%eax = XOR32rr %eax %eflags'
-     - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    ; CHECK: [[@LINE+1]]:25: expected ',' before the next machine operand
+    %eax = XOR32rr %eax %eflags
+    RETQ %eax
 ...
 
diff --git a/test/CodeGen/MIR/X86/missing-implicit-operand.mir b/test/CodeGen/MIR/X86/missing-implicit-operand.mir
index b610f89d82b..0135c756e13 100644
--- a/test/CodeGen/MIR/X86/missing-implicit-operand.mir
+++ b/test/CodeGen/MIR/X86/missing-implicit-operand.mir
@@ -21,21 +21,18 @@
 ...
 ---
 name:            foo
-body:
- - id:              0
-   name:            entry
-   successors:      [ '%bb.1.less', '%bb.2.exit' ]
-   instructions:
-     - '%eax = MOV32rm %rdi, 1, _, 0, _'
-     - 'CMP32ri8 %eax, 10, implicit-def %eflags'
-# CHECK: [[@LINE+1]]:24: missing implicit register operand 'implicit %eflags'
-     - 'JG_1 %bb.2.exit'
- - id:              1
-   name:            less
-   instructions:
-     - '%eax = MOV32r0 implicit-def %eflags'
- - id:              2
-   name:            exit
-   instructions:
-     - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    successors: %bb.1.less, %bb.2.exit
+
+    %eax = MOV32rm %rdi, 1, _, 0, _
+    CMP32ri8 %eax, 10, implicit-def %eflags
+  ; CHECK: [[@LINE+1]]:20: missing implicit register operand 'implicit %eflags'
+    JG_1 %bb.2.exit
+
+  bb.1.less:
+    %eax = MOV32r0 implicit-def %eflags
+
+  bb.2.exit:
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/missing-instruction.mir b/test/CodeGen/MIR/X86/missing-instruction.mir
deleted file mode 100644
index 8d11ab5eaab..00000000000
--- a/test/CodeGen/MIR/X86/missing-instruction.mir
+++ /dev/null
@@ -1,19 +0,0 @@
-# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s
-
---- |
-
-  define void @foo() {
-  entry:
-    ret void
-  }
-
-...
----
-name:            foo
-body:
- - id:           0
-   name:         entry
-   instructions:
-     # CHECK: [[@LINE+1]]:9: expected a machine instruction
-     - ''
-...
diff --git a/test/CodeGen/MIR/X86/named-registers.mir b/test/CodeGen/MIR/X86/named-registers.mir
index 91ed4856867..e547c326563 100644
--- a/test/CodeGen/MIR/X86/named-registers.mir
+++ b/test/CodeGen/MIR/X86/named-registers.mir
@@ -12,12 +12,10 @@
 ---
 # CHECK: name: foo
 name:            foo
-body:
- - id:           0
-   name:         entry
-   instructions:
-     # CHECK:      - '%eax = MOV32r0
-     # CHECK-NEXT: - 'RETQ %eax
-     - '%eax = MOV32r0 implicit-def %eflags'
-     - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    ; CHECK:      %eax = MOV32r0
+    ; CHECK-NEXT: RETQ %eax
+    %eax = MOV32r0 implicit-def %eflags
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/newline-handling.mir b/test/CodeGen/MIR/X86/newline-handling.mir
new file mode 100644
index 00000000000..a61df00ce39
--- /dev/null
+++ b/test/CodeGen/MIR/X86/newline-handling.mir
@@ -0,0 +1,109 @@
+# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s
+
+--- |
+
+  define i32 @foo(i32 %a) {
+  entry:
+    %0 = icmp sle i32 %a, 10
+    br i1 %0, label %less, label %exit
+
+  less:
+    ret i32 0
+
+  exit:
+    ret i32 %a
+  }
+
+  define i32 @bar(i32 %a) {
+  entry:
+    %0 = icmp sle i32 %a, 10
+    br i1 %0, label %less, label %exit
+
+  less:
+    ret i32 0
+
+  exit:
+    ret i32 %a
+  }
+
+...
+---
+name:            foo
+tracksRegLiveness: true
+liveins:
+  - { reg: '%edi' }
+# CHECK-LABEL: name: foo
+# CHECK: body: |
+# CHECK-NEXT: bb.0.entry:
+# CHECK-NEXT: successors: %bb.1.less, %bb.2.exit
+# CHECK-NEXT: liveins: %edi
+# CHECK:      CMP32ri8 %edi, 10, implicit-def %eflags
+# CHECK-NEXT: JG_1 %bb.2.exit, implicit killed %eflags
+
+# CHECK:      bb.1.less:
+# CHECK-NEXT: %eax = MOV32r0 implicit-def dead %eflags
+# CHECK-NEXT: RETQ killed %eax
+
+# CHECK:      bb.2.exit:
+# CHECK-NEXT: liveins: %edi
+# CHECK:      %eax = COPY killed %edi
+# CHECK-NEXT: RETQ killed %eax
+body: |
+  bb.0.entry:
+    successors: %bb.1.less, %bb.2.exit
+
+    liveins: %edi
+
+    CMP32ri8 %edi, 10, implicit-def %eflags
+
+    JG_1 %bb.2.exit, implicit killed %eflags
+
+  bb.1.less:
+
+
+    %eax = MOV32r0 implicit-def dead %eflags
+    RETQ killed %eax
+  bb.2.exit:
+
+
+    liveins: %edi
+    %eax = COPY killed %edi
+    RETQ killed %eax
+
+...
+---
+name:            bar
+tracksRegLiveness: true
+liveins:
+  - { reg: '%edi' }
+# CHECK-LABEL: name: bar
+# CHECK: body: |
+# CHECK-NEXT: bb.0.entry:
+# CHECK-NEXT: successors: %bb.1.less, %bb.2.exit
+# CHECK-NEXT: liveins: %edi
+# CHECK:      CMP32ri8 %edi, 10, implicit-def %eflags
+# CHECK-NEXT: JG_1 %bb.2.exit, implicit killed %eflags
+
+# CHECK:      bb.1.less:
+# CHECK-NEXT: %eax = MOV32r0 implicit-def dead %eflags
+# CHECK-NEXT: RETQ killed %eax
+
+# CHECK:      bb.2.exit:
+# CHECK-NEXT: liveins: %edi
+# CHECK:      %eax = COPY killed %edi
+# CHECK-NEXT: RETQ killed %eax
+body: |
+
+  bb.0.entry:
+    successors: %bb.1.less, %bb.2.exit
+    liveins: %edi
+    CMP32ri8 %edi, 10, implicit-def %eflags
+    JG_1 %bb.2.exit, implicit killed %eflags
+  bb.1.less:  %eax = MOV32r0 implicit-def dead %eflags
+              RETQ killed %eax
+
+  bb.2.exit:  liveins: %edi
+    %eax = COPY killed %edi
+    RETQ killed %eax
+
+...
diff --git a/test/CodeGen/MIR/X86/null-register-operands.mir b/test/CodeGen/MIR/X86/null-register-operands.mir
index 55c0ceb3a60..5563ef8e8f7 100644
--- a/test/CodeGen/MIR/X86/null-register-operands.mir
+++ b/test/CodeGen/MIR/X86/null-register-operands.mir
@@ -13,12 +13,10 @@
 ---
 # CHECK: name: deref
 name:            deref
-body:
- - id:           0
-   name:         entry
-   instructions:
-     # CHECK:      - '%eax = MOV32rm %rdi, 1, _, 0, _'
-     # CHECK-NEXT: - 'RETQ %eax'
-     - '%eax = MOV32rm %rdi, 1, _, 0, %noreg'
-     - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    ; CHECK:      %eax = MOV32rm %rdi, 1, _, 0, _
+    ; CHECK-NEXT: RETQ %eax
+    %eax = MOV32rm %rdi, 1, _, 0, %noreg
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/register-mask-operands.mir b/test/CodeGen/MIR/X86/register-mask-operands.mir
index f4136598ff5..9fa4e6e3994 100644
--- a/test/CodeGen/MIR/X86/register-mask-operands.mir
+++ b/test/CodeGen/MIR/X86/register-mask-operands.mir
@@ -20,24 +20,20 @@
 ...
 ---
 name:            compute
-body:
-  - id:          0
-    name:        body
-    instructions:
-      - '%eax = IMUL32rri8 %edi, 11, implicit-def %eflags'
-      - 'RETQ %eax'
+body: |
+  bb.0.body:
+    %eax = IMUL32rri8 %edi, 11, implicit-def %eflags
+    RETQ %eax
 ...
 ---
 # CHECK: name: foo
 name:            foo
-body:
-  - id:          0
-    name:        entry
-    instructions:
-      # CHECK:      - 'PUSH64r %rax
-      # CHECK-NEXT: - 'CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax'
-      - 'PUSH64r %rax, implicit-def %rsp, implicit %rsp'
-      - 'CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax'
-      - '%rdx = POP64r implicit-def %rsp, implicit %rsp'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    ; CHECK:      PUSH64r %rax
+    ; CHECK-NEXT: CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax
+    PUSH64r %rax, implicit-def %rsp, implicit %rsp
+    CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax
+    %rdx = POP64r implicit-def %rsp, implicit %rsp
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/register-operands-target-flag-error.mir b/test/CodeGen/MIR/X86/register-operands-target-flag-error.mir
index 219a0d32ae9..64d46d20db7 100644
--- a/test/CodeGen/MIR/X86/register-operands-target-flag-error.mir
+++ b/test/CodeGen/MIR/X86/register-operands-target-flag-error.mir
@@ -14,13 +14,11 @@
 ...
 ---
 name: inc
-body:
-  - id: 0
-    name: entry
-    instructions:
-# CHECK: [[@LINE+1]]:47: register operands can't have target flags
-      - '%rax = MOV64rm target-flags(x86-got) %rip, 1, _, @G, _'
-      - '%eax = MOV32rm killed %rax, 1, _, 0, _'
-      - '%eax = INC32r killed %eax, implicit-def dead %eflags'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+  ; CHECK: [[@LINE+1]]:42: register operands can't have target flags
+    %rax = MOV64rm target-flags(x86-got) %rip, 1, _, @G, _
+    %eax = MOV32rm killed %rax, 1, _, 0, _
+    %eax = INC32r killed %eax, implicit-def dead %eflags
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir b/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir
index 42ed70ee372..d7e76329be7 100644
--- a/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir
+++ b/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir
@@ -22,14 +22,13 @@ registers:
   - { id: 0, class: gr32 }
   - { id: 1, class: gr32, preferred-register: '%esi' }
   - { id: 2, class: gr32, preferred-register: '%edi' }
-body:
-  - id:              0
-    name:            body
-    liveins:         [ '%edi', '%esi' ]
-    instructions:
-      - '%1 = COPY %esi'
-      - '%2 = COPY %edi'
-      - '%2 = IMUL32rr %2, %1, implicit-def dead %eflags'
-      - '%eax = COPY %2'
-      - 'RETQ killed %eax'
+body: |
+  bb.0.body:
+    liveins: %edi, %esi
+
+    %1 = COPY %esi
+    %2 = COPY %edi
+    %2 = IMUL32rr %2, %1, implicit-def dead %eflags
+    %eax = COPY %2
+    RETQ killed %eax
 ...
diff --git a/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-aliased.mir b/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-aliased.mir
index 67f4bd21cd0..b62cd755fec 100644
--- a/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-aliased.mir
+++ b/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-aliased.mir
@@ -22,11 +22,9 @@ fixedStack:
   - { id: 0, type: spill-slot, offset: 0, size: 4, isAliased: true }
 stack:
   - { id: 0, offset: -12, size: 4, alignment: 4 }
-body:
-  - id:          0
-    name:        entry
-    instructions:
-      - 'MOV32mr %rsp, 1, _, -4, _, %edi'
-      - '%eax = COPY %edi'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    MOV32mr %rsp, 1, _, -4, _, %edi
+    %eax = COPY %edi
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-immutable.mir b/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-immutable.mir
index 1e1b0fdcc8d..c89216bea67 100644
--- a/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-immutable.mir
+++ b/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-immutable.mir
@@ -22,11 +22,9 @@ fixedStack:
   - { id: 0, type: spill-slot, offset: 0, size: 4, isImmutable: true }
 stack:
   - { id: 0, offset: -12, size: 4, alignment: 4 }
-body:
-  - id:          0
-    name:        entry
-    instructions:
-      - 'MOV32mr %rsp, 1, _, -4, _, %edi'
-      - '%eax = COPY %edi'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    MOV32mr %rsp, 1, _, -4, _, %edi
+    %eax = COPY %edi
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir b/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir
index f771f796ec3..7e13a26f0b6 100644
--- a/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir
+++ b/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir
@@ -24,11 +24,9 @@ fixedStack:
   - { id: 0, type: spill-slot, offset: 0, size: 4, alignment: 4 }
 stack:
   - { id: 0, offset: -12, size: 4, alignment: 4 }
-body:
-  - id:          0
-    name:        entry
-    instructions:
-      - 'MOV32mr %rsp, 1, _, -4, _, %edi'
-      - '%eax = COPY %edi'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    MOV32mr %rsp, 1, _, -4, _, %edi
+    %eax = COPY %edi
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/stack-object-invalid-name.mir b/test/CodeGen/MIR/X86/stack-object-invalid-name.mir
index 2d4f57bad3d..e42e1e59f1e 100644
--- a/test/CodeGen/MIR/X86/stack-object-invalid-name.mir
+++ b/test/CodeGen/MIR/X86/stack-object-invalid-name.mir
@@ -20,11 +20,9 @@ frameInfo:
 stack:
   # CHECK: [[@LINE+1]]:20: alloca instruction named 'x' isn't defined in the function 'test'
   - { id: 0, name: x, offset: -12, size: 4, alignment: 4 }
-body:
-  - id:          0
-    name:        entry
-    instructions:
-      - 'MOV32mr %rsp, 1, _, -4, _, %edi'
-      - '%eax = MOV32rm %rsp, 1, _, -4, _'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    MOV32mr %rsp, 1, _, -4, _, %edi
+    %eax = MOV32rm %rsp, 1, _, -4, _
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir b/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir
index a6ffb3b93e0..46661d95e72 100644
--- a/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir
+++ b/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir
@@ -23,13 +23,11 @@ frameInfo:
   maxAlignment:  4
 stack:
   - { id: 0, name: b, size: 4, alignment: 4 }
-body:
-  - id:          0
-    name:        entry
-    instructions:
-      - '%0 = COPY %edi'
-      # CHECK: [[@LINE+1]]:18: the name of the stack object '%stack.0' isn't 'x'
-      - 'MOV32mr %stack.0.x, 1, _, 0, _, %0'
-      - '%eax = COPY %0'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    %0 = COPY %edi
+    ; CHECK: [[@LINE+1]]:13: the name of the stack object '%stack.0' isn't 'x'
+    MOV32mr %stack.0.x, 1, _, 0, _, %0
+    %eax = COPY %0
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/stack-object-operands.mir b/test/CodeGen/MIR/X86/stack-object-operands.mir
index b1c078eb6a3..fce5bf717d1 100644
--- a/test/CodeGen/MIR/X86/stack-object-operands.mir
+++ b/test/CodeGen/MIR/X86/stack-object-operands.mir
@@ -29,20 +29,17 @@ fixedStack:
 stack:
   - { id: 0, name: b, size: 4, alignment: 4 }
   - { id: 1, size: 4, alignment: 4 }
-body:
-  # CHECK: name: entry
-  # CHECK: instructions:
-  # CHECK-NEXT: - '%0 = MOV32rm %fixed-stack.0, 1, _, 0, _'
-  # CHECK-NEXT: - 'MOV32mr %stack.0.b, 1, _, 0, _, %0'
-  # CHECK-NEXT: - 'MOV32mi %stack.1, 1, _, 0, _, 2'
-  # CHECK-NEXT: - '%1 = MOV32rm %stack.0.b, 1, _, 0, _'
-  - id:          0
-    name:        entry
-    instructions:
-      - '%0 = MOV32rm %fixed-stack.0, 1, _, 0, _'
-      - 'MOV32mr %stack.0.b, 1, _, 0, _, %0'
-      - 'MOV32mi %stack.1, 1, _, 0, _, 2'
-      - '%1 = MOV32rm %stack.0, 1, _, 0, _'
-      - '%eax = COPY %1'
-      - 'RETL %eax'
+body: |
+  ; CHECK: bb.0.entry:
+  ; CHECK-NEXT: %0 = MOV32rm %fixed-stack.0, 1, _, 0, _
+  ; CHECK-NEXT: MOV32mr %stack.0.b, 1, _, 0, _, %0
+  ; CHECK-NEXT: MOV32mi %stack.1, 1, _, 0, _, 2
+  ; CHECK-NEXT: %1 = MOV32rm %stack.0.b, 1, _, 0, _
+  bb.0.entry:
+    %0 = MOV32rm %fixed-stack.0, 1, _, 0, _
+    MOV32mr %stack.0.b, 1, _, 0, _, %0
+    MOV32mi %stack.1, 1, _, 0, _, 2
+    %1 = MOV32rm %stack.0, 1, _, 0, _
+    %eax = COPY %1
+    RETL %eax
 ...
diff --git a/test/CodeGen/MIR/X86/stack-object-redefinition-error.mir b/test/CodeGen/MIR/X86/stack-object-redefinition-error.mir
index b5b8dafdd0a..b84863ebca6 100644
--- a/test/CodeGen/MIR/X86/stack-object-redefinition-error.mir
+++ b/test/CodeGen/MIR/X86/stack-object-redefinition-error.mir
@@ -26,13 +26,12 @@ stack:
   - { id: 0, name: b, offset: -12, size: 4, alignment: 4 }
 # CHECK: [[@LINE+1]]:11: redefinition of stack object '%stack.0'
   - { id: 0, name: x, offset: -24, size: 8, alignment: 8 }
-body:
-  - id:              0
-    name:            entry
-    liveins:         [ '%edi' ]
-    instructions:
-      - 'MOV32mr %rsp, 1, _, -4, _, killed %edi'
-      - 'MOV64mi32 %rsp, 1, _, -16, _, 2'
-      - '%eax = MOV32rm %rsp, 1, _, -4, _'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    liveins: %edi
+
+    MOV32mr %rsp, 1, _, -4, _, killed %edi
+    MOV64mi32 %rsp, 1, _, -16, _, 2
+    %eax = MOV32rm %rsp, 1, _, -4, _
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/stack-objects.mir b/test/CodeGen/MIR/X86/stack-objects.mir
index 37666300a91..bdd911075da 100644
--- a/test/CodeGen/MIR/X86/stack-objects.mir
+++ b/test/CodeGen/MIR/X86/stack-objects.mir
@@ -28,12 +28,10 @@ stack:
   - { id: 0, name: b, offset: -12, size: 4, alignment: 4 }
   - { id: 1, name: x, offset: -24, size: 8, alignment: 8 }
   - { id: 2, type: spill-slot, offset: -32, size: 4, alignment: 4 }
-body:
-  - id:          0
-    name:        entry
-    instructions:
-      - 'MOV32mr %rsp, 1, _, -4, _, %edi'
-      - 'MOV64mi32 %rsp, 1, _, -16, _, 2'
-      - '%eax = MOV32rm %rsp, 1, _, -4, _'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    MOV32mr %rsp, 1, _, -4, _, %edi
+    MOV64mi32 %rsp, 1, _, -16, _, 2
+    %eax = MOV32rm %rsp, 1, _, -4, _
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/subregister-operands.mir b/test/CodeGen/MIR/X86/subregister-operands.mir
index bbdf3fb4a67..8a3fcf69aca 100644
--- a/test/CodeGen/MIR/X86/subregister-operands.mir
+++ b/test/CodeGen/MIR/X86/subregister-operands.mir
@@ -18,17 +18,15 @@ registers:
   - { id: 0, class: gr32 }
   - { id: 1, class: gr8 }
   - { id: 2, class: gr8 }
-body:
-  - name:        entry
-    id:          0
-    liveins:     [ '%edi' ]
-    instructions:
-      # CHECK:      %0 = COPY %edi
-      # CHECK-NEXT: %1 = COPY %0:sub_8bit
-      - '%0 = COPY %edi'
-      - '%1 = COPY %0:sub_8bit'
-      - '%2 = AND8ri %1, 1, implicit-def %eflags'
-      - '%al = COPY %2'
-      - 'RETQ %al'
+body: |
+  bb.0.entry:
+    liveins: %edi
+    ; CHECK:      %0 = COPY %edi
+    ; CHECK-NEXT: %1 = COPY %0:sub_8bit
+    %0 = COPY %edi
+    %1 = COPY %0:sub_8bit
+    %2 = AND8ri %1, 1, implicit-def %eflags
+    %al = COPY %2
+    RETQ %al
 ...
 
diff --git a/test/CodeGen/MIR/X86/successor-basic-blocks-few-weights.mir b/test/CodeGen/MIR/X86/successor-basic-blocks-few-weights.mir
deleted file mode 100644
index 93d2eead0bb..00000000000
--- a/test/CodeGen/MIR/X86/successor-basic-blocks-few-weights.mir
+++ /dev/null
@@ -1,41 +0,0 @@
-# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s
-
---- |
-
-  define i32 @foo(i32 %a) {
-  entry:
-    %0 = icmp sle i32 %a, 10
-    br i1 %0, label %less, label %exit
-
-  less:
-    ret i32 0
-
-  exit:
-    ret i32 %a
-  }
-
-...
----
-name:            foo
-body:
-  - id:          0
-    name:        entry
-    successors:  [ '%bb.1.less', '%bb.2.exit' ]
-# CHECK: [[@LINE+1]]:23: too few successor weights, expected 2, have 1
-    weights:     [ 16 ]
-    liveins:     [ '%edi' ]
-    instructions:
-      - 'CMP32ri8 %edi, 10, implicit-def %eflags'
-      - 'JG_1 %bb.2.exit, implicit killed %eflags'
-  - id:          1
-    name:        less
-    instructions:
-      - '%eax = MOV32r0 implicit-def dead %eflags'
-      - 'RETQ killed %eax'
-  - id:          2
-    name:        exit
-    liveins:     [ '%edi' ]
-    instructions:
-      - '%eax = COPY killed %edi'
-      - 'RETQ killed %eax'
-...
diff --git a/test/CodeGen/MIR/X86/successor-basic-blocks-many-weights.mir b/test/CodeGen/MIR/X86/successor-basic-blocks-many-weights.mir
deleted file mode 100644
index 2c0e1932aad..00000000000
--- a/test/CodeGen/MIR/X86/successor-basic-blocks-many-weights.mir
+++ /dev/null
@@ -1,41 +0,0 @@
-# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s
-
---- |
-
-  define i32 @foo(i32 %a) {
-  entry:
-    %0 = icmp sle i32 %a, 10
-    br i1 %0, label %less, label %exit
-
-  less:
-    ret i32 0
-
-  exit:
-    ret i32 %a
-  }
-
-...
----
-name:            foo
-body:
-  - id:          0
-    name:        entry
-    successors:  [ '%bb.1.less', '%bb.2.exit' ]
-# CHECK: [[@LINE+1]]:28: too many successor weights, expected 2, have 3
-    weights:     [ 16, 16, 16 ]
-    liveins:     [ '%edi' ]
-    instructions:
-      - 'CMP32ri8 %edi, 10, implicit-def %eflags'
-      - 'JG_1 %bb.2.exit, implicit killed %eflags'
-  - id:          1
-    name:        less
-    instructions:
-      - '%eax = MOV32r0 implicit-def dead %eflags'
-      - 'RETQ killed %eax'
-  - id:          2
-    name:        exit
-    liveins:     [ '%edi' ]
-    instructions:
-      - '%eax = COPY killed %edi'
-      - 'RETQ killed %eax'
-...
diff --git a/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir b/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir
index c7cfeaae90d..fc5e5d640f7 100644
--- a/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir
+++ b/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir
@@ -19,28 +19,24 @@
 ...
 ---
 name:            foo
-body:
-  # CHECK:      name: entry
-  # CHECK:      successors: [ '%bb.1.less', '%bb.2.exit' ]
-  # CHECK-NEXT: weights: [ 16, 32 ]
-  # CHECK:      name: less
-  - id:          0
-    name:        entry
-    successors:  [ '%bb.1.less', '%bb.2.exit' ]
-    weights:     [ 16, 32 ]
-    liveins:     [ '%edi' ]
-    instructions:
-      - 'CMP32ri8 %edi, 10, implicit-def %eflags'
-      - 'JG_1 %bb.2.exit, implicit killed %eflags'
-  - id:          1
-    name:        less
-    instructions:
-      - '%eax = MOV32r0 implicit-def dead %eflags'
-      - 'RETQ killed %eax'
-  - id:          2
-    name:        exit
-    liveins:     [ '%edi' ]
-    instructions:
-      - '%eax = COPY killed %edi'
-      - 'RETQ killed %eax'
+body: |
+  ; CHECK-LABEL: bb.0.entry:
+  ; CHECK:         successors: %bb.1.less(16), %bb.2.exit(32)
+  ; CHECK-LABEL: bb.1.less:
+  bb.0.entry:
+    successors: %bb.1.less (16), %bb.2.exit(32)
+    liveins: %edi
+
+    CMP32ri8 %edi, 10, implicit-def %eflags
+    JG_1 %bb.2.exit, implicit killed %eflags
+
+  bb.1.less:
+    %eax = MOV32r0 implicit-def dead %eflags
+    RETQ killed %eax
+
+  bb.2.exit:
+    liveins: %edi
+
+    %eax = COPY killed %edi
+    RETQ killed %eax
 ...
diff --git a/test/CodeGen/MIR/X86/successor-basic-blocks.mir b/test/CodeGen/MIR/X86/successor-basic-blocks.mir
index de4f84eb210..2323a39e85f 100644
--- a/test/CodeGen/MIR/X86/successor-basic-blocks.mir
+++ b/test/CodeGen/MIR/X86/successor-basic-blocks.mir
@@ -30,51 +30,54 @@
 ...
 ---
 name:            foo
-body:
-  # CHECK: name: entry
-  # CHECK: successors: [ '%bb.1.less', '%bb.2.exit' ]
-  # CHECK: name: less
-  - id:          0
-    name:        entry
-    successors:  [ '%bb.1.less', '%bb.2.exit' ]
-    liveins:     [ '%edi' ]
-    instructions:
-      - 'CMP32ri8 %edi, 10, implicit-def %eflags'
-      - 'JG_1 %bb.2.exit, implicit killed %eflags'
-  - id:          1
-    name:        less
-    instructions:
-      - '%eax = MOV32r0 implicit-def dead %eflags'
-      - 'RETQ killed %eax'
-  - id:          2
-    name:        exit
-    liveins:     [ '%edi' ]
-    instructions:
-      - '%eax = COPY killed %edi'
-      - 'RETQ killed %eax'
+body: |
+  ; CHECK-LABEL: bb.0.entry:
+  ; CHECK:         successors: %bb.1.less, %bb.2.exit
+  ; CHECK-LABEL: bb.1.less:
+  bb.0.entry:
+    successors: %bb.1.less, %bb.2.exit
+    liveins: %edi
+
+    CMP32ri8 %edi, 10, implicit-def %eflags
+    JG_1 %bb.2.exit, implicit killed %eflags
+
+  bb.1.less:
+    %eax = MOV32r0 implicit-def dead %eflags
+    RETQ killed %eax
+
+  bb.2.exit:
+    liveins: %edi
+
+    %eax = COPY killed %edi
+    RETQ killed %eax
 ...
 ---
 name:            bar
-body:
-  # CHECK: name: bar
-  # CHECK: name: entry
-  # CHECK: successors: [ '%bb.1', '%bb.2' ]
-  # CHECK: id: 1
-  # CHECK: id: 2
-  - id:           0
-    name:         entry
-    successors:   [ '%bb.1', '%bb.2' ]
-    liveins:      [ '%edi' ]
-    instructions:
-      - 'CMP32ri8 %edi, 10, implicit-def %eflags'
-      - 'JG_1 %bb.2, implicit killed %eflags'
-  - id:           1
-    instructions:
-      - '%eax = MOV32r0 implicit-def dead %eflags'
-      - 'RETQ killed %eax'
-  - id:           2
-    liveins:      [ '%edi' ]
-    instructions:
-      - '%eax = COPY killed %edi'
-      - 'RETQ killed %eax'
+body: |
+  ; CHECK-LABEL: name: bar
+  ; Verify that we can have multiple lists of successors that will be merged
+  ; into one.
+  ; CHECK-LABEL: bb.0.entry:
+  ; CHECK:         successors: %bb.1, %bb.2
+  bb.0.entry:
+    liveins: %edi
+    successors: %bb.1
+    successors: %bb.2
+
+    CMP32ri8 %edi, 10, implicit-def %eflags
+    JG_1 %bb.2, implicit killed %eflags
+
+  ; Verify that we can have an empty list of successors.
+  ; CHECK-LABEL: bb.1:
+  ; CHECK-NEXT:  %eax = MOV32r0 implicit-def dead %eflags
+  bb.1:
+    successors:
+    %eax = MOV32r0 implicit-def dead %eflags
+    RETQ killed %eax
+
+  bb.2:
+    liveins: %edi
+
+    %eax = COPY killed %edi
+    RETQ killed %eax
 ...
diff --git a/test/CodeGen/MIR/X86/undef-register-flag.mir b/test/CodeGen/MIR/X86/undef-register-flag.mir
index 83b9e10a80d..0b26c528aee 100644
--- a/test/CodeGen/MIR/X86/undef-register-flag.mir
+++ b/test/CodeGen/MIR/X86/undef-register-flag.mir
@@ -21,22 +21,18 @@
 ...
 ---
 name:            compute
-body:
-  - id:          0
-    name:        body
-    instructions:
-      - '%eax = IMUL32rri8 %edi, 11, implicit-def %eflags'
-      - 'RETQ %eax'
+body: |
+  bb.0.body:
+    %eax = IMUL32rri8 %edi, 11, implicit-def %eflags
+    RETQ %eax
 ...
 ---
 name:            foo
-body:
-  - id:          0
-    name:        entry
-    instructions:
-      # CHECK: - 'PUSH64r undef %rax
-      - 'PUSH64r undef %rax, implicit-def %rsp, implicit %rsp'
-      - 'CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax'
-      - '%rdx = POP64r implicit-def %rsp, implicit %rsp'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    ; CHECK: PUSH64r undef %rax
+    PUSH64r undef %rax, implicit-def %rsp, implicit %rsp
+    CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax
+    %rdx = POP64r implicit-def %rsp, implicit %rsp
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir b/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir
index 4a2fc80d52a..8d8f8614f32 100644
--- a/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir
+++ b/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir
@@ -26,15 +26,13 @@ fixedStack:
 stack:
   - { id: 0, name: b, size: 4, alignment: 4 }
   - { id: 1, size: 4, alignment: 4 }
-body:
-  - id:          0
-    name:        entry
-    instructions:
-      # CHECK: [[@LINE+1]]:23: use of undefined fixed stack object '%fixed-stack.11'
-      - '%0 = MOV32rm %fixed-stack.11, 1, _, 0, _'
-      - 'MOV32mr %stack.0, 1, _, 0, _, %0'
-      - 'MOV32mi %stack.1, 1, _, 0, _, 2'
-      - '%1 = MOV32rm %stack.0, 1, _, 0, _'
-      - '%eax = COPY %1'
-      - 'RETL %eax'
+body: |
+  bb.0.entry:
+    ; CHECK: [[@LINE+1]]:18: use of undefined fixed stack object '%fixed-stack.11'
+    %0 = MOV32rm %fixed-stack.11, 1, _, 0, _
+    MOV32mr %stack.0, 1, _, 0, _, %0
+    MOV32mi %stack.1, 1, _, 0, _, 2
+    %1 = MOV32rm %stack.0, 1, _, 0, _
+    %eax = COPY %1
+    RETL %eax
 ...
diff --git a/test/CodeGen/MIR/X86/undefined-global-value.mir b/test/CodeGen/MIR/X86/undefined-global-value.mir
index e41dc0454d2..f82c626397a 100644
--- a/test/CodeGen/MIR/X86/undefined-global-value.mir
+++ b/test/CodeGen/MIR/X86/undefined-global-value.mir
@@ -16,13 +16,11 @@
 ...
 ---
 name: inc
-body:
-  - id: 0
-    name: entry
-    instructions:
-      # CHECK: [[@LINE+1]]:37: use of undefined global value '@2'
-      - '%rax = MOV64rm %rip, 1, _, @2, _'
-      - '%eax = MOV32rm %rax, 1, _, 0, _'
-      - '%eax = INC32r %eax'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    ; CHECK: [[@LINE+1]]:32: use of undefined global value '@2'
+    %rax = MOV64rm %rip, 1, _, @2, _
+    %eax = MOV32rm %rax, 1, _, 0, _
+    %eax = INC32r %eax
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/undefined-ir-block-in-blockaddress.mir b/test/CodeGen/MIR/X86/undefined-ir-block-in-blockaddress.mir
index fc43df37303..f6b10e3123c 100644
--- a/test/CodeGen/MIR/X86/undefined-ir-block-in-blockaddress.mir
+++ b/test/CodeGen/MIR/X86/undefined-ir-block-in-blockaddress.mir
@@ -17,18 +17,14 @@
 ...
 ---
 name:            test
-body:
-  - id:              0
-    name:            entry
-    successors:      [ '%bb.1.block' ]
-    instructions:
-      # CHECK: [[@LINE+1]]:56: use of undefined IR block '%ir-block."block "'
-      - '%rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block."block "), _'
-      - 'MOV64mr %rip, 1, _, @addr, _, killed %rax'
-      - 'JMP64m %rip, 1, _, @addr, _'
-  - id:              1
-    name:            block
-    addressTaken:    true
-    instructions:
-      - RETQ
+body: |
+  bb.0.entry:
+    successors: %bb.1.block
+    ; CHECK: [[@LINE+1]]:51: use of undefined IR block '%ir-block."block "'
+    %rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block."block "), _
+    MOV64mr %rip, 1, _, @addr, _, killed %rax
+    JMP64m %rip, 1, _, @addr, _
+
+  bb.1.block (address-taken):
+    RETQ
 ...
diff --git a/test/CodeGen/MIR/X86/undefined-ir-block-slot-in-blockaddress.mir b/test/CodeGen/MIR/X86/undefined-ir-block-slot-in-blockaddress.mir
index 189b0f15ccc..0b3c0093dc6 100644
--- a/test/CodeGen/MIR/X86/undefined-ir-block-slot-in-blockaddress.mir
+++ b/test/CodeGen/MIR/X86/undefined-ir-block-slot-in-blockaddress.mir
@@ -16,17 +16,14 @@
 ...
 ---
 name:            test
-body:
-  - id:              0
-    name:            entry
-    successors:      [ '%bb.1' ]
-    instructions:
-      # CHECK: [[@LINE+1]]:56: use of undefined IR block '%ir-block.1'
-      - '%rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.1), _'
-      - 'MOV64mr %rip, 1, _, @addr, _, killed %rax'
-      - 'JMP64m %rip, 1, _, @addr, _'
-  - id:              1
-    addressTaken:    true
-    instructions:
-      - RETQ
+body: |
+  bb.0.entry:
+    successors: %bb.1
+    ; CHECK: [[@LINE+1]]:51: use of undefined IR block '%ir-block.1'
+    %rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.1), _
+    MOV64mr %rip, 1, _, @addr, _, killed %rax
+    JMP64m %rip, 1, _, @addr, _
+
+  bb.1 (address-taken):
+    RETQ
 ...
diff --git a/test/CodeGen/MIR/X86/undefined-jump-table-id.mir b/test/CodeGen/MIR/X86/undefined-jump-table-id.mir
index f4bc41cd8f7..b463dc4bd9f 100644
--- a/test/CodeGen/MIR/X86/undefined-jump-table-id.mir
+++ b/test/CodeGen/MIR/X86/undefined-jump-table-id.mir
@@ -35,46 +35,39 @@ jumpTable:
   entries:
     - id:        0
       blocks:    [ '%bb.3.lbl1', '%bb.4.lbl2', '%bb.5.lbl3', '%bb.6.lbl4' ]
-body:
-  - id:              0
-    name:            entry
-    successors:      [ '%bb.2.def', '%bb.1.entry' ]
-    instructions:
-      - '%eax = MOV32rr %edi, implicit-def %rax'
-      - 'CMP32ri8 %edi, 3, implicit-def %eflags'
-      - 'JA_1 %bb.2.def, implicit %eflags'
-  - id:              1
-    name:            entry
-    successors:      [ '%bb.3.lbl1', '%bb.4.lbl2', '%bb.5.lbl3', '%bb.6.lbl4' ]
-    instructions:
-    # CHECK: [[@LINE+1]]:36: use of undefined jump table '%jump-table.2'
-      - '%rcx = LEA64r %rip, 1, _, %jump-table.2, _'
-      - '%rax = MOVSX64rm32 %rcx, 4, %rax, 0, _'
-      - '%rax = ADD64rr %rax, %rcx, implicit-def %eflags'
-      - 'JMP64r %rax'
-  - id:              2
-    name:            def
-    instructions:
-      - '%eax = MOV32r0 implicit-def %eflags'
-      - 'RETQ %eax'
-  - id:              3
-    name:            lbl1
-    instructions:
-      - '%eax = MOV32ri 1'
-      - 'RETQ %eax'
-  - id:              4
-    name:            lbl2
-    instructions:
-      - '%eax = MOV32ri 2'
-      - 'RETQ %eax'
-  - id:              5
-    name:            lbl3
-    instructions:
-      - '%eax = MOV32ri 4'
-      - 'RETQ %eax'
-  - id:              6
-    name:            lbl4
-    instructions:
-      - '%eax = MOV32ri 8'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    successors: %bb.2.def, %bb.1.entry
+
+    %eax = MOV32rr %edi, implicit-def %rax
+    CMP32ri8 %edi, 3, implicit-def %eflags
+    JA_1 %bb.2.def, implicit %eflags
+
+  bb.1.entry:
+    successors: %bb.3.lbl1, %bb.4.lbl2, %bb.5.lbl3, %bb.6.lbl4
+    ; CHECK: [[@LINE+1]]:31: use of undefined jump table '%jump-table.2'
+    %rcx = LEA64r %rip, 1, _, %jump-table.2, _
+    %rax = MOVSX64rm32 %rcx, 4, %rax, 0, _
+    %rax = ADD64rr %rax, %rcx, implicit-def %eflags
+    JMP64r %rax
+
+  bb.2.def:
+    %eax = MOV32r0 implicit-def %eflags
+    RETQ %eax
+
+  bb.3.lbl1:
+    %eax = MOV32ri 1
+    RETQ %eax
+
+  bb.4.lbl2:
+    %eax = MOV32ri 2
+    RETQ %eax
+
+  bb.5.lbl3:
+    %eax = MOV32ri 4
+    RETQ %eax
+
+  bb.6.lbl4:
+    %eax = MOV32ri 8
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/undefined-named-global-value.mir b/test/CodeGen/MIR/X86/undefined-named-global-value.mir
index b40c2ce43b5..a1ada4b42e4 100644
--- a/test/CodeGen/MIR/X86/undefined-named-global-value.mir
+++ b/test/CodeGen/MIR/X86/undefined-named-global-value.mir
@@ -16,13 +16,11 @@
 ...
 ---
 name: inc
-body:
-  - id: 0
-    name: entry
-    instructions:
-      # CHECK: [[@LINE+1]]:37: use of undefined global value '@GG'
-      - '%rax = MOV64rm %rip, 1, _, @GG, _'
-      - '%eax = MOV32rm %rax, 1, _, 0, _'
-      - '%eax = INC32r %eax'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    ; CHECK: [[@LINE+1]]:32: use of undefined global value '@GG'
+    %rax = MOV64rm %rip, 1, _, @GG, _
+    %eax = MOV32rm %rax, 1, _, 0, _
+    %eax = INC32r %eax
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/undefined-register-class.mir b/test/CodeGen/MIR/X86/undefined-register-class.mir
index a14d2303a7d..348f6af5c44 100644
--- a/test/CodeGen/MIR/X86/undefined-register-class.mir
+++ b/test/CodeGen/MIR/X86/undefined-register-class.mir
@@ -17,10 +17,8 @@ tracksRegLiveness: true
 registers:
   # CHECK: [[@LINE+1]]:20: use of undefined register class 'gr3200'
   - {id: 0, class: 'gr3200'}
-body:
-  - id:          0
-    name:        entry
-    instructions:
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    RETQ %eax
 ...
 
diff --git a/test/CodeGen/MIR/X86/undefined-stack-object.mir b/test/CodeGen/MIR/X86/undefined-stack-object.mir
index bec703a2d11..416e6789ba0 100644
--- a/test/CodeGen/MIR/X86/undefined-stack-object.mir
+++ b/test/CodeGen/MIR/X86/undefined-stack-object.mir
@@ -20,13 +20,11 @@ frameInfo:
   maxAlignment:  4
 stack:
   - { id: 0, name: b, size: 4, alignment: 4 }
-body:
-  - id:          0
-    name:        entry
-    instructions:
-      - '%0 = COPY %edi'
-      # CHECK: [[@LINE+1]]:18: use of undefined stack object '%stack.2'
-      - 'MOV32mr %stack.2, 1, _, 0, _, %0'
-      - '%eax = COPY %0'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    %0 = COPY %edi
+    ; CHECK: [[@LINE+1]]:13: use of undefined stack object '%stack.2'
+    MOV32mr %stack.2, 1, _, 0, _, %0
+    %eax = COPY %0
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/undefined-value-in-memory-operand.mir b/test/CodeGen/MIR/X86/undefined-value-in-memory-operand.mir
index a41b8ee3def..a3907d7a3a4 100644
--- a/test/CodeGen/MIR/X86/undefined-value-in-memory-operand.mir
+++ b/test/CodeGen/MIR/X86/undefined-value-in-memory-operand.mir
@@ -14,13 +14,11 @@ name:            test
 tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
-body:
-  - id:          0
-    name:        entry
-    liveins:     [ '%rdi' ]
-    instructions:
-# CHECK: [[@LINE+1]]:65: use of undefined IR value '%ir.c'
-      - '%eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 from %ir.c)'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    liveins: %rdi
+  ; CHECK: [[@LINE+1]]:60: use of undefined IR value '%ir.c'
+    %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 from %ir.c)
+    RETQ %eax
 ...
 
diff --git a/test/CodeGen/MIR/X86/undefined-virtual-register.mir b/test/CodeGen/MIR/X86/undefined-virtual-register.mir
index 12370c80caf..2f9a304ffe5 100644
--- a/test/CodeGen/MIR/X86/undefined-virtual-register.mir
+++ b/test/CodeGen/MIR/X86/undefined-virtual-register.mir
@@ -16,13 +16,11 @@ isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
-body:
-  - id:          0
-    name:        entry
-    instructions:
-      - '%0 = COPY %edi'
-      # CHECK: [[@LINE+1]]:22: use of undefined virtual register '%10'
-      - '%eax = COPY %10'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    %0 = COPY %edi
+    ; CHECK: [[@LINE+1]]:17: use of undefined virtual register '%10'
+    %eax = COPY %10
+    RETQ %eax
 ...
 
diff --git a/test/CodeGen/MIR/X86/unknown-instruction.mir b/test/CodeGen/MIR/X86/unknown-instruction.mir
index 4e58ca6bad4..cec35494883 100644
--- a/test/CodeGen/MIR/X86/unknown-instruction.mir
+++ b/test/CodeGen/MIR/X86/unknown-instruction.mir
@@ -12,10 +12,8 @@
 ...
 ---
 name:            foo
-body:
- - id:           0
-   name:         entry
-   instructions:
-     # CHECK: [[@LINE+1]]:8: unknown machine instruction name 'retJust0'
-     - retJust0
+body: |
+  bb.0.entry:
+    ; CHECK: [[@LINE+1]]:5: unknown machine instruction name 'retJust0'
+    retJust0
 ...
diff --git a/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir b/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir
index a82e9a780f5..a512d9aa08e 100644
--- a/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir
+++ b/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir
@@ -21,18 +21,16 @@
 ...
 ---
 name:            foo
-body:
- - id: 0
-   name:         entry
-   instructions:
-     - '%eax = MOV32rm %rdi, 1, _, 0, _'
-     - 'CMP32ri8 %eax, 10, implicit-def %eflags'
-     # CHECK: [[@LINE+1]]:14: use of undefined machine basic block #4
-     - 'JG_1 %bb.4, implicit %eflags'
- - id: 1
-   instructions:
-     - '%eax = MOV32r0 implicit-def %eflags'
- - id: 2
-   instructions:
-     - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    %eax = MOV32rm %rdi, 1, _, 0, _
+    CMP32ri8 %eax, 10, implicit-def %eflags
+    ; CHECK: [[@LINE+1]]:10: use of undefined machine basic block #4
+    JG_1 %bb.4, implicit %eflags
+
+  bb.1:
+    %eax = MOV32r0 implicit-def %eflags
+
+  bb.2:
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/unknown-metadata-node.mir b/test/CodeGen/MIR/X86/unknown-metadata-node.mir
index 7afaf6036a1..b38b6c4b80d 100644
--- a/test/CodeGen/MIR/X86/unknown-metadata-node.mir
+++ b/test/CodeGen/MIR/X86/unknown-metadata-node.mir
@@ -48,14 +48,12 @@ frameInfo:
   maxAlignment:  4
 stack:
   - { id: 0, name: x.addr, size: 4, alignment: 4 }
-body:
-  - id:          0
-    name:        entry
-    instructions:
-      - '%0 = COPY %edi'
-      # CHECK: [[@LINE+1]]:26: use of undefined metadata '!42'
-      - 'DBG_VALUE _, 0, !42, !13'
-      - 'MOV32mr %stack.0.x.addr, 1, _, 0, _, %0'
-      - '%eax = COPY %0'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    %0 = COPY %edi
+    ; CHECK: [[@LINE+1]]:21: use of undefined metadata '!42'
+    DBG_VALUE _, 0, !42, !13
+    MOV32mr %stack.0.x.addr, 1, _, 0, _, %0
+    %eax = COPY %0
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir b/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir
index f304113f40b..6627273d447 100644
--- a/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir
+++ b/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir
@@ -20,20 +20,16 @@
 ...
 ---
 name:            foo
-body:
- - id:              0
-   name:            entry
-   instructions:
-     - '%eax = MOV32rm %rdi, 1, _, 0, _'
-     - 'CMP32ri8 %eax, 10, implicit-def %eflags'
-     # CHECK: [[@LINE+1]]:14: the name of machine basic block #2 isn't 'hit'
-     - 'JG_1 %bb.2.hit, implicit %eflags'
- - id:              1
-   name:            less
-   instructions:
-     - '%eax = MOV32r0 implicit-def %eflags'
- - id:              2
-   name:            exit
-   instructions:
-     - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    %eax = MOV32rm %rdi, 1, _, 0, _
+    CMP32ri8 %eax, 10, implicit-def %eflags
+    ; CHECK: [[@LINE+1]]:10: the name of machine basic block #2 isn't 'hit'
+    JG_1 %bb.2.hit, implicit %eflags
+
+  bb.1.less:
+    %eax = MOV32r0 implicit-def %eflags
+
+  bb.2.exit:
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/unknown-register.mir b/test/CodeGen/MIR/X86/unknown-register.mir
index ce40ee809bf..da0798ca1b5 100644
--- a/test/CodeGen/MIR/X86/unknown-register.mir
+++ b/test/CodeGen/MIR/X86/unknown-register.mir
@@ -12,11 +12,9 @@
 ...
 ---
 name:            foo
-body:
- - id:           0
-   name:         entry
-   instructions:
-     # CHECK: [[@LINE+1]]:9: unknown register name 'xax'
-     - '%xax = MOV32r0'
-     - 'RETQ %xax'
+body: |
+  bb.0.entry:
+    ; CHECK: [[@LINE+1]]:5: unknown register name 'xax'
+    %xax = MOV32r0
+    RETQ %xax
 ...
diff --git a/test/CodeGen/MIR/X86/unknown-subregister-index.mir b/test/CodeGen/MIR/X86/unknown-subregister-index.mir
index 50461232b62..5dde3456123 100644
--- a/test/CodeGen/MIR/X86/unknown-subregister-index.mir
+++ b/test/CodeGen/MIR/X86/unknown-subregister-index.mir
@@ -18,14 +18,12 @@ registers:
   - { id: 0, class: gr32 }
   - { id: 1, class: gr8 }
   - { id: 2, class: gr8 }
-body:
-  - name:        entry
-    id:          0
-    instructions:
-      - '%0 = COPY %edi'
-      # CHECK: [[@LINE+1]]:23: use of unknown subregister index 'bit8'
-      - '%1 = COPY %0:bit8'
-      - '%2 = AND8ri %1, 1, implicit-def %eflags'
-      - '%al = COPY %2'
-      - 'RETQ %al'
+body: |
+  bb.0.entry:
+    %0 = COPY %edi
+    ; CHECK: [[@LINE+1]]:18: use of unknown subregister index 'bit8'
+    %1 = COPY %0:bit8
+    %2 = AND8ri %1, 1, implicit-def %eflags
+    %al = COPY %2
+    RETQ %al
 ...
diff --git a/test/CodeGen/MIR/X86/unrecognized-character.mir b/test/CodeGen/MIR/X86/unrecognized-character.mir
index 3b4fb1a9fc6..845ccc8c6d5 100644
--- a/test/CodeGen/MIR/X86/unrecognized-character.mir
+++ b/test/CodeGen/MIR/X86/unrecognized-character.mir
@@ -10,10 +10,8 @@
 ...
 ---
 name:            foo
-body:
- - id:           0
-   name:         entry
-   instructions:
-     # CHECK: [[@LINE+1]]:9: unexpected character '`'
-     - '` RETQ'
+body: |
+  bb.0.entry:
+    ; CHECK: [[@LINE+1]]:5: unexpected character '`'
+    ` RETQ
 ...
diff --git a/test/CodeGen/MIR/X86/used-physical-register-info.mir b/test/CodeGen/MIR/X86/used-physical-register-info.mir
index 7858fe29841..9a81578703e 100644
--- a/test/CodeGen/MIR/X86/used-physical-register-info.mir
+++ b/test/CodeGen/MIR/X86/used-physical-register-info.mir
@@ -41,13 +41,12 @@ liveins:
   - { reg: '%edi' }
 frameInfo:
   stackSize:     8
-body:
-  - id:          0
-    name:        body
-    liveins:     [ '%edi' ]
-    instructions:
-      - '%eax = IMUL32rri8 %edi, 11, implicit-def %eflags'
-      - 'RETQ %eax'
+body: |
+  bb.0.body:
+    liveins: %edi
+
+    %eax = IMUL32rri8 %edi, 11, implicit-def %eflags
+    RETQ %eax
 ...
 ---
 name:            foo
@@ -62,15 +61,14 @@ calleeSavedRegisters: [ '%bh', '%bl', '%bp', '%bpl', '%bx', '%ebp', '%ebx',
                         '%rbp', '%rbx', '%r12', '%r13', '%r14', '%r15',
                         '%r12b', '%r13b', '%r14b', '%r15b', '%r12d', '%r13d',
                         '%r14d', '%r15d', '%r12w', '%r13w', '%r14w', '%r15w' ]
-body:
-  - id:          0
-    name:        entry
-    liveins:     [ '%edi' ]
-    instructions:
-      - 'PUSH64r %rax, implicit-def %rsp, implicit %rsp'
-      - 'CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax'
-      - '%rdx = POP64r implicit-def %rsp, implicit %rsp'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    liveins: %edi
+
+    PUSH64r %rax, implicit-def %rsp, implicit %rsp
+    CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax
+    %rdx = POP64r implicit-def %rsp, implicit %rsp
+    RETQ %eax
 ...
 ---
 name:            bar
@@ -83,15 +81,14 @@ liveins:
 # CHECK-NEXT:                    '%rbp', '%rbx', '%r12', '%r13', '%r14', '%r15',
 # CHECK-NEXT:                    '%r12b', '%r13b', '%r14b', '%r15b', '%r12d', '%r13d',
 # CHECK-NEXT:                    '%r14d', '%r15d', '%r12w', '%r13w', '%r14w', '%r15w' ]
-body:
-  - id:          0
-    name:        entry
-    liveins:     [ '%edi' ]
-    instructions:
-      - 'PUSH64r %rax, implicit-def %rsp, implicit %rsp'
-      - 'CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax'
-      - '%rdx = POP64r implicit-def %rsp, implicit %rsp'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    liveins: %edi
+
+    PUSH64r %rax, implicit-def %rsp, implicit %rsp
+    CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax
+    %rdx = POP64r implicit-def %rsp, implicit %rsp
+    RETQ %eax
 ...
 ---
 name:            empty
@@ -101,13 +98,12 @@ liveins:
 # CHECK: name: empty
 # CHECK: calleeSavedRegisters: [ ]
 calleeSavedRegisters: [ ]
-body:
-  - id:          0
-    name:        entry
-    liveins:     [ '%edi' ]
-    instructions:
-      - 'PUSH64r %rax, implicit-def %rsp, implicit %rsp'
-      - 'CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax'
-      - '%rdx = POP64r implicit-def %rsp, implicit %rsp'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    liveins: %edi
+
+    PUSH64r %rax, implicit-def %rsp, implicit %rsp
+    CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax
+    %rdx = POP64r implicit-def %rsp, implicit %rsp
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/variable-sized-stack-object-size-error.mir b/test/CodeGen/MIR/X86/variable-sized-stack-object-size-error.mir
index 8e50c52f5e1..e6a9ef8d4c8 100644
--- a/test/CodeGen/MIR/X86/variable-sized-stack-object-size-error.mir
+++ b/test/CodeGen/MIR/X86/variable-sized-stack-object-size-error.mir
@@ -25,12 +25,10 @@ stack:
   - { id: 1, offset: -32, size: 8, alignment: 8 }
   # CHECK: [[@LINE+1]]:55: unknown key 'size'
   - { id: 2, type: variable-sized, offset: -32, size: 42, alignment: 1 }
-body:
-  - id:          0
-    name:        entry
-    instructions:
-      - 'MOV32mr %rsp, 1, _, -4, _, %edi'
-      - 'MOV64mi32 %rsp, 1, _, -16, _, 2'
-      - '%eax = MOV32rm %rsp, 1, _, -4, _'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    MOV32mr %rsp, 1, _, -4, _, %edi
+    MOV64mi32 %rsp, 1, _, -16, _, 2
+    %eax = MOV32rm %rsp, 1, _, -4, _
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir b/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir
index 5e6467e9cfa..a58be69ae04 100644
--- a/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir
+++ b/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir
@@ -31,12 +31,10 @@ stack:
   - { id: 0, offset: -20, size: 4, alignment: 4 }
   - { id: 1, offset: -32, size: 8, alignment: 8 }
   - { id: 2, name: y, type: variable-sized, offset: -32, alignment: 1 }
-body:
-  - id:          0
-    name:        entry
-    instructions:
-      - 'MOV32mr %rsp, 1, _, -4, _, %edi'
-      - 'MOV64mi32 %rsp, 1, _, -16, _, 2'
-      - '%eax = MOV32rm %rsp, 1, _, -4, _'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    MOV32mr %rsp, 1, _, -4, _, %edi
+    MOV64mi32 %rsp, 1, _, -16, _, 2
+    %eax = MOV32rm %rsp, 1, _, -4, _
+    RETQ %eax
 ...
diff --git a/test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir b/test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir
index baadeaee3d4..5dae6e666c8 100644
--- a/test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir
+++ b/test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir
@@ -16,13 +16,12 @@ registers:
   - { id: 0, class: gr32 }
 # CHECK: [[@LINE+1]]:11: redefinition of virtual register '%0'
   - { id: 0, class: gr32 }
-body:
-  - id:          0
-    name:        body
-    liveins:     [ '%edi' ]
-    instructions:
-      - '%0 = COPY %edi'
-      - '%eax = COPY %0'
-      - 'RETQ %eax'
+body: |
+  bb.0.body:
+    liveins: %edi
+
+    %0 = COPY %edi
+    %eax = COPY %0
+    RETQ %eax
 ...
 
diff --git a/test/CodeGen/MIR/X86/virtual-registers.mir b/test/CodeGen/MIR/X86/virtual-registers.mir
index cde6b988519..93c2fea6fd9 100644
--- a/test/CodeGen/MIR/X86/virtual-registers.mir
+++ b/test/CodeGen/MIR/X86/virtual-registers.mir
@@ -41,31 +41,27 @@ registers:
   - { id: 0, class: gr32 }
   - { id: 1, class: gr32 }
   - { id: 2, class: gr32 }
-body:
-  - id:          0
-    name:        entry
-    successors:  [ '%bb.2.exit', '%bb.1.less' ]
-    liveins:     [ '%edi' ]
-    # CHECK:      %0 = COPY %edi
-    # CHECK-NEXT: %1 = SUB32ri8 %0, 10
-    instructions:
-      - '%0 = COPY %edi'
-      - '%1 = SUB32ri8 %0, 10, implicit-def %eflags'
-      - 'JG_1 %bb.2.exit, implicit %eflags'
-      - 'JMP_1 %bb.1.less'
-  - id:          1
-    name:        less
-    # CHECK:      %2 = MOV32r0
-    # CHECK-NEXT: %eax = COPY %2
-    instructions:
-      - '%2 = MOV32r0 implicit-def %eflags'
-      - '%eax = COPY %2'
-      - 'RETQ %eax'
-  - id:          2
-    name:        exit
-    instructions:
-      - '%eax = COPY %0'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    successors: %bb.2.exit, %bb.1.less
+    liveins: %edi
+    ; CHECK:      %0 = COPY %edi
+    ; CHECK-NEXT: %1 = SUB32ri8 %0, 10
+    %0 = COPY %edi
+    %1 = SUB32ri8 %0, 10, implicit-def %eflags
+    JG_1 %bb.2.exit, implicit %eflags
+    JMP_1 %bb.1.less
+
+  bb.1.less:
+    ; CHECK:      %2 = MOV32r0
+    ; CHECK-NEXT: %eax = COPY %2
+    %2 = MOV32r0 implicit-def %eflags
+    %eax = COPY %2
+    RETQ %eax
+
+  bb.2.exit:
+    %eax = COPY %0
+    RETQ %eax
 ...
 ---
 name:            foo
@@ -80,30 +76,26 @@ registers:
   - { id: 2, class: gr32 }
   - { id: 0, class: gr32 }
   - { id: 10, class: gr32 }
-body:
-  - id:          0
-    name:        entry
-    successors:  [ '%bb.2.exit', '%bb.1.less' ]
-    liveins:     [ '%edi' ]
-    # CHECK:      %0 = COPY %edi
-    # CHECK-NEXT: %1 = SUB32ri8 %0, 10
-    instructions:
-      - '%2 = COPY %edi'
-      - '%0 = SUB32ri8 %2, 10, implicit-def %eflags'
-      - 'JG_1 %bb.2.exit, implicit %eflags'
-      - 'JMP_1 %bb.1.less'
-  - id:          1
-    name:        less
-    # CHECK:      %2 = MOV32r0
-    # CHECK-NEXT: %eax = COPY %2
-    instructions:
-      - '%10 = MOV32r0 implicit-def %eflags'
-      - '%eax = COPY %10'
-      - 'RETQ %eax'
-  - id:          2
-    name:        exit
-    # CHECK: %eax = COPY %0
-    instructions:
-      - '%eax = COPY %2'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    successors: %bb.2.exit, %bb.1.less
+    liveins: %edi
+    ; CHECK:      %0 = COPY %edi
+    ; CHECK-NEXT: %1 = SUB32ri8 %0, 10
+    %2 = COPY %edi
+    %0 = SUB32ri8 %2, 10, implicit-def %eflags
+    JG_1 %bb.2.exit, implicit %eflags
+    JMP_1 %bb.1.less
+
+  bb.1.less:
+    ; CHECK:      %2 = MOV32r0
+    ; CHECK-NEXT: %eax = COPY %2
+    %10 = MOV32r0 implicit-def %eflags
+    %eax = COPY %10
+    RETQ %eax
+
+  bb.2.exit:
+    ; CHECK: %eax = COPY %0
+    %eax = COPY %2
+    RETQ %eax
 ...