diff options
author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-07-20 21:03:45 +0000 |
---|---|---|
committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-07-20 21:03:45 +0000 |
commit | 20f8334c2a881882c00a375d12c9b9d86fb32462 (patch) | |
tree | fcd7c314de4cfac9811393a2122299ef8d848e77 /test/CodeGen/MIR | |
parent | 9a18b7e82aa58711a312ce2780483682a63edab6 (diff) |
Add an ID field to StackObjects
On AMDGPU SGPR spills are really spilled to another register.
The spiller creates the spills to new frame index objects,
which is used as a placeholder.
This will eventually be replaced with a reference to a position
in a VGPR to write to and the frame index deleted. It is
most likely not a real stack location that can be shared
with another stack object.
This is a problem when StackSlotColoring decides it should
combine a frame index used for a normal VGPR spill with
a real stack location and a frame index used for an SGPR.
Add an ID field so that StackSlotColoring has a way
of knowing the different frame index types are
incompatible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308673 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/MIR')
-rw-r--r-- | test/CodeGen/MIR/AArch64/stack-object-local-offset.mir | 6 | ||||
-rw-r--r-- | test/CodeGen/MIR/AMDGPU/stack-id.mir | 35 | ||||
-rw-r--r-- | test/CodeGen/MIR/X86/callee-saved-info.mir | 2 | ||||
-rw-r--r-- | test/CodeGen/MIR/X86/fixed-stack-objects.mir | 3 | ||||
-rw-r--r-- | test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir | 3 | ||||
-rw-r--r-- | test/CodeGen/MIR/X86/stack-objects.mir | 9 | ||||
-rw-r--r-- | test/CodeGen/MIR/X86/variable-sized-stack-objects.mir | 6 |
7 files changed, 53 insertions, 11 deletions
diff --git a/test/CodeGen/MIR/AArch64/stack-object-local-offset.mir b/test/CodeGen/MIR/AArch64/stack-object-local-offset.mir index cfb3aef5fb0..06e0c8014b5 100644 --- a/test/CodeGen/MIR/AArch64/stack-object-local-offset.mir +++ b/test/CodeGen/MIR/AArch64/stack-object-local-offset.mir @@ -25,9 +25,9 @@ frameInfo: maxAlignment: 8 # CHECK-LABEL: stack_local # CHECK: stack: -# CHECK-NEXT: { id: 0, name: local_var, type: default, offset: 0, size: 8, alignment: 8, -# CHECK-NEXT: callee-saved-register: '', local-offset: -8, di-variable: '', di-expression: '', -# CHECK-NEXT: di-location: '' } +# CHECK: - { id: 0, name: local_var, type: default, offset: 0, size: 8, alignment: 8, +# CHECK-NEXT: stack-id: 0, callee-saved-register: '', local-offset: -8, di-variable: '', +# CHECK-NEXT: di-expression: '', di-location: '' } stack: - { id: 0,name: local_var,offset: 0,size: 8,alignment: 8, local-offset: -8 } body: | diff --git a/test/CodeGen/MIR/AMDGPU/stack-id.mir b/test/CodeGen/MIR/AMDGPU/stack-id.mir new file mode 100644 index 00000000000..c07c0790a1e --- /dev/null +++ b/test/CodeGen/MIR/AMDGPU/stack-id.mir @@ -0,0 +1,35 @@ +# RUN: llc -march=amdgcn -run-pass none -o - %s | FileCheck %s +... +--- + +# CHECK-LABEL: name: spill_slot_stack_id +# CHECK: {{^}}fixedStack: +# CHECK: - { id: 0, type: spill-slot, offset: 0, size: 4, alignment: 4, stack-id: 0, +# CHECK: - { id: 1, type: spill-slot, offset: 0, size: 8, alignment: 4, stack-id: 0, +# CHECK: - { id: 2, type: spill-slot, offset: 0, size: 16, alignment: 4, stack-id: 9, + +# CHECK: {{^}}stack: +# CHECK: - { id: 0, name: '', type: spill-slot, offset: 0, size: 16, +# CHECK-NEXT: stack-id: 3, + +# CHECK: - { id: 1, name: '', type: spill-slot, offset: 0, size: 8, +# CHECK-NEXT: stack-id: 0, + +# CHECK: - { id: 2, name: '', type: spill-slot, offset: 0, size: 4, +# CHECK-NEXT: stack-id: 0, + + +name: spill_slot_stack_id +fixedStack: + - { id: 0, type: spill-slot, offset: 0, size: 16, alignment: 4, stack-id: 9 } + - { id: 1, type: spill-slot, offset: 0, size: 8, alignment: 4, stack-id: 0 } + - { id: 2, type: spill-slot, offset: 0, size: 4, alignment: 4 } +stack: + - { id: 0, name: '', type: spill-slot, offset: 0, size: 16, alignment: 4, stack-id: 3 } + - { id: 1, name: '', type: spill-slot, offset: 0, size: 8, alignment: 4, stack-id: 0 } + - { id: 2, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4 } + +body: | + bb.0: + S_ENDPGM +... diff --git a/test/CodeGen/MIR/X86/callee-saved-info.mir b/test/CodeGen/MIR/X86/callee-saved-info.mir index 6920611019b..2a62b4e4f48 100644 --- a/test/CodeGen/MIR/X86/callee-saved-info.mir +++ b/test/CodeGen/MIR/X86/callee-saved-info.mir @@ -50,7 +50,7 @@ frameInfo: adjustsStack: true hasCalls: true # CHECK: fixedStack: -# CHECK: , callee-saved-register: '%rbx' } +# CHECK: callee-saved-register: '%rbx' } fixedStack: - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: '%rbx' } # CHECK: stack: diff --git a/test/CodeGen/MIR/X86/fixed-stack-objects.mir b/test/CodeGen/MIR/X86/fixed-stack-objects.mir index c87cb0b49f9..93544c426c3 100644 --- a/test/CodeGen/MIR/X86/fixed-stack-objects.mir +++ b/test/CodeGen/MIR/X86/fixed-stack-objects.mir @@ -20,7 +20,8 @@ frameInfo: stackSize: 4 maxAlignment: 4 # CHECK: fixedStack: -# CHECK-NEXT: - { id: 0, type: default, offset: 0, size: 4, alignment: 4, isImmutable: true, +# CHECK-NEXT: - { id: 0, type: default, offset: 0, size: 4, alignment: 4, stack-id: 0 +# CHECK-NEXT: isImmutable: true, fixedStack: - { id: 0, offset: 0, size: 4, alignment: 4, isImmutable: true, isAliased: false } stack: diff --git a/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir b/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir index d3c42236284..86e735e616e 100644 --- a/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir +++ b/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir @@ -19,7 +19,8 @@ name: test frameInfo: maxAlignment: 4 # CHECK: fixedStack: -# CHECK-NEXT: - { id: 0, type: spill-slot, offset: 0, size: 4, alignment: 4, callee-saved-register: '' } +# CHECK-NEXT: - { id: 0, type: spill-slot, offset: 0, size: 4, alignment: 4, stack-id: 0, +# CHECK-NEXT: callee-saved-register: '' } fixedStack: - { id: 0, type: spill-slot, offset: 0, size: 4, alignment: 4 } stack: diff --git a/test/CodeGen/MIR/X86/stack-objects.mir b/test/CodeGen/MIR/X86/stack-objects.mir index 608202ec5dc..ea3e8410df4 100644 --- a/test/CodeGen/MIR/X86/stack-objects.mir +++ b/test/CodeGen/MIR/X86/stack-objects.mir @@ -22,11 +22,14 @@ frameInfo: maxAlignment: 8 # CHECK: stack: # CHECK-NEXT: - { id: 0, name: b, type: default, offset: -12, size: 4, alignment: 4, -# CHECK-NEXT: callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' } +# CHECK-NEXT: stack-id: 0, callee-saved-register: '', di-variable: '', di-expression: '', +# CHECK-NEXT: di-location: '' } # CHECK-NEXT: - { id: 1, name: x, type: default, offset: -24, size: 8, alignment: 8, -# CHECK-NEXT: callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' } +# CHECK-NEXT: stack-id: 0, callee-saved-register: '', di-variable: '', di-expression: '', +# CHECK-NEXT: di-location: '' } # CHECK-NEXT: - { id: 2, name: '', type: spill-slot, offset: -32, size: 4, alignment: 4, -# CHECK-NEXT: callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' } +# CHECK-NEXT: stack-id: 0, callee-saved-register: '', di-variable: '', di-expression: '', +# CHECK-NEXT: di-location: '' } stack: - { id: 0, name: b, offset: -12, size: 4, alignment: 4 } - { id: 1, name: x, offset: -24, size: 8, alignment: 8 } diff --git a/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir b/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir index 95efd977d9c..726ea87fb44 100644 --- a/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir +++ b/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir @@ -25,9 +25,11 @@ frameInfo: adjustsStack: true # CHECK: stack: # CHECK-NEXT: - { id: 0, name: '', type: default, offset: -20, size: 4, alignment: 4, -# CHECK-NEXT: callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' } +# CHECK-NEXT: stack-id: 0, callee-saved-register: '', di-variable: '', di-expression: '', +# CHECK-NEXT: di-location: '' } # CHECK-NEXT: - { id: 1, name: '', type: default, offset: -32, size: 8, alignment: 8, -# CHECK-NEXT: callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' } +# CHECK-NEXT: stack-id: 0, callee-saved-register: '', di-variable: '', di-expression: '', +# CHECK-NEXT: di-location: '' } # CHECK-NEXT: - { id: 2, name: y, type: variable-sized, offset: -32, alignment: 1, stack: - { id: 0, offset: -20, size: 4, alignment: 4 } |