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| author | Nicolai Haehnle <nhaehnle@gmail.com> | 2016-11-02 17:03:11 +0000 |
|---|---|---|
| committer | Nicolai Haehnle <nhaehnle@gmail.com> | 2016-11-02 17:03:11 +0000 |
| commit | 08f7b241492e37a3199eb8e71a8c12ee502f05c9 (patch) | |
| tree | d7c9224c47ad0186ae23e9099d6c631f8a1a74ba /test/CodeGen/MIR | |
| parent | 4c1273222636e393da7584ead9019d9908871a44 (diff) | |
AMDGPU: Allow additional implicit operands on MOVRELS instructions
Summary:
The post-RA scheduler occasionally uses additional implicit operands when
the vector implicit operand as a whole is killed, but some subregisters
are still live because they are directly referenced later. Unfortunately,
this seems incredibly subtle to reproduce.
Fixes piglit spec/glsl-110/execution/variable-indexing/vs-temp-array-mat2-index-wr.shader_test
and others.
Reviewers: arsenm, tstellarAMD
Subscribers: kzhuravl, wdng, yaxunl, tony-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D25656
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285835 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/MIR')
| -rw-r--r-- | test/CodeGen/MIR/AMDGPU/movrels-bug.mir | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/test/CodeGen/MIR/AMDGPU/movrels-bug.mir b/test/CodeGen/MIR/AMDGPU/movrels-bug.mir new file mode 100644 index 00000000000..6493cc8703e --- /dev/null +++ b/test/CodeGen/MIR/AMDGPU/movrels-bug.mir @@ -0,0 +1,31 @@ +# RUN: llc -march=amdgcn -verify-machineinstrs -run-pass post-RA-sched %s -o - | FileCheck %s + +# This tests a situation where a sub-register of a killed super-register operand +# of V_MOVRELS happens to have an undef use later on. This leads to the post RA +# scheduler adding additional implicit operands to the V_MOVRELS, which used +# to fail machine instruction verification. + +--- | + + define amdgpu_vs void @main(i32 %arg) { ret void } + +... +--- +# CHECK-LABEL: name: main +# CHECK-LABEL: bb.0: +# CHECK: V_MOVRELS_B32_e32 +# CHECK: V_MAC_F32_e32 + +name: main +tracksRegLiveness: true +body: | + bb.0: + %m0 = S_MOV_B32 undef %sgpr0 + V_MOVRELD_B32_e32 undef %vgpr2, 0, implicit %m0, implicit %exec, implicit-def %vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8, implicit undef %vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8(tied-def 4) + %m0 = S_MOV_B32 undef %sgpr0 + %vgpr1 = V_MOVRELS_B32_e32 undef %vgpr1, implicit %m0, implicit %exec, implicit killed %vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8 + %vgpr4 = V_MAC_F32_e32 undef %vgpr0, undef %vgpr0, undef %vgpr4, implicit %exec + EXP 15, 12, 0, 1, 0, undef %vgpr0, killed %vgpr1, killed %vgpr4, undef %vgpr0, implicit %exec + S_ENDPGM + +... |