diff options
| author | Justin Bogner <mail@justinbogner.com> | 2017-10-24 18:04:54 +0000 |
|---|---|---|
| committer | Justin Bogner <mail@justinbogner.com> | 2017-10-24 18:04:54 +0000 |
| commit | edab7579664b13faad3680c676c6b8a49d2ea00b (patch) | |
| tree | dee3b97d46f3325ed2ceb0ddedb5e54e151a3676 /test/CodeGen/MIR/NVPTX | |
| parent | 7c330fabaedaba3d02c58bc3cc1198896c895f34 (diff) | |
MIR: Print the register class or bank in vreg defs
This updates the MIRPrinter to include the regclass when printing
virtual register defs, which is already valid syntax for the
parser. That is, given 64 bit %0 and %1 in a "gpr" regbank,
%1(s64) = COPY %0(s64)
would now be written as
%1:gpr(s64) = COPY %0(s64)
While this change alone introduces a bit of redundancy with the
registers block, it allows us to update the tests to be more concise
and understandable and brings us closer to being able to remove the
registers block completely.
Note: We generally only print the class in defs, but there is one
exception. If there are uses without any defs whatsoever, we'll print
the class on all uses. I'm not completely convinced this comes up in
meaningful machine IR, but for now the MIRParser and MachineVerifier
both accept that kind of stuff, so we don't want to have a situation
where we can print something we can't parse.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316479 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/MIR/NVPTX')
| -rw-r--r-- | test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir b/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir index 312bf004a9c..71d232b58cf 100644 --- a/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir +++ b/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir @@ -43,11 +43,11 @@ body: | %0 = LD_f32_avar 0, 4, 1, 2, 32, $test_param_0 %1 = CVT_f64_f32 %0, 0 %2 = LD_i32_avar 0, 4, 1, 0, 32, $test_param_1 - ; CHECK: %3 = FADD_rnf64ri %1, double 3.250000e+00 + ; CHECK: %3:float64regs = FADD_rnf64ri %1, double 3.250000e+00 %3 = FADD_rnf64ri %1, double 3.250000e+00 %4 = CVT_f32_f64 %3, 5 %5 = CVT_f32_s32 %2, 5 - ; CHECK: %6 = FADD_rnf32ri %5, float 6.250000e+00 + ; CHECK: %6:float32regs = FADD_rnf32ri %5, float 6.250000e+00 %6 = FADD_rnf32ri %5, float 6.250000e+00 %7 = FMUL_rnf32rr %6, %4 StoreRetvalF32 %7, 0 @@ -69,11 +69,11 @@ body: | %0 = LD_f32_avar 0, 4, 1, 2, 32, $test2_param_0 %1 = CVT_f64_f32 %0, 0 %2 = LD_i32_avar 0, 4, 1, 0, 32, $test2_param_1 - ; CHECK: %3 = FADD_rnf64ri %1, double 0x7FF8000000000000 + ; CHECK: %3:float64regs = FADD_rnf64ri %1, double 0x7FF8000000000000 %3 = FADD_rnf64ri %1, double 0x7FF8000000000000 %4 = CVT_f32_f64 %3, 5 %5 = CVT_f32_s32 %2, 5 - ; CHECK: %6 = FADD_rnf32ri %5, float 0x7FF8000000000000 + ; CHECK: %6:float32regs = FADD_rnf32ri %5, float 0x7FF8000000000000 %6 = FADD_rnf32ri %5, float 0x7FF8000000000000 %7 = FMUL_rnf32rr %6, %4 StoreRetvalF32 %7, 0 |