MIR Serialization: Change MIR syntax - use custom syntax for MBBs.

This commit modifies the way the machine basic blocks are serialized - now the
machine basic blocks are serialized using a custom syntax instead of relying on
YAML primitives. Instead of using YAML mappings to represent the individual
machine basic blocks in a machine function's body, the new syntax uses a single
YAML block scalar which contains all of the machine basic blocks and
instructions for that function.

This is an example of a function's body that uses the old syntax:

    body:
      - id: 0
        name: entry
        instructions:
          - '%eax = MOV32r0 implicit-def %eflags'
          - 'RETQ %eax'
    ...

The same body is now written like this:

    body: |
      bb.0.entry:
        %eax = MOV32r0 implicit-def %eflags
        RETQ %eax
    ...

This syntax change is motivated by the fact that the bundled machine
instructions didn't map that well to the old syntax which was using a single
YAML sequence to store all of the machine instructions in a block. The bundled
machine instructions internally use flags like BundledPred and BundledSucc to
determine the bundles, and serializing them as MI flags using the old syntax
would have had a negative impact on the readability and the ease of editing
for MIR files. The new syntax allows me to serialize the bundled machine
instructions using a block construct without relying on the internal flags,
for example:

   BUNDLE implicit-def dead %itstate, implicit-def %s1 ... {
      t2IT 1, 24, implicit-def %itstate
      %s1 = VMOVS killed %s0, 1, killed %cpsr, implicit killed %itstate
   }

This commit also converts the MIR testcases to the new syntax. I developed
a script that can convert from the old syntax to the new one. I will post the
script on the llvm-commits mailing list in the thread for this commit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@244982 91177308-0d34-0410-b5e6-96231b3b80d8

3 files changed, 42 insertions, 50 deletions

diff --git a/test/CodeGen/MIR/NVPTX/expected-floating-point-literal.mir b/test/CodeGen/MIR/NVPTX/expected-floating-point-literal.mir
index 1a746ce802b..28fb2a2cf5c 100644
--- a/test/CodeGen/MIR/NVPTX/expected-floating-point-literal.mir
+++ b/test/CodeGen/MIR/NVPTX/expected-floating-point-literal.mir
@@ -14,13 +14,11 @@ name:            test
 registers:
   - { id: 0, class: float32regs }
   - { id: 1, class: float32regs }
-body:
-  - id:              0
-    name:            entry
-    instructions:
-      - '%0 = LD_f32_avar 0, 4, 1, 2, 32, $test_param_0'
-# CHECK: [[@LINE+1]]:38: expected a floating point literal
-      - '%1 = FADD_rnf32ri %0, float 3'
-      - 'StoreRetvalF32 %1, 0'
-      - Return
+body: |
+  bb.0.entry:
+    %0 = LD_f32_avar 0, 4, 1, 2, 32, $test_param_0
+  ; CHECK: [[@LINE+1]]:33: expected a floating point literal
+    %1 = FADD_rnf32ri %0, float 3
+    StoreRetvalF32 %1, 0
+    Return
 ...
diff --git a/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir b/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir
index 3b2ae0f99ee..18866d58a94 100644
--- a/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir
+++ b/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir
@@ -38,22 +38,20 @@ registers:
   - { id: 5, class: float32regs }
   - { id: 6, class: float32regs }
   - { id: 7, class: float32regs }
-body:
-  - id:              0
-    name:            entry
-    instructions:
-      - '%0 = LD_f32_avar 0, 4, 1, 2, 32, $test_param_0'
-      - '%1 = CVT_f64_f32 %0, 0'
-      - '%2 = LD_i32_avar 0, 4, 1, 0, 32, $test_param_1'
-# CHECK: %3 = FADD_rnf64ri %1, double 3.250000e+00
-      - '%3 = FADD_rnf64ri %1, double 3.250000e+00'
-      - '%4 = CVT_f32_f64 %3, 5'
-      - '%5 = CVT_f32_s32 %2, 5'
-# CHECK: %6 = FADD_rnf32ri %5, float 6.250000e+00
-      - '%6 = FADD_rnf32ri %5, float 6.250000e+00'
-      - '%7 = FMUL_rnf32rr %6, %4'
-      - 'StoreRetvalF32 %7, 0'
-      - Return
+body: |
+  bb.0.entry:
+    %0 = LD_f32_avar 0, 4, 1, 2, 32, $test_param_0
+    %1 = CVT_f64_f32 %0, 0
+    %2 = LD_i32_avar 0, 4, 1, 0, 32, $test_param_1
+  ; CHECK: %3 = FADD_rnf64ri %1, double 3.250000e+00
+    %3 = FADD_rnf64ri %1, double 3.250000e+00
+    %4 = CVT_f32_f64 %3, 5
+    %5 = CVT_f32_s32 %2, 5
+  ; CHECK: %6 = FADD_rnf32ri %5, float 6.250000e+00
+    %6 = FADD_rnf32ri %5, float 6.250000e+00
+    %7 = FMUL_rnf32rr %6, %4
+    StoreRetvalF32 %7, 0
+    Return
 ...
 ---
 name:            test2
@@ -66,20 +64,18 @@ registers:
   - { id: 5, class: float32regs }
   - { id: 6, class: float32regs }
   - { id: 7, class: float32regs }
-body:
-  - id:              0
-    name:            entry
-    instructions:
-      - '%0 = LD_f32_avar 0, 4, 1, 2, 32, $test2_param_0'
-      - '%1 = CVT_f64_f32 %0, 0'
-      - '%2 = LD_i32_avar 0, 4, 1, 0, 32, $test2_param_1'
-# CHECK: %3 = FADD_rnf64ri %1, double 0x7FF8000000000000
-      - '%3 = FADD_rnf64ri %1, double 0x7FF8000000000000'
-      - '%4 = CVT_f32_f64 %3, 5'
-      - '%5 = CVT_f32_s32 %2, 5'
-# CHECK: %6 = FADD_rnf32ri %5, float 0x7FF8000000000000
-      - '%6 = FADD_rnf32ri %5, float 0x7FF8000000000000'
-      - '%7 = FMUL_rnf32rr %6, %4'
-      - 'StoreRetvalF32 %7, 0'
-      - Return
+body: |
+  bb.0.entry:
+    %0 = LD_f32_avar 0, 4, 1, 2, 32, $test2_param_0
+    %1 = CVT_f64_f32 %0, 0
+    %2 = LD_i32_avar 0, 4, 1, 0, 32, $test2_param_1
+  ; CHECK: %3 = FADD_rnf64ri %1, double 0x7FF8000000000000
+    %3 = FADD_rnf64ri %1, double 0x7FF8000000000000
+    %4 = CVT_f32_f64 %3, 5
+    %5 = CVT_f32_s32 %2, 5
+  ; CHECK: %6 = FADD_rnf32ri %5, float 0x7FF8000000000000
+    %6 = FADD_rnf32ri %5, float 0x7FF8000000000000
+    %7 = FMUL_rnf32rr %6, %4
+    StoreRetvalF32 %7, 0
+    Return
 ...
diff --git a/test/CodeGen/MIR/NVPTX/floating-point-invalid-type-error.mir b/test/CodeGen/MIR/NVPTX/floating-point-invalid-type-error.mir
index 810fa15bedd..e4080f80ee5 100644
--- a/test/CodeGen/MIR/NVPTX/floating-point-invalid-type-error.mir
+++ b/test/CodeGen/MIR/NVPTX/floating-point-invalid-type-error.mir
@@ -14,13 +14,11 @@ name:            test
 registers:
   - { id: 0, class: float32regs }
   - { id: 1, class: float32regs }
-body:
-  - id:              0
-    name:            entry
-    instructions:
-      - '%0 = LD_f32_avar 0, 4, 1, 2, 32, $test_param_0'
-# CHECK: [[@LINE+1]]:38: floating point constant does not have type 'float'
-      - '%1 = FADD_rnf32ri %0, float 0xH3C00'
-      - 'StoreRetvalF32 %1, 0'
-      - Return
+body: |
+  bb.0.entry:
+    %0 = LD_f32_avar 0, 4, 1, 2, 32, $test_param_0
+  ; CHECK: [[@LINE+1]]:33: floating point constant does not have type 'float'
+    %1 = FADD_rnf32ri %0, float 0xH3C00
+    StoreRetvalF32 %1, 0
+    Return
 ...