[lanai] Add subword scheduling itineraries.

Differentiate between word and subword memory operations as they take different
amount of cycles to complete. This just adds a basic model of the subword
latency to the scheduler.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266898 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 29 insertions, 0 deletions

diff --git a/test/CodeGen/Lanai/subword.ll b/test/CodeGen/Lanai/subword.ll
new file mode 100644
index 00000000000..c0e1eaf6ad3
--- /dev/null
+++ b/test/CodeGen/Lanai/subword.ll
@@ -0,0 +1,29 @@
+; RUN: llc < %s -mtriple=lanai-unknown-unknown | FileCheck %s
+
+; Test scheduling of subwords.
+
+%struct.X = type { i16, i16 }
+
+define void @f(%struct.X* inreg nocapture %c) #0 {
+entry:
+  %a = getelementptr inbounds %struct.X, %struct.X* %c, i32 0, i32 0
+  %0 = load i16, i16* %a, align 2
+  %inc = add i16 %0, 1
+  store i16 %inc, i16* %a, align 2
+  %b = getelementptr inbounds %struct.X, %struct.X* %c, i32 0, i32 1
+  %1 = load i16, i16* %b, align 2
+  %dec = add i16 %1, -1
+  store i16 %dec, i16* %b, align 2
+  ret void
+}
+
+; Verify that the two loads occur before the stores. Without memory
+; disambiguation and subword schedule, the resultant code was a per subword
+; load-modify-store sequence instead of the more optimal schedule where all
+; loads occurred before modification and storage.
+; CHECK:      uld.h
+; CHECK-NEXT: uld.h
+; CHECK-NEXT: add
+; CHECK-NEXT: st.h
+; CHECK-NEXT: sub
+; CHECK-NEXT: st.h