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| author | Alex Bradbury <asb@lowrisc.org> | 2017-12-07 10:26:05 +0000 |
|---|---|---|
| committer | Alex Bradbury <asb@lowrisc.org> | 2017-12-07 10:26:05 +0000 |
| commit | e65af32d44f2d727de5ad3dda03a60fffe3ecdb7 (patch) | |
| tree | 8076df901edd1b67d0be261efc48a5f5a9cbea7c /test/CodeGen/ARM | |
| parent | 2bd791038b53582293a9a6e9704af1c790f2f0b7 (diff) | |
[RISCV] MC layer support for the standard RV32F instruction set extension
The most interesting part of this patch is probably the handling of
rounding mode arguments. Sadly, the RISC-V assembler handles floating point
rounding modes as a special "argument" when it would be more consistent to
handle them like the atomics, opcode suffixes. This patch supports parsing
this optional parameter, using InstAlias to allow parsing these floating point
instructions when no rounding mode is specified.
Differential Revision: https://reviews.llvm.org/D39893
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320020 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM')
0 files changed, 0 insertions, 0 deletions