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authorBob Wilson <bob.wilson@apple.com>2010-07-14 01:22:12 +0000
committerBob Wilson <bob.wilson@apple.com>2010-07-14 01:22:12 +0000
commit9e82bf12a03117bfce78217662d5cf8e74aef357 (patch)
tree1eee14d7faf92bd09981243744c858ea358e61fc /test/CodeGen/ARM/vdup.ll
parenta10b8494a50108482302f6f077d72fbc76d776ed (diff)
Add an ARM-specific DAG combining to avoid redundant VDUPLANE nodes.
Radar 7373643. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108303 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM/vdup.ll')
-rw-r--r--test/CodeGen/ARM/vdup.ll12
1 files changed, 12 insertions, 0 deletions
diff --git a/test/CodeGen/ARM/vdup.ll b/test/CodeGen/ARM/vdup.ll
index 50e4df9f57c..a545f6c03d5 100644
--- a/test/CodeGen/ARM/vdup.ll
+++ b/test/CodeGen/ARM/vdup.ll
@@ -267,3 +267,15 @@ entry:
%0 = shufflevector <2 x double> %arg0_int64x1_t, <2 x double> undef, <2 x i32> <i32 0, i32 0>
ret <2 x double> %0
}
+
+; Radar 7373643
+;CHECK: redundantVdup:
+;CHECK: vmov.i8
+;CHECK-NOT: vdup.8
+;CHECK: vstr.64
+define void @redundantVdup(<8 x i8>* %ptr) nounwind {
+ %1 = insertelement <8 x i8> undef, i8 -128, i32 0
+ %2 = shufflevector <8 x i8> %1, <8 x i8> undef, <8 x i32> zeroinitializer
+ store <8 x i8> %2, <8 x i8>* %ptr, align 8
+ ret void
+}