diff options
author | David Blaikie <dblaikie@gmail.com> | 2015-02-27 21:17:42 +0000 |
---|---|---|
committer | David Blaikie <dblaikie@gmail.com> | 2015-02-27 21:17:42 +0000 |
commit | 7c9c6ed761bf9d28c0c257a045b35781969136e0 (patch) | |
tree | 508cac951011b10e2817eacecc1fa640bbdba51e /test/CodeGen/ARM/thumb1_return_sequence.ll | |
parent | dc64962c8649964d13cc60b83c8c400d5ae7504a (diff) |
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM/thumb1_return_sequence.ll')
-rw-r--r-- | test/CodeGen/ARM/thumb1_return_sequence.ll | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/test/CodeGen/ARM/thumb1_return_sequence.ll b/test/CodeGen/ARM/thumb1_return_sequence.ll index c83126098f7..9c62faeaa68 100644 --- a/test/CodeGen/ARM/thumb1_return_sequence.ll +++ b/test/CodeGen/ARM/thumb1_return_sequence.ll @@ -13,10 +13,10 @@ entry: %b = alloca <6 x i32>, align 16 %a = alloca <4 x i32>, align 16 - %stuff = load <6 x i32>* %p, align 16 + %stuff = load <6 x i32>, <6 x i32>* %p, align 16 store <6 x i32> %stuff, <6 x i32>* %b, align 16 store <4 x i32> <i32 0, i32 1, i32 2, i32 3>, <4 x i32>* %a, align 16 - %0 = load <4 x i32>* %a, align 16 + %0 = load <4 x i32>, <4 x i32>* %a, align 16 ret <4 x i32> %0 ; Epilogue @@ -46,7 +46,7 @@ entry: %a = alloca <4 x i32>, align 16 store <4 x i32> <i32 42, i32 42, i32 42, i32 42>, <4 x i32>* %b, align 16 store <4 x i32> <i32 0, i32 1, i32 2, i32 3>, <4 x i32>* %a, align 16 - %0 = load <4 x i32>* %a, align 16 + %0 = load <4 x i32>, <4 x i32>* %a, align 16 call void @llvm.va_start(i8* null) ret <4 x i32> %0 @@ -78,7 +78,7 @@ entry: ; CHECK-V4T: push {[[SAVED:(r[4567](, )?)+]], lr} ; CHECK-V5T: push {[[SAVED:(r[4567](, )?)+]], lr} - %0 = load <6 x i32>* %p, align 16 + %0 = load <6 x i32>, <6 x i32>* %p, align 16 %1 = extractelement <6 x i32> %0, i32 0 %2 = extractelement <6 x i32> %0, i32 1 %3 = extractelement <6 x i32> %0, i32 2 @@ -121,24 +121,24 @@ entry: store i32 2, i32* %b, align 4 store i32 3, i32* %c, align 4 store i32 4, i32* %d, align 4 - %0 = load i32* %a, align 4 + %0 = load i32, i32* %a, align 4 %inc = add nsw i32 %0, 1 store i32 %inc, i32* %a, align 4 - %1 = load i32* %b, align 4 + %1 = load i32, i32* %b, align 4 %inc1 = add nsw i32 %1, 1 store i32 %inc1, i32* %b, align 4 - %2 = load i32* %c, align 4 + %2 = load i32, i32* %c, align 4 %inc2 = add nsw i32 %2, 1 store i32 %inc2, i32* %c, align 4 - %3 = load i32* %d, align 4 + %3 = load i32, i32* %d, align 4 %inc3 = add nsw i32 %3, 1 store i32 %inc3, i32* %d, align 4 - %4 = load i32* %a, align 4 - %5 = load i32* %b, align 4 + %4 = load i32, i32* %a, align 4 + %5 = load i32, i32* %b, align 4 %add = add nsw i32 %4, %5 - %6 = load i32* %c, align 4 + %6 = load i32, i32* %c, align 4 %add4 = add nsw i32 %add, %6 - %7 = load i32* %d, align 4 + %7 = load i32, i32* %d, align 4 %add5 = add nsw i32 %add4, %7 %add6 = add nsw i32 %add5, %i call void @llvm.va_start(i8* null) |