diff options
author | Jan Wen Voung <jvoung@google.com> | 2015-02-02 16:56:50 +0000 |
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committer | Jan Wen Voung <jvoung@google.com> | 2015-02-02 16:56:50 +0000 |
commit | 1a63641597639d19597e2629bab134c2642c3bc3 (patch) | |
tree | df3fb19815ff8e85d5b885a4d09758d674227d06 /test/CodeGen/ARM/sub-cmp-peephole.ll | |
parent | 40d542097aef5f334d870aa7a4c169ca1afc5763 (diff) |
Fix ARM peephole optimizeCompare to avoid optimizing unsigned cmp to 0.
Summary:
Previously it only avoided optimizing signed comparisons to 0.
Sometimes the DAGCombiner will optimize the unsigned comparisons
to 0 before it gets to the peephole pass, but sometimes it doesn't.
Fix for PR22373.
Test Plan: test/CodeGen/ARM/sub-cmp-peephole.ll
Reviewers: jfb, manmanren
Subscribers: aemerson, llvm-commits
Differential Revision: http://reviews.llvm.org/D7274
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227809 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM/sub-cmp-peephole.ll')
-rw-r--r-- | test/CodeGen/ARM/sub-cmp-peephole.ll | 60 |
1 files changed, 60 insertions, 0 deletions
diff --git a/test/CodeGen/ARM/sub-cmp-peephole.ll b/test/CodeGen/ARM/sub-cmp-peephole.ll index 19727dabf09..f7328dc580e 100644 --- a/test/CodeGen/ARM/sub-cmp-peephole.ll +++ b/test/CodeGen/ARM/sub-cmp-peephole.ll @@ -88,6 +88,19 @@ if.end11: ; preds = %num2long.exit ret i32 23 } +; When considering the producer of cmp's src as the subsuming instruction, +; only consider that when the comparison is to 0. +define i32 @cmp_src_nonzero(i32 %a, i32 %b, i32 %x, i32 %y) { +entry: +; CHECK-LABEL: cmp_src_nonzero: +; CHECK: sub +; CHECK: cmp + %sub = sub i32 %a, %b + %cmp = icmp eq i32 %sub, 17 + %ret = select i1 %cmp, i32 %x, i32 %y + ret i32 %ret +} + define float @float_sel(i32 %a, i32 %b, float %x, float %y) { entry: ; CHECK-LABEL: float_sel: @@ -144,3 +157,50 @@ entry: store i32 %sub, i32* @t ret double %ret } + +declare void @abort() +declare void @exit(i32) + +; If the comparison uses the V bit (signed overflow/underflow), we can't +; omit the comparison. +define i32 @cmp_slt0(i32 %a, i32 %b, i32 %x, i32 %y) { +entry: +; CHECK-LABEL: cmp_slt0 +; CHECK: sub +; CHECK: cmp +; CHECK: bge + %load = load i32* @t, align 4 + %sub = sub i32 %load, 17 + %cmp = icmp slt i32 %sub, 0 + br i1 %cmp, label %if.then, label %if.else + +if.then: + call void @abort() + unreachable + +if.else: + call void @exit(i32 0) + unreachable +} + +; Same for the C bit. (Note the ult X, 0 is trivially +; false, so the DAG combiner may or may not optimize it). +define i32 @cmp_ult0(i32 %a, i32 %b, i32 %x, i32 %y) { +entry: +; CHECK-LABEL: cmp_ult0 +; CHECK: sub +; CHECK: cmp +; CHECK: bhs + %load = load i32* @t, align 4 + %sub = sub i32 %load, 17 + %cmp = icmp ult i32 %sub, 0 + br i1 %cmp, label %if.then, label %if.else + +if.then: + call void @abort() + unreachable + +if.else: + call void @exit(i32 0) + unreachable +} |