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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-09-05 23:58:02 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-09-05 23:58:02 +0000 |
| commit | 098c6a547fe540b3bbace4c3d4713f400c67b8a9 (patch) | |
| tree | 423e7a59c4df5905f14f8c8ff446868cfd55078e /test/CodeGen/ARM/select_xform.ll | |
| parent | 366df7945f0e65052d2e1df701ae1fd16b943642 (diff) | |
Use predication instead of pseudo-opcodes when folding into MOVCC.
Now that it is possible to dynamically tie MachineInstr operands,
predicated instructions are possible in SSA form:
%vreg3<def> = SUBri %vreg1, -2147483647, pred:14, pred:%noreg, %opt:%noreg
%vreg4<def,tied1> = MOVCCr %vreg3<tied0>, %vreg1, %pred:12, pred:%CPSR
Becomes a predicated SUBri with a tied imp-use:
SUBri %vreg1, -2147483647, pred:13, pred:%CPSR, opt:%noreg, %vreg1<imp-use,tied0>
This means that any instruction that is safe to move can be folded into
a MOVCC, and the *CC pseudo-instructions are no longer needed.
The test case changes reflect that Thumb2SizeReduce recognizes the
predicated instructions. It didn't understand the pseudos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163274 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM/select_xform.ll')
| -rw-r--r-- | test/CodeGen/ARM/select_xform.ll | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/test/CodeGen/ARM/select_xform.ll b/test/CodeGen/ARM/select_xform.ll index cfc0e701200..75078089126 100644 --- a/test/CodeGen/ARM/select_xform.ll +++ b/test/CodeGen/ARM/select_xform.ll @@ -9,7 +9,7 @@ define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind { ; T2: t1: ; T2: mvn r0, #-2147483648 -; T2: addle.w r1, r1 +; T2: addle r1, r0 ; T2: mov r0, r1 %tmp1 = icmp sgt i32 %c, 10 %tmp2 = select i1 %tmp1, i32 0, i32 2147483647 @@ -23,7 +23,7 @@ define i32 @t2(i32 %a, i32 %b, i32 %c, i32 %d) nounwind { ; ARM: mov r0, r1 ; T2: t2: -; T2: suble.w r1, r1, #10 +; T2: suble r1, #10 ; T2: mov r0, r1 %tmp1 = icmp sgt i32 %c, 10 %tmp2 = select i1 %tmp1, i32 0, i32 10 @@ -37,7 +37,7 @@ define i32 @t3(i32 %a, i32 %b, i32 %x, i32 %y) nounwind { ; ARM: mov r0, r3 ; T2: t3: -; T2: andge.w r3, r3, r2 +; T2: andge r3, r2 ; T2: mov r0, r3 %cond = icmp slt i32 %a, %b %z = select i1 %cond, i32 -1, i32 %x @@ -51,7 +51,7 @@ define i32 @t4(i32 %a, i32 %b, i32 %x, i32 %y) nounwind { ; ARM: mov r0, r3 ; T2: t4: -; T2: orrge.w r3, r3, r2 +; T2: orrge r3, r2 ; T2: mov r0, r3 %cond = icmp slt i32 %a, %b %z = select i1 %cond, i32 0, i32 %x @@ -81,7 +81,7 @@ define i32 @t6(i32 %a, i32 %b, i32 %c, i32 %d) nounwind { ; T2: t6: ; T2-NOT: movge -; T2: eorlt.w r3, r3, r2 +; T2: eorlt r3, r2 %cond = icmp slt i32 %a, %b %tmp1 = select i1 %cond, i32 %c, i32 0 %tmp2 = xor i32 %tmp1, %d @@ -200,7 +200,7 @@ entry: ; T2: t13 ; T2: cmp r1, #10 -; T2: addgt.w r0, r0, #1 +; T2: addgt r0, #1 %cmp = icmp sgt i32 %a, 10 %conv = zext i1 %cmp to i32 %add = add i32 %conv, %c @@ -216,7 +216,7 @@ entry: ; T2: t14 ; T2: cmp r1, #10 -; T2: subgt.w r0, r0, #1 +; T2: subgt r0, #1 %cmp = icmp sgt i32 %a, 10 %conv = sext i1 %cmp to i32 %add = add i32 %conv, %c |