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author | Hans Wennborg <hans@hanshq.net> | 2018-01-17 16:29:10 +0000 |
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committer | Hans Wennborg <hans@hanshq.net> | 2018-01-17 16:29:10 +0000 |
commit | 57ed2ef9cfdb90107904c705e7f84e816be22d92 (patch) | |
tree | 56d655761ffc66c5d3892c6af63831631039690b /test/CodeGen/ARM/peephole-phi.mir | |
parent | 489cae9d77dd8f89a0bea5f2bac501299c34bdcc (diff) |
Merging r322313:
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r322313 | matze | 2018-01-11 13:57:03 -0800 (Thu, 11 Jan 2018) | 18 lines
PeepholeOptimizer: Do not form PHI with subreg arguments
When replacing a PHI the PeepholeOptimizer currently takes the register
class of the register at the first operand. This however is not correct
if this argument has a subregister index.
As there is currently no API to query the register class resulting from
applying a subregister index to all registers in a class, we can only
abort in these cases and not perform the transformation.
This changes findNextSource() to require the end of all copy chains to
not use a subregister if there is any PHI in the chain. I had to rewrite
the overly complicated inner loop there to have a good place to insert
the new check.
This fixes https://llvm.org/PR33071 (aka rdar://32262041)
Differential Revision: https://reviews.llvm.org/D40758
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@322684 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM/peephole-phi.mir')
-rw-r--r-- | test/CodeGen/ARM/peephole-phi.mir | 67 |
1 files changed, 67 insertions, 0 deletions
diff --git a/test/CodeGen/ARM/peephole-phi.mir b/test/CodeGen/ARM/peephole-phi.mir new file mode 100644 index 00000000000..30343654dea --- /dev/null +++ b/test/CodeGen/ARM/peephole-phi.mir @@ -0,0 +1,67 @@ +# RUN: llc -o - %s -mtriple=armv7-- -verify-machineinstrs -run-pass=peephole-opt | FileCheck %s +# +# Make sure we do not crash on this input. +# Note that this input could in principle be optimized, but right now we don't +# have this case implemented so the output should simply be unchanged. +# +# CHECK-LABEL: name: func +# CHECK: body: | +# CHECK: bb.0: +# CHECK: Bcc %bb.2, 1, undef %cpsr +# +# CHECK: bb.1: +# CHECK: %0:dpr = IMPLICIT_DEF +# CHECK: %1:gpr, %2:gpr = VMOVRRD %0, 14, %noreg +# CHECK: B %bb.3 +# +# CHECK: bb.2: +# CHECK: %3:spr = IMPLICIT_DEF +# CHECK: %4:gpr = VMOVRS %3, 14, %noreg +# +# CHECK: bb.3: +# CHECK: %5:gpr = PHI %1, %bb.1, %4, %bb.2 +# CHECK: %6:spr = VMOVSR %5, 14, %noreg +--- +name: func0 +tracksRegLiveness: true +body: | + bb.0: + Bcc %bb.2, 1, undef %cpsr + + bb.1: + %0:dpr = IMPLICIT_DEF + %1:gpr, %2:gpr = VMOVRRD %0:dpr, 14, %noreg + B %bb.3 + + bb.2: + %3:spr = IMPLICIT_DEF + %4:gpr = VMOVRS %3:spr, 14, %noreg + + bb.3: + %5:gpr = PHI %1, %bb.1, %4, %bb.2 + %6:spr = VMOVSR %5, 14, %noreg +... + +# CHECK-LABEL: name: func1 +# CHECK: %6:spr = PHI %0, %bb.1, %2, %bb.2 +# CHEKC: %7:spr = COPY %6 +--- +name: func1 +tracksRegLiveness: true +body: | + bb.0: + Bcc %bb.2, 1, undef %cpsr + + bb.1: + %1:spr = IMPLICIT_DEF + %0:gpr = VMOVRS %1, 14, %noreg + B %bb.3 + + bb.2: + %3:spr = IMPLICIT_DEF + %2:gpr = VMOVRS %3:spr, 14, %noreg + + bb.3: + %4:gpr = PHI %0, %bb.1, %2, %bb.2 + %5:spr = VMOVSR %4, 14, %noreg +... |