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| author | David Blaikie <dblaikie@gmail.com> | 2015-02-27 21:17:42 +0000 |
|---|---|---|
| committer | David Blaikie <dblaikie@gmail.com> | 2015-02-27 21:17:42 +0000 |
| commit | 7c9c6ed761bf9d28c0c257a045b35781969136e0 (patch) | |
| tree | 508cac951011b10e2817eacecc1fa640bbdba51e /test/CodeGen/ARM/neon_ld2.ll | |
| parent | dc64962c8649964d13cc60b83c8c400d5ae7504a (diff) | |
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM/neon_ld2.ll')
| -rw-r--r-- | test/CodeGen/ARM/neon_ld2.ll | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/test/CodeGen/ARM/neon_ld2.ll b/test/CodeGen/ARM/neon_ld2.ll index 571a16a061d..5bd6ae6d2a9 100644 --- a/test/CodeGen/ARM/neon_ld2.ll +++ b/test/CodeGen/ARM/neon_ld2.ll @@ -13,8 +13,8 @@ ; SWIFT: vst1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+:128\]}} define void @t1(<4 x i32>* %r, <2 x i64>* %a, <2 x i64>* %b) nounwind { entry: - %0 = load <2 x i64>* %a, align 16 ; <<2 x i64>> [#uses=1] - %1 = load <2 x i64>* %b, align 16 ; <<2 x i64>> [#uses=1] + %0 = load <2 x i64>, <2 x i64>* %a, align 16 ; <<2 x i64>> [#uses=1] + %1 = load <2 x i64>, <2 x i64>* %b, align 16 ; <<2 x i64>> [#uses=1] %2 = add <2 x i64> %0, %1 ; <<2 x i64>> [#uses=1] %3 = bitcast <2 x i64> %2 to <4 x i32> ; <<4 x i32>> [#uses=1] store <4 x i32> %3, <4 x i32>* %r, align 16 @@ -35,8 +35,8 @@ entry: ; SWIFT: vmov r2, r3, d define <4 x i32> @t2(<2 x i64>* %a, <2 x i64>* %b) nounwind readonly { entry: - %0 = load <2 x i64>* %a, align 16 ; <<2 x i64>> [#uses=1] - %1 = load <2 x i64>* %b, align 16 ; <<2 x i64>> [#uses=1] + %0 = load <2 x i64>, <2 x i64>* %a, align 16 ; <<2 x i64>> [#uses=1] + %1 = load <2 x i64>, <2 x i64>* %b, align 16 ; <<2 x i64>> [#uses=1] %2 = sub <2 x i64> %0, %1 ; <<2 x i64>> [#uses=1] %3 = bitcast <2 x i64> %2 to <4 x i32> ; <<4 x i32>> [#uses=1] ret <4 x i32> %3 @@ -50,8 +50,8 @@ entry: ; SWIFT: vst1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+}} define void @t3(<4 x i32>* %r, <2 x i64>* %a, <2 x i64>* %b) nounwind { entry: - %0 = load <2 x i64>* %a, align 8 - %1 = load <2 x i64>* %b, align 8 + %0 = load <2 x i64>, <2 x i64>* %a, align 8 + %1 = load <2 x i64>, <2 x i64>* %b, align 8 %2 = add <2 x i64> %0, %1 %3 = bitcast <2 x i64> %2 to <4 x i32> store <4 x i32> %3, <4 x i32>* %r, align 8 |