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| author | Bob Wilson <bob.wilson@apple.com> | 2009-12-18 01:03:29 +0000 |
|---|---|---|
| committer | Bob Wilson <bob.wilson@apple.com> | 2009-12-18 01:03:29 +0000 |
| commit | 5afffaed5c0095930020947322633f0d0b02ffed (patch) | |
| tree | 0fd14078c6a45f2d5fabd542e121e759cf9c2303 /test/CodeGen/ARM/inlineasm3.ll | |
| parent | f042396b0f01d3cb7aeacef433f0b0c2cc138878 (diff) | |
Handle ARM inline asm "w" constraints with 64-bit ("d") registers.
The change in SelectionDAGBuilder is needed to allow using bitcasts to convert
between f64 (the default type for ARM "d" registers) and 64-bit Neon vector
types. Radar 7457110.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91649 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM/inlineasm3.ll')
| -rw-r--r-- | test/CodeGen/ARM/inlineasm3.ll | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/test/CodeGen/ARM/inlineasm3.ll b/test/CodeGen/ARM/inlineasm3.ll index 5ebf2fb94cc..f0627728e53 100644 --- a/test/CodeGen/ARM/inlineasm3.ll +++ b/test/CodeGen/ARM/inlineasm3.ll @@ -1,5 +1,6 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; Radar 7449043 %struct.int32x4_t = type { <4 x i32> } define arm_apcscc void @t() nounwind { @@ -11,3 +12,14 @@ entry: call void asm sideeffect "vmov.I64 q15, #0\0Avmov.32 d30[0], $1\0Avmov ${0:q}, q15\0A", "=*w,r,~{d31},~{d30}"(%struct.int32x4_t* %tmp, i32 8192) nounwind ret void } + +; Radar 7457110 +%struct.int32x2_t = type { <4 x i32> } + +define arm_apcscc void @t2() nounwind { +entry: +; CHECK: vmov d30, d0 +; CHECK: vmov.32 r0, d30[0] + %asmtmp2 = tail call i32 asm sideeffect "vmov d30, $1\0Avmov.32 $0, d30[0]\0A", "=r,w,~{d30}"(<2 x i32> undef) nounwind + ret void +} |