diff options
| author | Rafael Espindola <rafael.espindola@gmail.com> | 2013-05-30 20:37:52 +0000 |
|---|---|---|
| committer | Rafael Espindola <rafael.espindola@gmail.com> | 2013-05-30 20:37:52 +0000 |
| commit | 9e3e730417ec806f5a671e23d762795e550d0930 (patch) | |
| tree | bce18be2934b79b6f9057479f7e907f8a2a06c17 /test/CodeGen/ARM/fast-isel-vararg.ll | |
| parent | 198f972077e0756f533732ceb7cb1bc12fc29a3d (diff) | |
Revert r182937 and r182877.
r182877 broke MCJIT tests on ARM and r182937 was working around another failure
by r182877.
This should make the ARM bots green.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182960 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM/fast-isel-vararg.ll')
| -rw-r--r-- | test/CodeGen/ARM/fast-isel-vararg.ll | 47 |
1 files changed, 0 insertions, 47 deletions
diff --git a/test/CodeGen/ARM/fast-isel-vararg.ll b/test/CodeGen/ARM/fast-isel-vararg.ll deleted file mode 100644 index 0b7b0bd1c6f..00000000000 --- a/test/CodeGen/ARM/fast-isel-vararg.ll +++ /dev/null @@ -1,47 +0,0 @@ -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB - -define i32 @VarArg() nounwind { -entry: - %i = alloca i32, align 4 - %j = alloca i32, align 4 - %k = alloca i32, align 4 - %m = alloca i32, align 4 - %n = alloca i32, align 4 - %tmp = alloca i32, align 4 - %0 = load i32* %i, align 4 - %1 = load i32* %j, align 4 - %2 = load i32* %k, align 4 - %3 = load i32* %m, align 4 - %4 = load i32* %n, align 4 -; ARM: VarArg -; ARM: mov [[FP:r[0-9]+]], sp -; ARM: sub sp, sp, #32 -; ARM: movw r0, #5 -; ARM: ldr r1, {{\[}}[[FP]], #-4] -; ARM: ldr r2, {{\[}}[[FP]], #-8] -; ARM: ldr r3, {{\[}}[[FP]], #-12] -; ARM: ldr [[Ra:r[0-9]+]], [sp, #16] -; ARM: ldr [[Rb:[lr]+[0-9]*]], [sp, #12] -; ARM: str [[Ra]], [sp] -; ARM: str [[Rb]], [sp, #4] -; ARM: bl {{_?CallVariadic}} -; THUMB: sub sp, #32 -; THUMB: movs r0, #5 -; THUMB: movt r0, #0 -; THUMB: ldr r1, [sp, #28] -; THUMB: ldr r2, [sp, #24] -; THUMB: ldr r3, [sp, #20] -; THUMB: ldr.w {{[a-z0-9]+}}, [sp, #16] -; THUMB: ldr.w {{[a-z0-9]+}}, [sp, #12] -; THUMB: str.w {{[a-z0-9]+}}, [sp] -; THUMB: str.w {{[a-z0-9]+}}, [sp, #4] -; THUMB: bl {{_?}}CallVariadic - %call = call i32 (i32, ...)* @CallVariadic(i32 5, i32 %0, i32 %1, i32 %2, i32 %3, i32 %4) - store i32 %call, i32* %tmp, align 4 - %5 = load i32* %tmp, align 4 - ret i32 %5 -} - -declare i32 @CallVariadic(i32, ...) |