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| author | Kristof Beyls <kristof.beyls@arm.com> | 2017-06-28 07:07:03 +0000 |
|---|---|---|
| committer | Kristof Beyls <kristof.beyls@arm.com> | 2017-06-28 07:07:03 +0000 |
| commit | f41c3c9239734af0a6c543430ea4ffd2dfe736cb (patch) | |
| tree | 6d9b1a7c9a0d1534eba5b16c62767766b85fcb86 /test/CodeGen/ARM/cortexr52-misched-basic.ll | |
| parent | 61e059d1711dccc3dfedf005471a653743f13c34 (diff) | |
[ARM] Make -mcpu=generic schedule for an in-order core (Cortex-A8).
The benchmarking summarized in
http://lists.llvm.org/pipermail/llvm-dev/2017-May/113525.html showed
this is beneficial for a wide range of cores.
As is to be expected, quite a few small adaptations are needed to the
regressions tests, as the difference in scheduling results in:
- Quite a few small instruction schedule differences.
- A few changes in register allocation decisions caused by different
instruction schedules.
- A few changes in IfConversion decisions, due to a difference in
instruction schedule and/or the estimated cost of a branch mispredict.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306514 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM/cortexr52-misched-basic.ll')
| -rw-r--r-- | test/CodeGen/ARM/cortexr52-misched-basic.ll | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/test/CodeGen/ARM/cortexr52-misched-basic.ll b/test/CodeGen/ARM/cortexr52-misched-basic.ll index eb2c29a3a5d..614157eb0e1 100644 --- a/test/CodeGen/ARM/cortexr52-misched-basic.ll +++ b/test/CodeGen/ARM/cortexr52-misched-basic.ll @@ -12,10 +12,10 @@ ; GENERIC: Latency : 1 ; R52_SCHED: Latency : 3 ; CHECK: MLA -; GENERIC: Latency : 1 +; GENERIC: Latency : 2 ; R52_SCHED: Latency : 4 ; CHECK: SDIV -; GENERIC: Latency : 1 +; GENERIC: Latency : 0 ; R52_SCHED: Latency : 8 ; CHECK: ** Final schedule for BB#0 *** ; GENERIC: EORrr |