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| author | Francis Visoiu Mistrih <francisvm@yahoo.com> | 2017-12-04 17:18:51 +0000 |
|---|---|---|
| committer | Francis Visoiu Mistrih <francisvm@yahoo.com> | 2017-12-04 17:18:51 +0000 |
| commit | ca0df55065b11f2310f55c731b2f990d09ae1c32 (patch) | |
| tree | fff52bf80df56346069e50ec52b17a4e36907e87 /test/CodeGen/ARM/cortexr52-misched-basic.ll | |
| parent | 93356784e0e357e3f1f74d565480cc9c25ea4bc9 (diff) | |
[CodeGen] Unify MBB reference format in both MIR and debug output
As part of the unification of the debug format and the MIR format, print
MBB references as '%bb.5'.
The MIR printer prints the IR name of a MBB only for block definitions.
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g'
* find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g'
* grep -nr 'BB#' and fix
Differential Revision: https://reviews.llvm.org/D40422
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319665 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM/cortexr52-misched-basic.ll')
| -rw-r--r-- | test/CodeGen/ARM/cortexr52-misched-basic.ll | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/test/CodeGen/ARM/cortexr52-misched-basic.ll b/test/CodeGen/ARM/cortexr52-misched-basic.ll index 614157eb0e1..0edc6653a03 100644 --- a/test/CodeGen/ARM/cortexr52-misched-basic.ll +++ b/test/CodeGen/ARM/cortexr52-misched-basic.ll @@ -7,7 +7,7 @@ ; as div takes more cycles to compute than eor. ; ; CHECK: ********** MI Scheduling ********** -; CHECK: foo:BB#0 entry +; CHECK: foo:%bb.0 entry ; CHECK: EORrr ; GENERIC: Latency : 1 ; R52_SCHED: Latency : 3 @@ -17,7 +17,7 @@ ; CHECK: SDIV ; GENERIC: Latency : 0 ; R52_SCHED: Latency : 8 -; CHECK: ** Final schedule for BB#0 *** +; CHECK: ** Final schedule for %bb.0 *** ; GENERIC: EORrr ; GENERIC: SDIV ; R52_SCHED: SDIV |