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| author | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2015-02-05 01:52:19 +0000 |
|---|---|---|
| committer | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2015-02-05 01:52:19 +0000 |
| commit | a7f2cf45f35f6a98a3e8e252d379e7023b48ba04 (patch) | |
| tree | 722a7f022720c1806d763a97c7f494d2d8276b2d /test/CodeGen/ARM/big-endian-neon-extend.ll | |
| parent | 42ec3433ef75364da735ac0d591f50c71c3eded5 (diff) | |
[ARM] Use patterns instead of hardcoded regs in test. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228259 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM/big-endian-neon-extend.ll')
| -rw-r--r-- | test/CodeGen/ARM/big-endian-neon-extend.ll | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/test/CodeGen/ARM/big-endian-neon-extend.ll b/test/CodeGen/ARM/big-endian-neon-extend.ll index fd3016da509..1498356eb97 100644 --- a/test/CodeGen/ARM/big-endian-neon-extend.ll +++ b/test/CodeGen/ARM/big-endian-neon-extend.ll @@ -12,7 +12,7 @@ define void @vector_ext_2i8_to_2i64( <2 x i8>* %loadaddr, <2 x i64>* %storeaddr ; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]] ; CHECK-NEXT: vand [[QREG]], [[QREG]], [[MASK]] ; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]] -; CHECK-NEXT: vst1.64 {[[REG]], d17}, [r1] +; CHECK-NEXT: vst1.64 {[[REG]], {{d[0-9]+}}}, [r1] ; CHECK-NEXT: bx lr %1 = load <2 x i8>* %loadaddr %2 = zext <2 x i8> %1 to <2 x i64> @@ -31,7 +31,7 @@ define void @vector_ext_2i16_to_2i64( <2 x i16>* %loadaddr, <2 x i64>* %storeadd ; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]] ; CHECK-NEXT: vand [[QREG]], [[QREG]], [[MASK]] ; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]] -; CHECK-NEXT: vst1.64 {[[REG]], d17}, [r1] +; CHECK-NEXT: vst1.64 {[[REG]], {{d[0-9]+}}}, [r1] ; CHECK-NEXT: bx lr %1 = load <2 x i16>* %loadaddr %2 = zext <2 x i16> %1 to <2 x i64> @@ -76,8 +76,8 @@ define void @vector_ext_2i8_to_2i16( <2 x i8>* %loadaddr, <2 x i16>* %storeaddr ; CHECK-NEXT: vmovl.u8 [[QREG:q[0-9]+]], [[REG]] ; CHECK-NEXT: vmovl.u16 [[QREG]], [[REG]] ; CHECK-NEXT: vrev32.16 [[REG]], [[REG]] -; CHECK-NEXT: vuzp.16 [[REG]], d17 -; CHECK-NEXT: vrev32.16 [[REG]], d17 +; CHECK-NEXT: vuzp.16 [[REG]], {{d[0-9]+}} +; CHECK-NEXT: vrev32.16 [[REG]], {{d[0-9]+}} ; CHECK-NEXT: vst1.32 {[[REG]][0]}, [r1:32] ; CHECK-NEXT: bx lr %1 = load <2 x i8>* %loadaddr @@ -93,7 +93,7 @@ define void @vector_ext_4i8_to_4i32( <4 x i8>* %loadaddr, <4 x i32>* %storeaddr ; CHECK-NEXT: vmovl.u8 [[QREG:q[0-9]+]], [[REG]] ; CHECK-NEXT: vmovl.u16 [[QREG]], [[REG]] ; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]] -; CHECK-NEXT: vst1.64 {[[REG]], d17}, [r1] +; CHECK-NEXT: vst1.64 {[[REG]], {{d[0-9]+}}}, [r1] ; CHECK-NEXT: bx lr %1 = load <4 x i8>* %loadaddr %2 = zext <4 x i8> %1 to <4 x i32> |