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| author | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2015-03-05 19:37:53 +0000 |
|---|---|---|
| committer | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2015-03-05 19:37:53 +0000 |
| commit | 67297cd9563d6385570be219098faf8d0fe4c0de (patch) | |
| tree | 9417170ce30b46f8ef002cf04af6cdc6fe2ff9fd /test/CodeGen/ARM/big-endian-neon-extend.ll | |
| parent | 387cf215c00f72212b5b088803c71147f9025ff6 (diff) | |
[ARM] Enable vector extload combine for legal types.
This commit enables forming vector extloads for ARM.
It only does so for legal types, and when we can't fold the extension
in a wide/long form of the user instruction.
Enabling it for larger types isn't as good an idea on ARM as it is on
X86, because:
- we pretend that extloads are legal, but end up generating vld+vmov
- we have instructions like vld {dN, dM}, which can't be generated
when we "manually expand" extloads to vld+vmov.
For legal types, the combine doesn't fire that often: in the
integration tests only in a big endian testcase, where it removes a
pointless AND.
Related to rdar://19723053
Differential Revision: http://reviews.llvm.org/D7423
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231396 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM/big-endian-neon-extend.ll')
| -rw-r--r-- | test/CodeGen/ARM/big-endian-neon-extend.ll | 10 |
1 files changed, 0 insertions, 10 deletions
diff --git a/test/CodeGen/ARM/big-endian-neon-extend.ll b/test/CodeGen/ARM/big-endian-neon-extend.ll index 1e35305bdba..f8542b708b8 100644 --- a/test/CodeGen/ARM/big-endian-neon-extend.ll +++ b/test/CodeGen/ARM/big-endian-neon-extend.ll @@ -3,15 +3,10 @@ define void @vector_ext_2i8_to_2i64( <2 x i8>* %loadaddr, <2 x i64>* %storeaddr ) { ; CHECK-LABEL: vector_ext_2i8_to_2i64: ; CHECK: vld1.16 {[[REG:d[0-9]+]][0]}, [r0:16] -; CHECK-NEXT: vmov.i64 [[MASK:q[0-9]+]], #0xff -; CHECK-NEXT: vrev64.32 [[MASK]], [[MASK]] ; CHECK-NEXT: vrev16.8 [[REG]], [[REG]] ; CHECK-NEXT: vmovl.u8 [[QREG:q[0-9]+]], [[REG]] ; CHECK-NEXT: vmovl.u16 [[QREG]], [[REG]] ; CHECK-NEXT: vmovl.u32 [[QREG]], [[REG]] -; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]] -; CHECK-NEXT: vand [[QREG]], [[QREG]], [[MASK]] -; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]] ; CHECK-NEXT: vst1.64 {[[REG]], {{d[0-9]+}}}, [r1] ; CHECK-NEXT: bx lr %1 = load <2 x i8>, <2 x i8>* %loadaddr @@ -23,14 +18,9 @@ define void @vector_ext_2i8_to_2i64( <2 x i8>* %loadaddr, <2 x i64>* %storeaddr define void @vector_ext_2i16_to_2i64( <2 x i16>* %loadaddr, <2 x i64>* %storeaddr ) { ; CHECK-LABEL: vector_ext_2i16_to_2i64: ; CHECK: vld1.32 {[[REG:d[0-9]+]][0]}, [r0:32] -; CHECK-NEXT: vmov.i64 [[MASK:q[0-9]+]], #0xffff -; CHECK-NEXT: vrev64.32 [[MASK]], [[MASK]] ; CHECK-NEXT: vrev32.16 [[REG]], [[REG]] ; CHECK-NEXT: vmovl.u16 [[QREG:q[0-9]+]], [[REG]] ; CHECK-NEXT: vmovl.u32 [[QREG]], [[REG]] -; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]] -; CHECK-NEXT: vand [[QREG]], [[QREG]], [[MASK]] -; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]] ; CHECK-NEXT: vst1.64 {[[REG]], {{d[0-9]+}}}, [r1] ; CHECK-NEXT: bx lr %1 = load <2 x i16>, <2 x i16>* %loadaddr |