diff options
author | Tim Northover <tnorthover@apple.com> | 2013-07-03 09:20:36 +0000 |
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committer | Tim Northover <tnorthover@apple.com> | 2013-07-03 09:20:36 +0000 |
commit | a10c01a6c62792be825c562314a646437b21bfec (patch) | |
tree | 63c3600a8c347945f32732f94407ed65a2734404 /test/CodeGen/ARM/atomic-load-store.ll | |
parent | b997b56383a99f739d7e2aa14e6945fea477e597 (diff) |
ARM: relax the atomic release barrier to "dmb ishst" on Swift
Swift cores implement store barriers that are stronger than the ARM
specification but weaker than general barriers. They are, in fact, just about
enough to provide the ordering needed for atomic operations with release
semantics.
This patch makes use of that quirk.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185527 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM/atomic-load-store.ll')
-rw-r--r-- | test/CodeGen/ARM/atomic-load-store.ll | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/test/CodeGen/ARM/atomic-load-store.ll b/test/CodeGen/ARM/atomic-load-store.ll index 66916a7c2e2..476b3ddd45d 100644 --- a/test/CodeGen/ARM/atomic-load-store.ll +++ b/test/CodeGen/ARM/atomic-load-store.ll @@ -6,15 +6,15 @@ define void @test1(i32* %ptr, i32 %val1) { ; ARM: test1 -; ARM: dmb ish +; ARM: dmb {{ish$}} ; ARM-NEXT: str -; ARM-NEXT: dmb ish +; ARM-NEXT: dmb {{ish$}} ; THUMBONE: test1 ; THUMBONE: __sync_lock_test_and_set_4 ; THUMBTWO: test1 -; THUMBTWO: dmb ish +; THUMBTWO: dmb {{ish$}} ; THUMBTWO-NEXT: str -; THUMBTWO-NEXT: dmb ish +; THUMBTWO-NEXT: dmb {{ish$}} store atomic i32 %val1, i32* %ptr seq_cst, align 4 ret void } @@ -22,12 +22,12 @@ define void @test1(i32* %ptr, i32 %val1) { define i32 @test2(i32* %ptr) { ; ARM: test2 ; ARM: ldr -; ARM-NEXT: dmb ish +; ARM-NEXT: dmb {{ish$}} ; THUMBONE: test2 ; THUMBONE: __sync_val_compare_and_swap_4 ; THUMBTWO: test2 ; THUMBTWO: ldr -; THUMBTWO-NEXT: dmb ish +; THUMBTWO-NEXT: dmb {{ish$}} %val = load atomic i32* %ptr seq_cst, align 4 ret i32 %val } |