diff options
author | Robin Morisset <morisset@google.com> | 2014-09-17 17:41:16 +0000 |
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committer | Robin Morisset <morisset@google.com> | 2014-09-17 17:41:16 +0000 |
commit | 30486fa3de6f33bd5f537fd9d0a8611d2fd7052a (patch) | |
tree | d1272ff628c1d9a6cbae806d0523bd1fecc995ab /test/CodeGen/ARM/atomic-load-store.ll | |
parent | 507636288f9377961023be02ff1cfa1e21565e09 (diff) |
[ARM, Fix] Fix emitLeading/TrailingFence on old ARM processors
Summary:
I had only tested this code for ARMv7 and ARMv8. This patch adds several
fallback paths if the processor does not support dmb ish:
- dmb sy if a cortex-M with support for dmb
- mcr p15, #0, r0, c7, c10, #5 for ARMv6 (special instruction equivalent to a DMB)
These fallback paths were chosen based on the code for fence seq_cst.
Thanks to luqmana for having noticed this bug.
Test Plan: Added more cases to atomic-load-store.ll + make check-all
Reviewers: jfb, t.p.northover, luqmana
Subscribers: aemerson, llvm-commits
Differential Revision: http://reviews.llvm.org/D5304
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217965 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM/atomic-load-store.ll')
-rw-r--r-- | test/CodeGen/ARM/atomic-load-store.ll | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/test/CodeGen/ARM/atomic-load-store.ll b/test/CodeGen/ARM/atomic-load-store.ll index 49342d2d1bf..af13dfc80d2 100644 --- a/test/CodeGen/ARM/atomic-load-store.ll +++ b/test/CodeGen/ARM/atomic-load-store.ll @@ -3,6 +3,8 @@ ; RUN: llc < %s -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s -check-prefix=THUMBTWO ; RUN: llc < %s -mtriple=thumbv6-apple-ios | FileCheck %s -check-prefix=THUMBONE ; RUN: llc < %s -mtriple=armv4-apple-ios | FileCheck %s -check-prefix=ARMV4 +; RUN: llc < %s -mtriple=armv6-apple-ios | FileCheck %s -check-prefix=ARMV6 +; RUN: llc < %s -mtriple=thumbv7m-apple-ios | FileCheck %s -check-prefix=THUMBM define void @test1(i32* %ptr, i32 %val1) { ; ARM-LABEL: test1 @@ -15,6 +17,14 @@ define void @test1(i32* %ptr, i32 %val1) { ; THUMBTWO: dmb {{ish$}} ; THUMBTWO-NEXT: str ; THUMBTWO-NEXT: dmb {{ish$}} +; ARMV6-LABEL: test1 +; ARMV6: mcr p15, #0, {{r[0-9]*}}, c7, c10, #5 +; ARMV6: str +; ARMV6: mcr p15, #0, {{r[0-9]*}}, c7, c10, #5 +; THUMBM-LABEL: test1 +; THUMBM: dmb sy +; THUMBM: str +; THUMBM: dmb sy store atomic i32 %val1, i32* %ptr seq_cst, align 4 ret void } @@ -28,6 +38,12 @@ define i32 @test2(i32* %ptr) { ; THUMBTWO-LABEL: test2 ; THUMBTWO: ldr ; THUMBTWO-NEXT: dmb {{ish$}} +; ARMV6-LABEL: test2 +; ARMV6: ldr +; ARMV6: mcr p15, #0, {{r[0-9]*}}, c7, c10, #5 +; THUMBM-LABEL: test2 +; THUMBM: ldr +; THUMBM: dmb sy %val = load atomic i32* %ptr seq_cst, align 4 ret i32 %val } @@ -55,6 +71,11 @@ define void @test3(i8* %ptr1, i8* %ptr2) { ; THUMBONE-NOT: dmb ; THUMBONE: strb ; THUMBONE-NOT: dmb + +; ARMV6-LABEL: test3 +; ARMV6-NOT: mcr +; THUMBM-LABEL: test3 +; THUMBM-NOT: dmb sy %val = load atomic i8* %ptr1 unordered, align 1 store atomic i8 %val, i8* %ptr2 unordered, align 1 ret void @@ -64,6 +85,8 @@ define void @test4(i8* %ptr1, i8* %ptr2) { ; THUMBONE-LABEL: test4 ; THUMBONE: ___sync_val_compare_and_swap_1 ; THUMBONE: ___sync_lock_test_and_set_1 +; ARMV6-LABEL: test4 +; THUMBM-LABEL: test4 %val = load atomic i8* %ptr1 seq_cst, align 1 store atomic i8 %val, i8* %ptr2 seq_cst, align 1 ret void |