diff options
| author | Hans Wennborg <hans@hanshq.net> | 2018-01-24 15:33:33 +0000 |
|---|---|---|
| committer | Hans Wennborg <hans@hanshq.net> | 2018-01-24 15:33:33 +0000 |
| commit | d8c108c8d0c90508261ec8c7688993c0f23583f5 (patch) | |
| tree | 4c33363a78112fb8279b3ca678a58527061ff433 /test/CodeGen/ARM/atomic-cmpxchg.ll | |
| parent | d952162cf65354b6f918b511746b44e2b8921536 (diff) | |
Merging r322372 and r322767:
------------------------------------------------------------------------
r322372 | nemanjai | 2018-01-12 15:58:41 +0100 (Fri, 12 Jan 2018) | 10 lines
[PowerPC] Zero-extend the compare operand for ATOMIC_CMP_SWAP
Part of the fix for https://bugs.llvm.org/show_bug.cgi?id=35812.
This patch ensures that the compare operand for the atomic compare and swap
is properly zero-extended to 32 bits if applicable.
A follow-up commit will fix the extension for the SETCC node generated when
expanding an ATOMIC_CMP_SWAP_WITH_SUCCESS. That will complete the bug fix.
Differential Revision: https://reviews.llvm.org/D41856
------------------------------------------------------------------------
------------------------------------------------------------------------
r322767 | efriedma | 2018-01-17 23:04:36 +0100 (Wed, 17 Jan 2018) | 12 lines
[LegalizeDAG] Fix ATOMIC_CMP_SWAP_WITH_SUCCESS legalization.
The code wasn't zero-extending correctly, so the comparison could
spuriously fail.
Adds some AArch64 tests to cover this case.
Inspired by D41791.
Differential Revision: https://reviews.llvm.org/D41798
------------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@323334 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM/atomic-cmpxchg.ll')
| -rw-r--r-- | test/CodeGen/ARM/atomic-cmpxchg.ll | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/test/CodeGen/ARM/atomic-cmpxchg.ll b/test/CodeGen/ARM/atomic-cmpxchg.ll index a136e44fc19..fec11667708 100644 --- a/test/CodeGen/ARM/atomic-cmpxchg.ll +++ b/test/CodeGen/ARM/atomic-cmpxchg.ll @@ -49,9 +49,10 @@ entry: ; CHECK-THUMBV6: mov [[EXPECTED:r[0-9]+]], r1 ; CHECK-THUMBV6-NEXT: bl __sync_val_compare_and_swap_1 ; CHECK-THUMBV6-NEXT: mov [[RES:r[0-9]+]], r0 +; CHECK-THUMBV6-NEXT: uxtb [[EXPECTED_ZEXT:r[0-9]+]], [[EXPECTED]] ; CHECK-THUMBV6-NEXT: movs r0, #1 ; CHECK-THUMBV6-NEXT: movs [[ZERO:r[0-9]+]], #0 -; CHECK-THUMBV6-NEXT: cmp [[RES]], [[EXPECTED]] +; CHECK-THUMBV6-NEXT: cmp [[RES]], [[EXPECTED_ZEXT]] ; CHECK-THUMBV6-NEXT: beq [[END:.LBB[0-9_]+]] ; CHECK-THUMBV6-NEXT: mov r0, [[ZERO]] ; CHECK-THUMBV6-NEXT: [[END]]: |