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authorJim Grosbach <grosbach@apple.com>2011-11-14 23:03:21 +0000
committerJim Grosbach <grosbach@apple.com>2011-11-14 23:03:21 +0000
commitffc658b056b7cc0b3f6a2626694b6a4216ed728d (patch)
treeebe680a03750316ed3c572177cd1306a4c0fd173 /test/CodeGen/ARM/2011-10-26-memset-with-neon.ll
parent88990248d3bfb2f265fcf27f8a032ac0eb14d09f (diff)
ARM VLDR/VSTR instructions don't need a size suffix.
Canonicallize on the non-suffixed form, but continue to accept assembly that has any correctly sized type suffix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144583 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM/2011-10-26-memset-with-neon.ll')
-rw-r--r--test/CodeGen/ARM/2011-10-26-memset-with-neon.ll2
1 files changed, 1 insertions, 1 deletions
diff --git a/test/CodeGen/ARM/2011-10-26-memset-with-neon.ll b/test/CodeGen/ARM/2011-10-26-memset-with-neon.ll
index 3c9216cde7b..42b14914814 100644
--- a/test/CodeGen/ARM/2011-10-26-memset-with-neon.ll
+++ b/test/CodeGen/ARM/2011-10-26-memset-with-neon.ll
@@ -1,7 +1,7 @@
; RUN: llc -march=arm -mcpu=cortex-a8 < %s | FileCheck %s
; Should trigger a NEON store.
-; CHECK: vstr.64
+; CHECK: vstr
define void @f_0_12(i8* nocapture %c) nounwind optsize {
entry:
call void @llvm.memset.p0i8.i64(i8* %c, i8 0, i64 12, i32 8, i1 false)