diff options
| author | Francis Visoiu Mistrih <francisvm@yahoo.com> | 2017-11-30 16:12:24 +0000 |
|---|---|---|
| committer | Francis Visoiu Mistrih <francisvm@yahoo.com> | 2017-11-30 16:12:24 +0000 |
| commit | e6b89910eb5c0a89e5bbdd8ceb3b6394efe6dabc (patch) | |
| tree | 2888ae660f4d6f45df7a663e14a0187a37679326 /test/CodeGen/AMDGPU | |
| parent | 4a8c2b625b7ed7d95e349cdd45ff6a3df0771bc5 (diff) | |
[CodeGen] Always use `printReg` to print registers in both MIR and debug
output
As part of the unification of the debug format and the MIR format,
always use `printReg` to print all kinds of registers.
Updated the tests using '_' instead of '%noreg' until we decide which
one we want to be the default one.
Differential Revision: https://reviews.llvm.org/D40421
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319445 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/AMDGPU')
| -rw-r--r-- | test/CodeGen/AMDGPU/fadd.ll | 2 | ||||
| -rw-r--r-- | test/CodeGen/AMDGPU/inserted-wait-states.mir | 2 | ||||
| -rw-r--r-- | test/CodeGen/AMDGPU/promote-alloca-to-lds-select.ll | 2 | ||||
| -rw-r--r-- | test/CodeGen/AMDGPU/regcoalesce-dbg.mir | 2 |
4 files changed, 4 insertions, 4 deletions
diff --git a/test/CodeGen/AMDGPU/fadd.ll b/test/CodeGen/AMDGPU/fadd.ll index 621a0de281d..a2f1f7195f2 100644 --- a/test/CodeGen/AMDGPU/fadd.ll +++ b/test/CodeGen/AMDGPU/fadd.ll @@ -72,4 +72,4 @@ define amdgpu_kernel void @fadd_0_nsz_attr_f32(float addrspace(1)* %out, float % } attributes #0 = { nounwind } -attributes #1 = { nounwind "no-signed-zeros-fp-math"="true" }
\ No newline at end of file +attributes #1 = { nounwind "no-signed-zeros-fp-math"="true" } diff --git a/test/CodeGen/AMDGPU/inserted-wait-states.mir b/test/CodeGen/AMDGPU/inserted-wait-states.mir index 16d9070849b..698f2c3ebc4 100644 --- a/test/CodeGen/AMDGPU/inserted-wait-states.mir +++ b/test/CodeGen/AMDGPU/inserted-wait-states.mir @@ -548,7 +548,7 @@ body: | %flat_scr_lo = S_ADD_U32 %sgpr6, %sgpr9, implicit-def %scc %flat_scr_hi = S_ADDC_U32 %sgpr7, 0, implicit-def %scc, implicit %scc - DBG_VALUE _, 2, !5, !11, debug-location !12 + DBG_VALUE %noreg, 2, !5, !11, debug-location !12 %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr4_sgpr5, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`) dead %sgpr6_sgpr7 = KILL %sgpr4_sgpr5 %sgpr8 = S_MOV_B32 %sgpr5 diff --git a/test/CodeGen/AMDGPU/promote-alloca-to-lds-select.ll b/test/CodeGen/AMDGPU/promote-alloca-to-lds-select.ll index 55c2229fb6b..ebeed0dd443 100644 --- a/test/CodeGen/AMDGPU/promote-alloca-to-lds-select.ll +++ b/test/CodeGen/AMDGPU/promote-alloca-to-lds-select.ll @@ -130,4 +130,4 @@ bb: } attributes #0 = { norecurse nounwind "amdgpu-waves-per-eu"="1,1" } -attributes #1 = { norecurse nounwind }
\ No newline at end of file +attributes #1 = { norecurse nounwind } diff --git a/test/CodeGen/AMDGPU/regcoalesce-dbg.mir b/test/CodeGen/AMDGPU/regcoalesce-dbg.mir index c5a9a0ad01a..69538d8b738 100644 --- a/test/CodeGen/AMDGPU/regcoalesce-dbg.mir +++ b/test/CodeGen/AMDGPU/regcoalesce-dbg.mir @@ -63,7 +63,7 @@ body: | %19.sub1 = COPY killed %18 %10 = S_MOV_B32 61440 %11 = S_MOV_B32 0 - DBG_VALUE debug-use %11, debug-use _, !1, !8, debug-location !9 + DBG_VALUE debug-use %11, debug-use %noreg, !1, !8, debug-location !9 undef %12.sub0 = COPY killed %11 %12.sub1 = COPY killed %10 undef %13.sub0_sub1 = COPY killed %4 |