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author | Tom Stellard <thomas.stellard@amd.com> | 2015-06-13 03:28:10 +0000 |
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committer | Tom Stellard <thomas.stellard@amd.com> | 2015-06-13 03:28:10 +0000 |
commit | 953c6814730951ad9a286d7991e9c8c481433d45 (patch) | |
tree | 18ceb605903abc4d40e124137fe5d2d3744c44af /test/CodeGen/AMDGPU/reciprocal.ll | |
parent | 8b8b72ef03c3c7f28ab9f38c462e95046e7a677a (diff) |
R600 -> AMDGPU rename
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239657 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/AMDGPU/reciprocal.ll')
-rw-r--r-- | test/CodeGen/AMDGPU/reciprocal.ll | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/test/CodeGen/AMDGPU/reciprocal.ll b/test/CodeGen/AMDGPU/reciprocal.ll new file mode 100644 index 00000000000..b4ac47afced --- /dev/null +++ b/test/CodeGen/AMDGPU/reciprocal.ll @@ -0,0 +1,15 @@ +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +;CHECK: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} + +define void @test(<4 x float> inreg %reg0) #0 { + %r0 = extractelement <4 x float> %reg0, i32 0 + %r1 = fdiv float 1.0, %r0 + %vec = insertelement <4 x float> undef, float %r1, i32 0 + call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0) + ret void +} + +declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) + +attributes #0 = { "ShaderType"="0" } |