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authorSimon Pilgrim <llvm-dev@redking.me.uk>2017-12-26 23:27:44 +0000
committerSimon Pilgrim <llvm-dev@redking.me.uk>2017-12-26 23:27:44 +0000
commitff53894326094f71ebf99785d4d6dce30cb089a6 (patch)
tree2cadbe1d9004643e957b8d338aa63415c713c20d /test/CodeGen/AArch64
parent4ad2702a08e320335007ea37f68e477b0b426c15 (diff)
[DAGCombine] visitANDLike - ensure APInt is is in range for getSExtValue/getZExtValue
Reduced from oss-fuzz #4782 test case git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321464 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/AArch64')
-rw-r--r--test/CodeGen/AArch64/combine-and-like.ll13
1 files changed, 13 insertions, 0 deletions
diff --git a/test/CodeGen/AArch64/combine-and-like.ll b/test/CodeGen/AArch64/combine-and-like.ll
new file mode 100644
index 00000000000..15770c2e02f
--- /dev/null
+++ b/test/CodeGen/AArch64/combine-and-like.ll
@@ -0,0 +1,13 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s
+
+define i32 @f(i32 %a0) {
+; CHECK-LABEL: f:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w0, wzr
+; CHECK-NEXT: ret
+ %1 = lshr i32 %a0, 2147483647
+ %2 = add i32 %1, 2147483647
+ %3 = and i32 %2, %1
+ ret i32 %3
+}