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| author | Florian Hahn <florian.hahn@arm.com> | 2017-12-06 22:48:36 +0000 |
|---|---|---|
| committer | Florian Hahn <florian.hahn@arm.com> | 2017-12-06 22:48:36 +0000 |
| commit | f42965e37eedda03623bf9df15b5f2894c173f1f (patch) | |
| tree | 3c38e3ce11c2daa0da56704ab5a400cd07fd705c /test/CodeGen/AArch64 | |
| parent | d62c5bdaf9003c3a927cc561562dcaf9f3872fcd (diff) | |
[AArch64] Add patterns to replace fsub fmul with fma fneg.
Summary:
This patch adds MachineCombiner patterns for transforming
(fsub (fmul x y) z) into (fma x y (fneg z)). This has a lower
latency on micro architectures where fneg is cheap.
Patch based on work by George Steed.
Reviewers: rengolin, joelkevinjones, joel_k_jones, evandro, efriedma
Reviewed By: evandro
Subscribers: aemerson, javed.absar, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D40306
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319980 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/AArch64')
| -rw-r--r-- | test/CodeGen/AArch64/aarch64-combine-fmul-fsub.mir | 82 |
1 files changed, 82 insertions, 0 deletions
diff --git a/test/CodeGen/AArch64/aarch64-combine-fmul-fsub.mir b/test/CodeGen/AArch64/aarch64-combine-fmul-fsub.mir new file mode 100644 index 00000000000..630b3402816 --- /dev/null +++ b/test/CodeGen/AArch64/aarch64-combine-fmul-fsub.mir @@ -0,0 +1,82 @@ +# RUN: llc -run-pass=machine-combiner -o - -mtriple=aarch64-unknown-linux -mcpu=cortex-a57 -enable-unsafe-fp-math %s | FileCheck --check-prefix=UNPROFITABLE %s +# RUN: llc -run-pass=machine-combiner -o - -mtriple=aarch64-unknown-linux -mcpu=falkor -enable-unsafe-fp-math %s | FileCheck --check-prefix=PROFITABLE %s +# RUN: llc -run-pass=machine-combiner -o - -mtriple=aarch64-unknown-linux -mcpu=exynosm1 -enable-unsafe-fp-math %s | FileCheck --check-prefix=PROFITABLE %s +# RUN: llc -run-pass=machine-combiner -o - -mtriple=aarch64-unknown-linux -mcpu=thunderx2t99 -enable-unsafe-fp-math %s | FileCheck --check-prefix=PROFITABLE %s +# +name: f1_2s +registers: + - { id: 0, class: fpr64 } + - { id: 1, class: fpr64 } + - { id: 2, class: fpr64 } + - { id: 3, class: fpr64 } + - { id: 4, class: fpr64 } +body: | + bb.0.entry: + %2:fpr64 = COPY %d2 + %1:fpr64 = COPY %d1 + %0:fpr64 = COPY %d0 + %3:fpr64 = FMULv2f32 %0, %1 + %4:fpr64 = FSUBv2f32 killed %3, %2 + %d0 = COPY %4 + RET_ReallyLR implicit %d0 + +... +# UNPROFITABLE-LABEL: name: f1_2s +# UNPROFITABLE: %3:fpr64 = FMULv2f32 %0, %1 +# UNPROFITABLE-NEXT: FSUBv2f32 killed %3, %2 +# +# PROFITABLE-LABEL: name: f1_2s +# PROFITABLE: %5:fpr64 = FNEGv2f32 %2 +# PROFITABLE-NEXT: FMLAv2f32 killed %5, %0, %1 +--- +name: f1_4s +registers: + - { id: 0, class: fpr128 } + - { id: 1, class: fpr128 } + - { id: 2, class: fpr128 } + - { id: 3, class: fpr128 } + - { id: 4, class: fpr128 } +body: | + bb.0.entry: + %2:fpr128 = COPY %q2 + %1:fpr128 = COPY %q1 + %0:fpr128 = COPY %q0 + %3:fpr128 = FMULv4f32 %0, %1 + %4:fpr128 = FSUBv4f32 killed %3, %2 + %q0 = COPY %4 + RET_ReallyLR implicit %q0 + +... +# UNPROFITABLE-LABEL: name: f1_4s +# UNPROFITABLE: %3:fpr128 = FMULv4f32 %0, %1 +# UNPROFITABLE-NEXT: FSUBv4f32 killed %3, %2 +# +# PROFITABLE-LABEL: name: f1_4s +# PROFITABLE: %5:fpr128 = FNEGv4f32 %2 +# PROFITABLE-NEXT: FMLAv4f32 killed %5, %0, %1 +--- +name: f1_2d +registers: + - { id: 0, class: fpr128 } + - { id: 1, class: fpr128 } + - { id: 2, class: fpr128 } + - { id: 3, class: fpr128 } + - { id: 4, class: fpr128 } +body: | + bb.0.entry: + %2:fpr128 = COPY %q2 + %1:fpr128 = COPY %q1 + %0:fpr128 = COPY %q0 + %3:fpr128 = FMULv2f64 %0, %1 + %4:fpr128 = FSUBv2f64 killed %3, %2 + %q0 = COPY %4 + RET_ReallyLR implicit %q0 + +... +# UNPROFITABLE-LABEL: name: f1_2d +# UNPROFITABLE: %3:fpr128 = FMULv2f64 %0, %1 +# UNPROFITABLE-NEXT: FSUBv2f64 killed %3, %2 +# +# PROFITABLE-LABEL: name: f1_2d +# PROFITABLE: %5:fpr128 = FNEGv2f64 %2 +# PROFITABLE-NEXT: FMLAv2f64 killed %5, %0, %1 |