diff options
| author | Daniel Sanders <daniel_l_sanders@apple.com> | 2017-10-16 01:16:35 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel_l_sanders@apple.com> | 2017-10-16 01:16:35 +0000 |
| commit | 728d43b28f1412c8b6bee7e7ef6cec79b872078f (patch) | |
| tree | 4dfb14aae07590a0737864a5267df58fde4634e0 /test/CodeGen/AArch64 | |
| parent | 508747d41851c6a0dcd44b7e14b6e5de08634d73 (diff) | |
[globalisel][tblgen] Add support for iPTR and implement am_unscaled* and am_indexed*
Summary:
iPTR is a pointer of subtarget-specific size to any address space. Therefore
type checks on this size derive the SizeInBits from a subtarget hook.
At this point, we can import the simplests G_LOAD rules and select load
instructions using them. Further patches will support for the predicates to
enable additional loads as well as the stores.
Depends on D37457
Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar
Reviewed By: qcolombet
Subscribers: kristof.beyls, javed.absar, llvm-commits, igorb
Differential Revision: https://reviews.llvm.org/D37458
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315885 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/AArch64')
| -rw-r--r-- | test/CodeGen/AArch64/GlobalISel/select-load.mir | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/test/CodeGen/AArch64/GlobalISel/select-load.mir b/test/CodeGen/AArch64/GlobalISel/select-load.mir index 7e0c9d6ebc0..2955788a71e 100644 --- a/test/CodeGen/AArch64/GlobalISel/select-load.mir +++ b/test/CodeGen/AArch64/GlobalISel/select-load.mir @@ -1,9 +1,5 @@ # RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -# This patch temporarily causes LD1Onev1d to match instead of LDRDui on a -# couple functions. A patch to support iPTR will follow that fixes this. -# XFAIL: * - --- | target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" @@ -533,13 +529,13 @@ registers: # CHECK: body: # CHECK: %0 = COPY %x0 -# CHECK: %1 = LD1Onev2s %0 +# CHECK: %1 = LDRDui %0, 0 :: (load 8 from %ir.addr) # CHECK: %d0 = COPY %1 body: | bb.0: liveins: %x0 %0(p0) = COPY %x0 - %1(<2 x s32>) = G_LOAD %0 :: (load 4 from %ir.addr) + %1(<2 x s32>) = G_LOAD %0 :: (load 8 from %ir.addr) %d0 = COPY %1(<2 x s32>) ... |