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| author | Geoff Berry <gberry@codeaurora.org> | 2017-12-12 17:53:59 +0000 |
|---|---|---|
| committer | Geoff Berry <gberry@codeaurora.org> | 2017-12-12 17:53:59 +0000 |
| commit | 3b391fe80e65f144d9e2e31a09e24f00ac7bb230 (patch) | |
| tree | 2e73cc0bf11d06fa2c54f3d8b37e17a40fda4cf8 /test/CodeGen/AArch64 | |
| parent | 9cc4cf09cace7a496734dfcfb5fd3227290e6cdf (diff) | |
[MachineOperand][MIR] Add isRenamable to MachineOperand.
Summary:
Add isRenamable() predicate to MachineOperand. This predicate can be
used by machine passes after register allocation to determine whether it
is safe to rename a given register operand. Register operands that
aren't marked as renamable may be required to be assigned their current
register to satisfy constraints that are not captured by the machine
IR (e.g. ABI or ISA constraints).
Reviewers: qcolombet, MatzeB, hfinkel
Subscribers: nemanjai, mcrosier, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D39400
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320503 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/AArch64')
| -rw-r--r-- | test/CodeGen/AArch64/arm64-misched-multimmo.ll | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/test/CodeGen/AArch64/arm64-misched-multimmo.ll b/test/CodeGen/AArch64/arm64-misched-multimmo.ll index bdd4f49d174..47f2ec790c7 100644 --- a/test/CodeGen/AArch64/arm64-misched-multimmo.ll +++ b/test/CodeGen/AArch64/arm64-misched-multimmo.ll @@ -8,11 +8,11 @@ ; Check that no scheduling dependencies are created between the paired loads and the store during post-RA MI scheduling. ; ; CHECK-LABEL: # Machine code for function foo: -; CHECK: SU(2): %w{{[0-9]+}}, %w{{[0-9]+}} = LDPWi +; CHECK: SU(2): renamable %w{{[0-9]+}}, renamable %w{{[0-9]+}} = LDPWi ; CHECK: Successors: ; CHECK-NOT: ch SU(4) ; CHECK: SU(3) -; CHECK: SU(4): STRWui %wzr, %x{{[0-9]+}} +; CHECK: SU(4): STRWui %wzr, renamable %x{{[0-9]+}} define i32 @foo() { entry: %0 = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @G2, i64 0, i64 0), align 4 |