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authorHans Wennborg <hans@hanshq.net>2018-01-30 10:53:45 +0000
committerHans Wennborg <hans@hanshq.net>2018-01-30 10:53:45 +0000
commit03a6999cf40097d99d048118b632a48f320cf8b2 (patch)
tree1cd5ff8ca7077eb42547310596a26a1e162421cb /test/CodeGen/AArch64
parentf8f8b9b531ff0dc0f39b6259e288aca9824c80a2 (diff)
Merging r323710:
------------------------------------------------------------------------ r323710 | qcolombet | 2018-01-30 00:42:37 +0100 (Tue, 30 Jan 2018) | 13 lines [RAFast] Don't dereference MBB::end When RAFast sees liveins in on a basic block, it uses that information to initialize the availability of the registers. The called method uses an instruction as one of its argument and in the liveins case, RAFast was dereferencing MBB::begin which can be MBB::end for empty basic block. Change the API of definePhysReg to use MachineBasicBlock::iterator instead of MachineInstr so that we don't dereference an invalid iterator while making the call. rdar://problem/36952401 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@323746 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/AArch64')
-rw-r--r--test/CodeGen/AArch64/fast-regalloc-empty-bb-with-liveins.mir26
1 files changed, 26 insertions, 0 deletions
diff --git a/test/CodeGen/AArch64/fast-regalloc-empty-bb-with-liveins.mir b/test/CodeGen/AArch64/fast-regalloc-empty-bb-with-liveins.mir
new file mode 100644
index 00000000000..fc19173a176
--- /dev/null
+++ b/test/CodeGen/AArch64/fast-regalloc-empty-bb-with-liveins.mir
@@ -0,0 +1,26 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple aarch64-apple-ios -run-pass regallocfast -o - %s | FileCheck %s
+# This test used to crash the fast register alloc.
+# Basically, when a basic block has liveins, the fast regalloc
+# was deferencing the begin iterator of this block. However,
+# when this block is empty and it will just crashed!
+---
+name: crashing
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: crashing
+ ; CHECK: bb.0:
+ ; CHECK: successors: %bb.1(0x80000000)
+ ; CHECK: liveins: %x0, %x1
+ ; CHECK: bb.1:
+ ; CHECK: renamable %w0 = MOVi32imm -1
+ ; CHECK: RET_ReallyLR implicit killed %w0
+ bb.1:
+ liveins: %x0, %x1
+
+ bb.2:
+ %0:gpr32 = MOVi32imm -1
+ %w0 = COPY %0
+ RET_ReallyLR implicit %w0
+
+...