summaryrefslogtreecommitdiff
path: root/test/CodeGen/AArch64/tst-br.ll
diff options
context:
space:
mode:
authorTim Northover <tnorthover@apple.com>2014-04-16 11:53:07 +0000
committerTim Northover <tnorthover@apple.com>2014-04-16 11:53:07 +0000
commit1a8adcb56921d51a406c5b32b3c0c280f0edf749 (patch)
tree836ec0fe9fdc8e75dec5bd50f0ba2049b32b2a8b /test/CodeGen/AArch64/tst-br.ll
parent1a44333f0e0938532c1a40b4b6d4f5e114bcf287 (diff)
AArch64/ARM64: add another set of tests from AArch64
Another batch with no code changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206381 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/AArch64/tst-br.ll')
-rw-r--r--test/CodeGen/AArch64/tst-br.ll11
1 files changed, 6 insertions, 5 deletions
diff --git a/test/CodeGen/AArch64/tst-br.ll b/test/CodeGen/AArch64/tst-br.ll
index 154bc08c144..b6e2b19fb84 100644
--- a/test/CodeGen/AArch64/tst-br.ll
+++ b/test/CodeGen/AArch64/tst-br.ll
@@ -1,4 +1,5 @@
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
+; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64-apple-ios7.0 | FileCheck %s
; We've got the usual issues with LLVM reordering blocks here. The
; tests are correct for the current order, but who knows when that
@@ -15,7 +16,7 @@ define i32 @test_tbz() {
%tbit0 = and i32 %val, 32768
%tst0 = icmp ne i32 %tbit0, 0
br i1 %tst0, label %test1, label %end1
-; CHECK: tbz {{w[0-9]+}}, #15, [[LBL_end1:.LBB0_[0-9]+]]
+; CHECK: tbz {{w[0-9]+}}, #15, [[LBL_end1:.?LBB0_[0-9]+]]
test1:
%tbit1 = and i32 %val, 4096
@@ -27,22 +28,22 @@ test2:
%tbit2 = and i64 %val64, 32768
%tst2 = icmp ne i64 %tbit2, 0
br i1 %tst2, label %test3, label %end1
-; CHECK: tbz {{x[0-9]+}}, #15, [[LBL_end1]]
+; CHECK: tbz {{[wx][0-9]+}}, #15, [[LBL_end1]]
test3:
%tbit3 = and i64 %val64, 4096
%tst3 = icmp ne i64 %tbit3, 0
br i1 %tst3, label %end2, label %end1
-; CHECK: tbz {{x[0-9]+}}, #12, [[LBL_end1]]
+; CHECK: tbz {{[wx][0-9]+}}, #12, [[LBL_end1]]
end2:
-; CHECK: movz x0, #1
+; CHECK: {{movz x0, #1|orr w0, wzr, #0x1}}
; CHECK-NEXT: ret
ret i32 1
end1:
; CHECK: [[LBL_end1]]:
-; CHECK-NEXT: mov x0, xzr
+; CHECK-NEXT: {{mov x0, xzr|mov w0, wzr}}
; CHECK-NEXT: ret
ret i32 0
}